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Static information storage and retrieval March listing by industry category 03/12

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
03/29/2012 > 47 patent applications in 27 patent subcategories. listing by industry category

20120075902 - Identifying and accessing individual memory devices in a memory channel: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity... Agent:

20120075903 - Nonvolatile semiconductor memory: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent... Agent: Kabushiki Kaisha Toshiba

20120075904 - Semiconductor device: A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first... Agent: Elpida Memory, Inc.

20120075905 - Semiconductor memory device and semiconductor integrated circuit: A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense... Agent: Panasonic Corporation

20120075914 - Low read current architecture for memory: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.... Agent: Unity Semiconductor Corporation

20120075913 - Non-volatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder... Agent: Kabushiki Kaisha Toshiba

20120075912 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a three-dimensional cell array block in which a plurality of cell array layers are stacked, each of the cell array layers including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of memory cells... Agent: Kabushiki Kaisha Toshiba

20120075916 - Nonvolatile semiconductor memory device: A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a... Agent: Kabushiki Kaisha Toshiba

20120075906 - Resistance based memory having two-diode access device: A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the... Agent: Qualcomm Incorporated

20120075908 - Resistive random access memory and verifying method thereof: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the... Agent: Industrial Technology Research Institute

20120075907 - Resistor structure for a non-volatile memory device and method: A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and... Agent: Crossbar, Inc.

20120075910 - Semiconductor integrated circuit: According to one embodiment, a semiconductor integrated circuit includes first and second resistance change type memory element and first and second switches. The first resistance change type memory element includes a first terminal connected to a first power supply and a second terminal connected to a first node. The second... Agent: Kabushiki Kaisha Toshiba

20120075909 - Semiconductor memory device: Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that... Agent:

20120075911 - Semiconductor memory device: Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is... Agent:

20120075915 - Semiconductor storage device: A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively... Agent: Kabushiki Kaisha Toshiba

20120075917 - Semiconductor memory device and method for driving the same: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120075920 - Memory base cell and memory bank: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width... Agent: Stmicroelectronics S.r.i.

20120075919 - Methods and systems for adjusting wordline up-level voltage to improve production yield relative to sram-cell stability: Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust... Agent: International Business Machines Corporation

20120075918 - Sram having wordline up-level voltage adjustable to assist bitcell stability and design structure for same: An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that... Agent: International Business Machines Corporation

20120075922 - Magnetic memory element and storage device using the same: A magnetic memory element capable of maintaining high thermal stability (retention characteristics) while reducing a writing current. The magnetic memory element includes a magnetic tunnel junction having a first magnetic body including a perpendicular magnetization film, an insulating layer, and a second magnetic body serving as a storage layer including... Agent: Fuji Electric Co., Ltd.

20120075921 - Semiconductor device: A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow... Agent: Renesas Electronics Corporation

20120075924 - Method, apparatus and system to determine access information for a phase change memory: Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the... Agent:

20120075925 - Pcram with current flowing laterally relative to axis defined by electrodes: An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In... Agent: Macronix International Co., Ltd.

20120075923 - Phase change memory state determination using threshold edge detection: Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.... Agent: Numonyx B.v.

20120075926 - Semiconductor device: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which... Agent: Hitachi, Ltd.

20120075927 - Magnetic element having perpendicular anisotropy with enhanced efficiency: Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy, a nonmagnetic spacer layer, and a free layer having a changeable free layer magnetization and perpendicular anisotropy.... Agent: Grandis Inc.

20120075928 - Semiconductor memory device: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front... Agent: Kabushiki Kaisha Toshiba

20120075930 - Reuse of information from memory read operations: A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for... Agent: Seagate Technology LLC

20120075931 - Techniques for the fast settling of word lines in nand flash memory: In non-volatile memory devices, a write operation typically consists of an alternating set of pulse and verify operations. After a pulse is applied, the device must be biased properly for an accurate verify, with a selected word-line settled at the desired voltage level. The techniques described here address the problem... Agent:

20120075932 - Charge loss compensation during programming of a memory device: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed... Agent: Micron Technology, Inc.

20120075929 - Sensing of memory cells in nand flash: An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash... Agent: Micron Technology, Inc.

20120075933 - Programming a memory device to increase data reliability: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group... Agent: Micron Technology, Inc.

20120075934 - Access line management in a memory device: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored... Agent: Micron Technology, Inc.

20120075935 - Voltage discharge circuits and methods: Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is coupled to memory support circuitry. When a supply voltage decreases to be less than or equal to a trip voltage, the discharge circuit discharges a voltage from... Agent: Micron Technology, Inc.

20120075936 - Bit line negative potential circuit and semiconductor storage device: According to one embodiment, a bit line negative potential circuit includes a bit line capacitance compensation capacitor which compensates the capacitance of a bit line and a peripheral capacitance compensation capacitor which compensates the peripheral capacitance of the bit line. After the bit line is switched to a low potential,... Agent: Kabushiki Kaisha Toshiba

20120075937 - Semiconductor memory device: A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a... Agent: Hynix Semiconductor Inc.

20120075938 - Adaptive and dynamic stability enhancement for memories: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist... Agent:

20120075939 - Memory cells having a row-based read and/or write support circuitry: A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120075940 - Memory system: A memory system according to the embodiment comprises a cell array including word lines and plural memory cells operative to store data in accordance with plural different physical levels when selected by the word lines; a register operative to hold first data input from external; and a data converter unit... Agent: Kabushiki Kaisha Toshiba

20120075941 - Memory programming methods and memory programming devices: Memory programming devices include a print head that moves across a substrate to deposit memory material on the substrate to form an array of memory cells and programming circuitry coupled to the print head so that the programming circuitry moves across the substrate along with the print head and that,... Agent:

20120075942 - Row address decoder and semiconductor memory device having the same: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row... Agent: Hynix Semiconductor Inc.

20120075943 - Method and apparatus for memory repair with redundant columns: A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the... Agent: Macronix International Co., Ltd.

20120075944 - Semiconductor device and manufacturing method thereof: A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at... Agent: Elpida Memory, Inc.

20120075946 - Memory device with phase distribution circuit for controlling relative durations of precharge and active phases: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor... Agent:

20120075945 - Passgate for dynamic circuitry: A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the second bit... Agent:

20120075947 - Semiconductor memory devices having self-refresh capability: A semiconductor memory device is provided. The semiconductor memory device includes at least one memory bank including a plurality of memory cells and a self-refresh controller configured to generate a refresh address and to output a row address for a page to be refreshed based on the refresh address. The... Agent:

20120075948 - Method and apparatus for managing behavior of memory devices: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed... Agent:

  
03/22/2012 > 74 patent applications in 31 patent subcategories. listing by industry category

20120069620 - System including vertically stacked embedded non flash re writable non volatile memory: A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked... Agent: Unity Semiconductor Corporation

20120069621 - Integrated circuits using non volatile resistivity sensitive memory for emulation of embedded flash memory: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element,... Agent: Unity Semiconductor Corporation

20120069623 - Ferroelectric memory: One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage... Agent: Kabushiki Kaisha Toshiba

20120069622 - Sector array addressing for ecc management: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at... Agent:

20120069632 - Current control, memory element, memory device, and production method for current control element:

20120069631 - Memory element and memory device: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is... Agent: Sony Corporation

20120069627 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of... Agent: Kabushiki Kaisha Toshiba

20120069628 - Nonvolatile semiconductor memory device and method of controlling the same: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell which includes a variable resistance element and a current-limiting element that has a nonlinear current-voltage characteristic and a driver which changes the resistance of the variable resistance element by causing a first current to flow in the... Agent:

20120069633 - Nonvolatile storage device and method for writing into the same: The nonvolatile storage device includes a variable resistance element (106) and a write circuit (101) which writes data into the variable resistance element, wherein the variable resistance element has a property of changing from a first resistance state (LR state or HR state) to a second resistance state (HR state... Agent:

20120069624 - Reactive metal implated oxide based memory: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming... Agent: Micron Technology, Inc.

20120069625 - Resistance change element and resistance change memory: According to one embodiment, a resistance change element includes a first film provided on a first electrode side, a second film provided on a second electrode side, a barrier film sandwiched between the first film and the second film, and metal impurities added in the first or second film, the... Agent:

20120069626 - Semiconductor memory device: The invention provides a semiconductor memory device including a variable resistance element capable of decreasing a variation of a resistance value of stored data due to a large number of times of switching operations and capable of performing a stable writing operation. The device has a circuit that applies a... Agent:

20120069629 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same... Agent:

20120069630 - Write verify method for resistive random access memory: Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and applying a forward resetting voltage pulse across... Agent: Seagate Technology LLC

20120069635 - Capacity and density enhancement circuit for sub-threshold memory unit array: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask... Agent: Southeast University

20120069634 - Semiconductor memory device and method for inspecting the same: When the threshold voltage Vth of the transistor in the memory cell is within the allowable range is determined, a memory cell which does not have sufficient data retention characteristics is eliminated. In order to eliminate such a memory cell, the potential of a gate of the transistor is kept... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120069636 - Static random access memory (sram) having bit cells accessible by separate read and write paths: A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of... Agent:

20120069637 - Semiconductor memory device and semiconductor device: An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power supply corresponding... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120069641 - Magnetic memory: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is... Agent:

20120069640 - Magnetoresistive element and magnetic memory: A magnetoresistive element according to an embodiment includes: a first and second magnetic layers having an easy axis of magnetization in a direction perpendicular to a film plane; and a first nonmagnetic layer interposed between the first and second magnetic layers, at least one of the first and second magnetic... Agent: Kabushiki Kaisha Toshiba

20120069642 - Magnetoresistive element and magnetic random access memory: According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to... Agent: Kabushiki Kaisha Toshiba

20120069643 - Non-uniform switching based non-volatile magnetic based memory: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free... Agent: Avalanche Technology, Inc.

20120069638 - Semiconductor device: A semiconductor device which it can accommodate variations in a write current threshold in each memory cell and can secure a write margin is provided. An MRAM device includes an MTJ memory cell arranged in a matrix, plural bit lines each arranged corresponding to a memory cell column, plural digit... Agent: Renesas Electronics Corporation

20120069639 - Semiconductor storage device: A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device... Agent: Kabushiki Kaisha Toshiba

20120069645 - Multiple bit phase change memory cell: A phase change memory cell has more than one memory region (14,18) each being a narrowed region of phase change memory material (2) extending between first and second electrodes (4,6). Each of the plurality of memory regions (14, 18) can be programmed to be in a low resistance state or... Agent: Nxp B.v.

20120069644 - Replaceable, precise-tracking reference lines for memory products: Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or... Agent: Magic Technologies, Inc.

20120069649 - Non-uniform switching based non-volatile magnetic based memory: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free... Agent: Avalanche Technology, Inc.

20120069646 - Spin torque transfer memory cell structures and methods: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic... Agent: Micron Technology, Inc.

20120069647 - Spin torque transfer memory cell structures and methods: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more SIT memory cell structures comprise a STT stack including; a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a... Agent: Micron Technology, Inc.

20120069648 - Spin torque transfer memory cell structures and methods: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and... Agent: Micron Technology, Inc.

20120069650 - Sub-threshold memory cell circuit with high density and high robustness: A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the... Agent: Southeast University

20120069654 - Memory device and method for estimating characteristics of multi-bit programming: Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data... Agent:

20120069653 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage... Agent: Kabushiki Kaisha Toshiba

20120069652 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data... Agent:

20120069655 - Nonvolatile semiconductor memory device: A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor... Agent: Kabushiki Kaisha Toshiba

20120069656 - Semiconductor storage device: A memory includes plurality of word lines extending in a first direction, plurality of bit lines extending in a second direction to intersect with the word lines, and a memory cell array including plurality of memory cells connected to the word lines and the bit lines. Plurality of sense amplifiers... Agent: Kabushiki Kaisha Toshiba

20120069657 - Memory device and self interleaving method thereof: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.... Agent:

20120069659 - Memory with interleaved read and redundant columns: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality... Agent: Micron Technology, Inc.

20120069658 - Methods, devices, and systems for dealing with threshold voltage change in memory devices: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated... Agent: Micron Technology, Inc.

20120069664 - Flash memory system and word line interleaving method thereof: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation... Agent:

20120069665 - Memory device with vertically embedded non flash non volatile memory for emulation of nand flash memory: A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory... Agent: Unity Semiconductor Corporation

20120069660 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first... Agent: Kabushiki Kaisha Toshiba

20120069661 - Nonvolatile semiconductor memory device: A control circuit during an erase operation sets a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage, sets a voltage... Agent: Kabushiki Kaisha Toshiba

20120069663 - Nonvolatile semiconductor memory device: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the... Agent: Kabushiki Kaisha Toshiba

20120069662 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes memory cell units including serially-connected memory cells, which includes a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar. The memory cell units constitute blocks each of which is the minimum unit of data erasure. A pipe layer in... Agent:

20120069666 - Memory system: A memory system includes a controller and a memory part including a memory cell array including memory cells, word lines, bit lines including bit line pairs each composed of an even bit line and an odd bit line adjacent to each other, and sense amplifiers provided to the bit line... Agent: Kabushiki Kaisha Toshiba

20120069667 - Nonvolatile semiconductor memory device capable of speeding up data write: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array having a plurality of memory cells is connected to a plurality of word lines stacked on a semiconductor substrate, and the memory cells having a charge accumulation layer,... Agent:

20120069671 - Memory and operation method therefor: An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get... Agent: Macronix International Co., Ltd.

20120069669 - Nonvolatile semiconductor storage device and method of controlling and manufacturing the same: A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell... Agent: Kabushiki Kaisha Toshiba

20120069668 - Semiconductor device: According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged to the first voltage by... Agent:

20120069670 - Semiconductor integrated circuit device for driving liquid crystal display: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable... Agent: Renesas Electronics Corporation

20120069674 - Flash memory device and related program verification method: A nonvolatile memory device performs a program operation using an incremental pulse programming (ISPP) scheme in which a plurality of program loops alternate between a coarse-fine verify operation, and a fine verify operation according to a value of a program loop counter.... Agent: Samsung Electronics Co., Ltd.

20120069673 - Method and device for programming data into non-volatile memories: A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal.... Agent: Infineon Technologies Ag

20120069672 - Nonvolatile semiconductor memory device and operating method thereof: A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell... Agent: Kabushiki Kaisha Toshiba

20120069675 - Reducing noise in semiconductor devices: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the... Agent: Micron Technology, Inc.

20120069651 - Eeprom-based, data-oriented combo nvm design: A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the... Agent: Aplus Flash Technoloy, Inc.

20120069676 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a... Agent:

20120069677 - Nonvolatile memory device and erasure method thereof: A nonvolatile memory device comprises a cell array comprising a plurality of memory cells wherein the memory cells have a desired threshold voltage distribution for a state of being erased, wherein the distribution spreads over between a lower bound verification voltage and an upper bound verification voltage, a voltage generator... Agent:

20120069680 - Nand with back biased operation: Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of... Agent: Micron Technology, Inc.

20120069679 - Nonvolatile semiconductor memory device and method for driving same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell.... Agent: Kabushiki Kaisha Toshiba

20120069678 - Nonvolatile semiconductor storage device and method for driving the same: A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction,... Agent: Kabushiki Kaisha Toshiba

20120069681 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes a cell array, a controller, and a voltage generator. The cell array includes cells. Each of the cells holds data “0” or “1”. The controller counts the number of times N of sequentially writing the data into the cells. The controller... Agent:

20120069683 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to... Agent:

20120069682 - Word line booster for flash memory device: A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20120069686 - Latch timing adjustment device and memory access system using the same: A latch timing adjustment device includes: first to third variable delay sections configured to delay a strobe signal by first to third variable delay amounts, respectively; first to third data latch sections configured to latch a data signal in response to the outputs of the first to third variable delay... Agent: Panasonic Corporation

20120069685 - Semiconductor device having optical fuse and electrical fuse: A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second... Agent: Elpida Memory, Inc.

20120069684 - Semiconductor integrated circuit: According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column... Agent: Kabushiki Kaisha Toshiba

20120069687 - Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device: A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals synchronous mode information including a selected one of selection and non-selection modes, the selection... Agent: Elpida Memory, Inc.

20120069691 - Block repair scheme: Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with... Agent: Micron Technology, Inc.

20120069689 - Built-in self repair for memory: A method for repairing a memory includes running a built-in self-test of the memory to find faulty bits. A first repair result using a redundant row block is calculated. A second repair result using a redundant column block is calculated. The first repair result and the second repair result are... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120069688 - Implementing single bit redundancy for dynamic sram circuit with any bit decode: A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to... Agent: International Business Machines Corporation

20120069690 - Semiconductor integrated circuit and control method: A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value... Agent: Renesas Electronics Corporation

20120069692 - Semiconductor device: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state... Agent: Renesas Electronics Corporation

20120069693 - Dynamic random access memory and boosted voltage producer therefor: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump... Agent: Mosaid Technologies Incorporated

  
03/15/2012 > 68 patent applications in 35 patent subcategories. listing by industry category

20120063189 - Longest prefix match internet protocol content addressable memories and related methods: Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.... Agent: Arizona Board Of Regents For And On Behalf Of Arizona State University

20120063190 - Complex semiconductor device for use in mobile equipment: Provided is a complex semiconductor device. The complex semiconductor device includes first memory chips in a first package, second memory chips in a second package configured for mass storage of data, and a controller packaged with either the first package or the second package in a complex package. The controller... Agent: Samsung Electronics Co., Ltd.

20120063191 - Performing data operations using non volatile third dimension memory: Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the... Agent: Unity Semiconductor Corporation

20120063200 - Dual ported non volatile fifo with third dimension memory: A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that... Agent: Unity Semiconductor Corporation

20120063198 - Methods of forming memory cells and methods of forming programmed memory cells: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change... Agent: Micron Technology Inc.

20120063193 - Multi-level resistance change memory: According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width... Agent:

20120063201 - Nonvolatile memory element, production method therefor, design support method therefor, and nonvolatile memory device: A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes... Agent:

20120063195 - Reconfigurable multi-level sensing scheme for semiconductor memories: A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value... Agent: International Business Machines Corporation

20120063196 - Resistive memory device and method of controlling refresh operation of resistive memory device: A resistive memory device comprises a memory cell array comprising a plurality of memory units. The memory device performs a refresh read operation to check a condition of each of the memory units. Then, it determines whether to refresh each memory unit based on data read by performing the refresh... Agent: Samsung Electronics Co., Ltd.

20120063199 - Semiconductor device: A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from... Agent:

20120063194 - Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by... Agent: Samsung Electronics Co., Ltd.

20120063197 - Switchable junction with an intrinsic diode formed with a voltage dependent resistor: A switchable junction (600) having an intrinsic diode (634) formed with a voltage dependent resistor (640) is disclosed. The switchable junction comprises a first electrode (618), a second electrode (622), and a memristive matrix (620) configured to form an electrical interface (626) with the first electrode (618). The electrical interface... Agent:

20120063192 - Three-device non-volatile memory cell: A three-device non-volatile memory cell includes a first resistive device, a second resistive device connected to the first resistive device in a mutual complementary manner, and a third resistive device connected to both said first resistive device and said second resistive device in a mutual complementary manner. A memory array... Agent:

20120063202 - 3t dram cell with added capacitance on storage node: A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a... Agent: Texas Instruments Incorporated

20120063203 - Driving method of semiconductor device: A driving method of a semiconductor device is provided. In a semiconductor device including a bit line, a selection line, a selection transistor, m (m is a natural number greater than or equal to 2) writing word lines, m reading word lines, a source line, and first to m-th memory... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063208 - Memory device: In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063209 - Memory device and semiconductor device: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063204 - Semiconductor device: One object is to provide a novel semiconductor device which can hold stored data even when not powered and which has an unlimited number of writing operations. Another object is to reduce a circuit size and to improve reliability of writing and reading of data. When a memory cell using... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063205 - Semiconductor device: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063207 - Semiconductor device: An object of one embodiment of the present invention is to miniaturize a semiconductor device. Another object of one embodiment of the present invention is to reduce the area of a driver circuit of a semiconductor device including a memory element. A plurality of cells in which the positions of... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063206 - Semiconductor memory device: An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120063211 - Method for improving writability of sram memory: A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging... Agent: Stichting Imec Nederland

20120063210 - Semiconductor device: Provided is a semiconductor device including an SRAM memory cell that includes: a first inverter and a second inverter that are connected to a single power-supply node and are cross-coupled to each other; a first transfer transistor; and a second transfer transistor. A predetermined voltage is applied from a voltage... Agent: Kabushiki Kaisha Toshiba

20120063212 - Semiconductor device and method of manufacturing the same: According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the... Agent: Kabushiki Kaisha Toshiba

20120063213 - Semiconductor storage device and method of fabricating the same: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first... Agent: Renesas Electronics Corporation

20120063217 - Memory element and memory device: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between... Agent: Sony Corporation

20120063214 - Pulse field assisted spin momentum transfer mram design: An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and... Agent: Magic Technologies, Inc.

20120063215 - Semiconductor storage device: A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device... Agent: Kabushiki Kaisha Toshiba

20120063216 - Semiconductor storage device: A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in... Agent: Kabushiki Kaisha Toshiba

20120063219 - Magnetic vortex storage device: A magnetic storage device includes a network of planar magnetic cells in a vortex state, each cell's vortex core having a magnetization with either a first and second equilibrium position in opposite direction and perpendicular to the cellular plane, each of the two positions representing binary information. The device includes... Agent: Commissariat A L'energie Atomique Et Aux Energies Alternatives

20120063218 - Spin-transfer torque magnetic random access memory with perpendicular magnetic anisotropy multilayers: A spin-torque transfer memory random access memory (STTMRAM) element includes a composite fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer, the magnetization direction of each of the composite free layer... Agent: Avalanche Technology, Inc.

20120063220 - Memory element and memory device: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an... Agent: Sony Corporation

20120063221 - Memory element and memory device: There is disclosed a memory element including a layered structure including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer; and an insulating layer provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of a layered structure,... Agent: Sony Corporation

20120063222 - Memory element and memory device: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between... Agent: Sony Corporation

20120063223 - Most compact flotox-based combo nvm design without sacrificing eeprom endurance cycles for 1-die data and code storage: Disclosed is a low-cost hybrid storage solution that allows Code like sector-alterable NOR and Data like block-alterable NAND and byte-alterable EEPROM being integrated on a same die. The disclosed combo NVM design of the present invention is a truly Data-oriented NVM design that allows 2T-EEPROM to integrate both 0.5T-NAND and... Agent: Aplus Flash Technology, Inc.

20120063224 - Nonvolatile semiconductor memory: According to one embodiment, a nonvolatile semiconductor memory includes a source line connected to first and second cell units, a cell-source driver setting the source line on a fixed potential in a programming, a data latch circuit temporary storing program data, a hookup circuit connecting one of the first and... Agent:

20120063225 - Reading data from memory cells including storing charges to analog storage devices: Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored charge.... Agent: Micron Technology, Inc.

20120063226 - Small unit internal verify read in a memory device: Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected... Agent: Micron Technology, Inc.

20120063227 - System and method for adjusting read voltage thresholds in memories: A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality... Agent:

20120063228 - Data sensing arrangement using first and second bit lines: Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing... Agent: Macronix International Co., Ltd.

20120063229 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register,... Agent:

20120063231 - Apparatus, system, and method for non-volatile storage element programming: Methods, storage controllers, and systems for non-volatile storage element programming are described. One method includes programming user data in pages associated with a set of wordlines of an erase block of a non-volatile, solid-state storage element. The method further includes selecting at least one of the wordlines of the set... Agent: Fusion-io, Inc.

20120063230 - Trench monos memory cell and array: The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode.... Agent: Trom

20120063232 - Method and apparatus for reducing read disturb in memory: Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.... Agent: Macronix International Co., Ltd.

20120063233 - Eeprom-based, data-oriented combo nvm design: A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the... Agent: Aplus Flash Technology, Inc.

20120063234 - Memory system having nonvolatile semiconductor memories: According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The... Agent:

20120063235 - Memory devices for reducing boosting charge leakage and systems including the same: A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.... Agent: Samsung Electronics Co., Ltd.

20120063236 - Method and apparatus for reducing read disturb in memory: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series... Agent: Macronix International Co., Ltd.

20120063237 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a memory block including a plurality of memory cells grouped by word lines, an operation circuit group configured to perform a program operation or a read operation for the memory cells, and a control circuit configured to control the operation circuit group to set each... Agent:

20120063238 - Pre-charge sensing scheme for non-volatile memory (nvm): The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such... Agent:

20120063240 - Memory system supporting input/output path swap: A memory system includes a controller having first and second input/output terminals, and first and second memory devices each having first and second input/output terminals. The system includes a path selection mechanism for selectively employing one of the first and second terminals of either the controller or the first memory... Agent: Samsung Electronics Co., Ltd.

20120063241 - Semiconductor device and control method thereof: A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit... Agent: Elpida Memory, Inc.

20120063242 - Data receiver and semiconductor memory device including the same: A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially... Agent:

20120063243 - Apparatus and method for data capture using a read preamble: A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and... Agent: Spansion LLC

20120063244 - Voltage generator, nonvolatile memory device comprising voltage generator, and method of operating voltage generator: A voltage generator comprises a first booster that generates a first high voltage, and a second booster that generates a second high voltage by boosting an external voltage. The first booster comprises a comparator that controls a boosting operation with reference to the fed back first high voltage and uses... Agent: Samsung Electronics Co., Ltd.

20120063245 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device according to an embodiment includes a write/erase unit, during data write or erase, the write/erase unit supplying a first electric pulse to a selected memory cell, the first electric pulse having an electric energy to an extent that an physical state of a memory element... Agent: Kabushiki Kaisha Toshiba

20120063239 - Circuitry and method for indicating a memory: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of... Agent: Unity Semiconductor Corporation

20120063246 - Memory controller, memory system including the same, and control method of memory device: One aspect of the present invention is a memory controller which controls a memory device including two or more memory access units and includes a data control circuit and an adjusting circuit that performs at least one of a first processing and a second processing. In the first processing, a... Agent: Nec Computertechno, Ltd.

20120063247 - Temperature sensing circuit and semiconductor memory device using the same: A temperature sensing circuit comprises a temperature sensing unit for generating a reference voltage having a constant level, regardless of a temperature fluctuation, and a variable voltage to be changed according to the temperature fluctuation, and a comparison unit for comparing the reference voltage to the variable voltage, detecting an... Agent: Hynix Semiconductor Inc.

20120063248 - Low cost comparator design for memory bist: A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured... Agent: Lsi Corporation

20120063249 - Memory and method for sensing data in a memory using complementary sensing scheme: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a... Agent: Freescale Semiconductor, Inc.

20120063250 - Non-volatile memory device and charge pump circuit for the same: A charge pump apparatus comprises a plurality of charge pump stages. The charge pump stages each include a respective output node. Output nodes are connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state... Agent: Macronix International Co., Ltd.

20120063251 - Semiconductor device, method of adjusting load capacitance for the same, and semiconductor system including the same: A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to... Agent:

20120063252 - Variability resilient sense amplifier with reduced energy consumption: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage... Agent: Katholieke Universiteit Leuven

20120063253 - Optical memory device and method of recording/reproducing information by using the same: An optical memory device and a method of recording/reproducing information by using the optical memory device. The optical memory device includes a substrate; a first barrier layer formed on the substrate; a quantum well layer; a second barrier layer; a quantum dot layer; and a third barrier layer. The quantum... Agent: Samsung Electronics Co., Ltd.

20120063254 - Voltage regulator for memory: A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When... Agent:

20120063255 - Storage device, electronic device, and storage device control method: According to one embodiment, a storage device includes a volatile memory, an auxiliary power source, a nonvolatile memory, a write module, and an inhibition module. The volatile memory stores user data. The auxiliary power source supplies power to the volatile memory when power from a main power source is cut... Agent: Kabushiki Kaisha Toshiba

20120063256 - Memory device word line drivers and methods: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such... Agent: Micron Technology, Inc.

  
03/08/2012 > 36 patent applications in 27 patent subcategories. listing by industry category

20120057389 - Memory system and method of operating the same: A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data... Agent:

20120057392 - High density non-volatile information storagehigh density non-volatile information storage: The present invention provides for a composition comprising a nanostructure comprising a semiconductor component and a metallic component, with the proviso that when the semiconductor component is Ge the metallic component is not Te. The nanostructure can be in one of two types of structures: (1) a segregated structure, and... Agent: The Regents Of The University Of California

20120057390 - Memory array with write feedback: A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a... Agent:

20120057391 - Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively... Agent:

20120057393 - Reading a phase change memory: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some... Agent:

20120057394 - Securing non volatile data in an embedded memory device: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension... Agent: Unity Semiconductor Corporation

20120057397 - Method for driving semiconductor device: In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120057396 - Semiconductor device and driving method of semiconductor device: An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is provided with both a memory circuit including a transistor including an oxide semiconductor (in a broader... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120057395 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word lines, a cell plate electrode formed over a whole area of the cell block, and a plate power... Agent: Hynix Semiconductor Inc.

20120057398 - Sram device: An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a... Agent: National Institute Of Advanced Industrial Science And Technology

20120057399 - Asymmetric virtual-ground single-ended sram and system thereof: The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the... Agent:

20120057400 - System and method for shared sensing mram: Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array,... Agent: Qualcomm Incorporated

20120057401 - Phase change memory cycle timer and method: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a... Agent: International Business Machines Corporation

20120057402 - Write driver, semiconductor memory apparatus using the same and programming method: A write driver, a semiconductor memory apparatus using the same, and a programming method. The write driver includes a reset control unit configured to output a first current pulse for a first period of time and subsequently output a second current pulse having a higher current level than the first... Agent:

20120057403 - Memory element and memory device: There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and... Agent: Sony Corporation

20120057404 - Memory device and method having charge level assignments selected to minimize signal coupling: A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in... Agent: Micron Technology, Inc.

20120057405 - Semiconductor memory device: According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory... Agent:

20120057406 - Flash memory apparatus: A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory... Agent: Eon Silicon Solution Inc.

20120057407 - Caching scheme synergy for extent migration between tiers of a storage system and methods thereof: A storage system according to one embodiment includes logic adapted for determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a set of tracks of the extent is presently being accessed; logic adapted for determining whether any track from... Agent: International Business Machines Corporation

20120057408 - Analog read and write paths in a solid state memory device: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage... Agent: Micron Technology, Inc.

20120057409 - Nonvolatile memory device and method of reading the same: A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells,... Agent: Hynix Semiconductor Inc.

20120057410 - Method and apparatus for the erase suspend operation: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program... Agent: Macronix International Co., Ltd.

20120057411 - Latch based memory device: A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the... Agent:

20120057414 - Data input circuit of nonvolatile memory device: The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch... Agent:

20120057412 - Memory macro configuration and method: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120057413 - Semiconductor memory apparatus and test method thereof: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to... Agent: Hynix Semiconductor Inc.

20120057415 - Nonvolatile memory device: A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer... Agent:

20120057416 - Sram leakage reduction circuit: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where... Agent:

20120057417 - Semiconductor memory apparatus and method for controlling programming current pulse: A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a... Agent: Hynix Semiconductor Inc.

20120057418 - Memories and methods for sharing a signal node for the receipt and provision of non-data signals: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to... Agent: Micron Technology, Inc.

20120057419 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes an address controller for storing fail column addresses and sequentially outputting the fail column addresses while a first control signal is activated and a control logic for performing control so that data indicating a program pass is inputted to each of main page buffers associated... Agent: Hynix Semiconductor Inc.

20120057420 - Semiconductor memory and method for testing the same: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the... Agent: Fujitsu Semiconductor Limited

20120057421 - Devices and system providing reduced quantity of interconnections: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion... Agent: Micron Technology, Inc.

20120057422 - Low power sense amplifier for reading memory: A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.... Agent: Atmel Corporation

20120057423 - Electrical fuse memory arrays: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120057424 - Memory device having multiple power modes: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is... Agent:

  
03/01/2012 > 62 patent applications in 32 patent subcategories. listing by industry category

20120051112 - Memory devices having break cells: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120051111 - Printed board assembly movement detection: A system may include a first connector housing, a magnetic data storage device mechanically coupled to the first connector housing, a second connector housing configured to be mechanically engaged with the first connector housing, and a permanent magnet mechanically coupled to the second cavity. In some examples, relative motion between... Agent: Honeywell International Inc.

20120051113 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of slave chips each including a core area including a memory cell array, a global data line configured to transfer input/output data of the corresponding core area, and a first peripheral circuit area configured to interface the corresponding core area and the corresponding... Agent:

20120051114 - Non-volatile memory device: A non-volatile memory device for performing a sensing operation using a current signal includes a cell array, a current-voltage converter, and a sense amplifier. The cell array includes at least one unit cell so as to read or write data. The current-voltage converter converts a sensing current corresponding to data... Agent: Hynix Semiconductor Inc.

20120051115 - Resistance changing memory cell architecture: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along... Agent: Spansion LLC

20120051116 - Driving method of semiconductor device: A semiconductor device with a novel structure and a driving method thereof are provided. A semiconductor device includes a non-volatile memory cell including a writing transistor including an oxide semiconductor, a reading p-channel transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120051120 - Driving method of semiconductor device: A driving method by which stored data can be retained even with no power supply and the number of writing operations is not limited is provided. The variation of a writing potential to a memory element is suppressed to improve the reliability according to a new driving method. According to... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120051118 - Memory device and semiconductor device: A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120051119 - Semiconductor device: An object is to provide a semiconductor device which includes a memory cell capable of holding accurate data even when the data is multilevel data. The semiconductor device includes a memory cell holding data in a node to which one of a source and a drain of a transistor whose... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120051117 - Signal processing circuit and method for driving the same: An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element includes two logic elements (referred to as a first phase-inversion element and a second phase-inversion element) which invert a phase of an input signal and... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120051121 - Power gateable retention storage element: A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data... Agent: Advanced Micro Devices, Inc.

20120051122 - Semiconductor device: A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell... Agent:

20120051125 - Multilayer structures having memory elements with varied resistance of switching layers: A multilayer structure is provided that includes a base and a multilayer circuit disposed above the base. The multilayer circuit includes memory elements, each including a switching layer, and conductive lines leading from the base to the memory element. The total resistance of the switching layer of a memory element... Agent:

20120051123 - Phase change memory structures and methods: Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first... Agent: Micron Technology, Inc.

20120051124 - Phase change memory structures and methods: Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material,... Agent: Micron Technology, Inc.

20120051126 - Semiconductor memory apparatus and data reading method thereof: A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a resistance value thereof in a data read mode; a voltage transfer unit coupled between the read current supply unit... Agent: Hynix Semiconductor Inc.

20120051127 - System for handling data in a semiconductor memory apparatus: A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data... Agent: Hynix Semiconductor Inc.

20120051128 - Magnetically coupled electrostatically shiftable memory device and method: A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate structure and a surface that are magnetically coupled (e.g., an electrostatic force to decouple the separate structure and the surface is generated with an electrode),... Agent:

20120051129 - Memory device having three-dimensional gate structure: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.... Agent: Numonyx B.v.

20120051131 - Efficient method of replicate memory data with virtual port solution: A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is... Agent: Oracle International Corporation

20120051132 - Memory cell structures and methods: Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and... Agent: Micron Technology, Inc.

20120051134 - Nonvolatile semiconductor memory device and method testing the same: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches... Agent: Kabushiki Kaisha Toshiba

20120051133 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device includes a memory cell array which comprises a plurality of blocks each comprising a plurality of memory cells, ordinary data being stored in ordinary blocks included in the plurality of blocks, a time code which is set for each of the ordinary blocks and which... Agent: Kabushiki Kaisha Toshiba

20120051135 - Flash memory device and operating method thereof: A flash memory device includes a memory cell string including a plurality of memory cells serially coupled to one another between a bit line and a source line, a page buffer configured to perform a precharging operation and a sensing operation with respect to the bit line, and a power... Agent:

20120051137 - Memory architecture of 3d array with diode in memory string: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of... Agent: Macronix International Co., Ltd.

20120051136 - Nonvolatile memory device, operating method thereof and memory system including the same: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation to second memory cells associated with a second word line (WL)... Agent:

20120051138 - Nonvolatile memory device, operating method thereof and memory system including the same: A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the... Agent:

20120051139 - Reducing read failure in a memory device: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain... Agent: Micron Technology, Inc.

20120051141 - Multi-bit flash memory devices and methods of programming and erasing the same: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further... Agent:

20120051140 - Ram memory device with nand type interface: A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any random access storage technology including PRAM,... Agent:

20120051130 - System and method for detecting disturbed memory cells of a semiconductor memory device: A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the... Agent: Macronix International Co., Ltd.

20120051143 - Nonvolatile memory device, operating method thereof and memory system including the same: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a... Agent:

20120051142 - Soft program method and computer redable medium thereof: A soft program method is provided for recovering memory cells of a memory array. In an embodiment, the method includes the following steps. Memory blocks of the memory array are soft programmed with first bias voltage. A selected memory unit within a selected memory block is then soft programmed with... Agent: Macronix International Co., Ltd.

20120051144 - System and method for accelerated sampling: A system and method for reading memory cells in a multi-level cell memory device. A set of thresholds may be received for reading a current page of the memory cells. The set of threshold may include hard decision thresholds for hard decoding, soft decision thresholds for soft decoding, erase thresholds... Agent:

20120051145 - Semiconductor memory device and method of operating the same: A memory device includes a block switch for transferring operating voltages, supplied to global lines, to local lines coupled to a memory cell array in response to the voltage level of a block selection signal and a negative voltage transfer circuit for transferring a negative voltage as the block selection... Agent: Hynix Semiconductor Inc.

20120051146 - Semiconductor memory device capable of memorizing multivalued data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality... Agent:

20120051147 - Area saving electrically-erasable-programmable read-only memory (eeprom) array: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines and a second... Agent: Yield Microelectronics Corp.

20120051149 - Semiconductor apparatus and data write circuit of semiconductor apparatus: A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals... Agent:

20120051148 - Voltage signals multiplexer: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first... Agent: Stmicroelectronics S.r.l.

20120051151 - Memory write assist: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120051150 - Modified read operation for non-volatile memory: Subject matter disclosed herein relates to a read operation process for a nonvolatile memory.... Agent: Numonyx B.v.

20120051153 - Block control command generation circuit: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first... Agent: Hynix Semiconductor Inc.

20120051152 - Buffer die in stacks of memory dies and methods: Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one... Agent:

20120051154 - Fuse circuit, fuse array, semiconductor memory device and method of manufacturing semiconductor device: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and... Agent: Samsung Electronics Co., Ltd.

20120051155 - Process variation compensated multi-chip memory package: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection... Agent: Samsung Electronics Co., Ltd.

20120051157 - Semiconductor device: In a semiconductor device, a reference voltage generating unit generates a first reference voltage adjusted in accordance with trimming data and a second reference voltage that does not depend on the trimming data based on an external power source voltage. A nonvolatile memory operates in accordance with a voltage based... Agent: Renesas Electronics Corporation

20120051156 - Semiconductor memory device: A semiconductor memory device includes a pre-charger configured to pre-charge a first pair of differential bus lines SIO and SIOb to a target voltage level, an amplifier configured to amplify a signal loaded on the first pair of the differential bus lines SIO and SIOb based on a drain bias... Agent:

20120051158 - Voltage signals switching circuit: A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal or to the second input voltage signal... Agent: Stmicroelectronics S.r.l.

20120051159 - Synchronous semiconductor memory device: A synchronous semiconductor memory device includes a data alignment reference pulse generation unit configured to generate a data alignment reference pulse in response to a data strobe signal, a data alignment suspension signal generation unit configured to generate a data alignment suspension signal in response to the data alignment reference... Agent:

20120051160 - Multiple bitcells tracking scheme for semiconductor memories: A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120051161 - Memory devices and methods of operating memory: Methods and apparatus for synchronizing a delay locked loop, such as delay locked loops used with NAND memories are disclosed. In at least one embodiment, one or both of a clock and the delay locked loop are stopped for energy savings. A synchronization start signal can be provided by the... Agent: Micron Technology, Inc.

20120051164 - Memory cell, methods of manufacturing memory cell, and memory device having the same: A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit... Agent:

20120051162 - Method and apparatus for bit cell repair: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120051165 - Redundancy control circuit and memory device including the same: A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a... Agent:

20120051166 - Self-repair integrated circuit and repair method: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region.... Agent: International Business Machines Corporation

20120051163 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes an enable fuse unit configured to generate a repair enable signal corresponding to a cutting state of an enable fuse after a power-up operation starts, and an address fuse unit enabled in response to the repair enable signal, and configured to generate an output signal... Agent:

20120051167 - Semiconductor memory device: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first... Agent:

20120051168 - Circuit and method for controlling self-refresh operation in semiconductor memory device: A self-refresh control circuit includes: a code generator configured to generate a code by counting periods of a periodic wave based on a self-refresh signal and reset when a code value of the generated code reaches a first value; a bank active signal generator configured to generate a plurality of... Agent:

20120051169 - Refresh control circuit and semiconductor memory apparatus using the same: Disclosed is a refresh control circuit for activating a plurality of bank selection signals in response to a refresh command signal. Each of the plurality of bank selection signals is assigned to one of a plurality of bank groups. The refresh control circuit is configured to activate the plurality of... Agent: Hynix Semiconductor Inc.

20120051170 - Non-volatile memory device: A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the... Agent: Hynix Semiconductor Inc.

20120051171 - Channel skewing: Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding... Agent: Micron Technology, Inc.

20120051172 - Shift circuit of a semiconductor device: A shift circuit of a semiconductor device reduces the power consumption of the semiconductor device. The shift circuit comprises a plurality of shifters and a plurality of clock controllers. The plurality of shifters shifts an input signal in sequence in response to a clock. The plurality of clock each supply... Agent:

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