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Static information storage and retrieval February patent applications/inventions, industry category 02/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/23/2012 > 48 patent applications in 25 patent subcategories. patent applications/inventions, industry category
20120044733 - Single device driver circuit to control three-dimensional memory element array: A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers... Agent: Sandisk 3d LLC
20120044734 - Bit line sense amplifier layout array, layout method, and apparatus having the same: A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an ith sense amplifier layout region among the sense amplifier layout regions. An ith... Agent:
20120044735 - Structures with increased photo-alignment margins: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in... Agent: Round Rock Research, LLC.
20120044736 - Memory devices using a plurality of diodes as program selectors for memory cells: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to... Agent:
20120044739 - Circuit and system of using junction diode as program selector for one-time programmable devices: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can... Agent:
20120044737 - Circuit and system of using polysilicon diode as program selector for one-time programmable devices: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can... Agent:
20120044740 - One-time programmable memories using junction diodes as program selectors: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P... Agent:
20120044738 - One-time programmable memories using polysilicon diodes as program selectors: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The... Agent:
20120044741 - Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is... Agent: Renesas Electronics Corporation
20120044751 - Bipolar resistive-switching memory with a single diode per memory cell: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage... Agent: Intermolecular, Inc.
20120044746 - Circuit and system of using a junction diode as program selector for resistive devices: Junction diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+ and N+ active regions on an... Agent:
20120044743 - Circuit and system of using a polysilicon diode as program selector for resistive devices in cmos logic processes: Polysilicon diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+/N+ implants on a polysilicon as a... Agent:
20120044744 - Programmably reversible resistive device cells using polysilicon diodes: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices such as PCRAM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+/N+ implants on a... Agent:
20120044747 - Reversible resistive memory using diodes formed in cmos processes as program selectors: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible... Agent:
20120044745 - Reversible resistive memory using polysilicon diodes as program selectors: Embodiments of reversible resistive memory cells using polysilicon diodes are disclosed. The programmable resistive devices can be fabricated using standard CMOS logic processes to reduce cell size and cost. In one embodiment, polysilicon diodes can be used as program selectors for reversible resistive memory cells that can be programmed based... Agent:
20120044750 - Semiconductor memory device: A semiconductor memory device includes a cell array having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between the plurality of first wirings and the plurality of second wirings. The semiconductor memory device further includes a control circuit... Agent: Kabushiki Kaisha Toshiba
20120044748 - Sensing circuit for programmable resistive device using diode as program selector: A sensing circuit for programmable resistive device using diode as program selector is disclosed. The sensing circuit can have a reference and a sensing branch. In one embodiment, each branch can have a first type of MOS with the source coupled to a first supply voltage, the drain coupled to... Agent:
20120044742 - Variable resistance memory array architecture: Memory devices, memory arrays, and methods of operation of memory arrays are disclosed. In one such memory device, a parallel selection architecture includes a control element, such as a selection transistor, in parallel with a variable resistance memory cell. Biasing of the selection transistor enables access to the memory cell... Agent: Micron Technology, Inc.
20120044749 - Variable resistance nonvolatile storage device and method of forming memory cell: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is... Agent:
20120044752 - High density integrated circuitry for semiconductor memory: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed... Agent: Round Rock Research, LLC
20120044753 - Programmably reversible resistive device cells using cmos logic processes: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active... Agent:
20120044754 - Spin-torque transfer magneto-resistive memory architecture: A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a... Agent: International Business Machines Corporation
20120044755 - System and method of reference cell testing: In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a... Agent: Qualcomm Incorporated
20120044758 - Circuit and system of using at least one junction diode as program selector for memories: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for memory cells that can be programmed based on direction of current flow. These cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to a P... Agent:
20120044756 - Memory devices using a plurality of diodes as program selectors with at least one being a polysilicon diode: Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal... Agent:
20120044757 - Memory using a plurality of diodes as program selectors with at least one being a polysilicon diode: Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal... Agent:
20120044759 - Nonvolatile semiconductor memory device and driving method thereof: A nonvolatile semiconductor memory device has a first select transistor having a gate connected to a first select word line extending in a column direction, a source connected to a first sub bit line, and a drain connected to a first main bit line extending in a row direction, and... Agent:
20120044760 - Nonvolatile semiconductor memory device and driving method thereof: A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected... Agent:
20120044763 - Non-volatile memory and semiconductor device: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120044761 - Nonvolatile memory device and method of programming the same: A method of 4-bit MLC programming a nonvolatile memory device includes inputting an mth program operation command and sequentially executing first to fourth logical page program operations according to first to fourth logical page program start voltages, each stored in first to fourth logical page program start voltage storage units,... Agent:
20120044762 - Rejuvenation of analog memory cells: A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the... Agent: Anobit Technologies Ltd
20120044764 - Nonvolatile semiconductor memory device which performs improved erase operation: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the... Agent:
20120044765 - Word line activation in memory devices: Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control... Agent: Micron Technology, Inc.
20120044767 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a... Agent: Hynix Semiconductor Inc.
20120044766 - Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the... Agent:
20120044769 - Multi-pass programming in a memory device: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to... Agent: Micron Technology, Inc.
20120044770 - Nand based nmos nor flash memory cell, a nand based nmos nor flash memory array, and a method of forming a nand based nmos flash memory array: A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through... Agent:
20120044768 - Programming to mitigate memory cell performance differences: Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and... Agent: Micron Technology, Inc.
20120044771 - Method of programming non-volatile memory device and apparatuses for performing the method: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells... Agent: Samsung Electronics Co., Ltd.
20120044772 - Non-volatile memory device, system, and cell array: A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second... Agent: Samsung Electronics Co., Ltd.
20120044775 - Semiconductor integrated circuit device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit... Agent: Renesas Electronics Corporation
20120044773 - Semiconductor memory device: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.... Agent:
20120044774 - Sense amplifier for low voltage high speed sensing: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to... Agent: Silicon Storage Technology, Inc.
20120044777 - Semiconductor device: By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied... Agent: Renesas Electronics Corporation
20120044776 - Semiconductor device and control method thereof: A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in... Agent: Elpida Memory, Inc.
20120044778 - Semiconductor device, method for inspecting the same, and method for driving the same: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120044779 - Data-aware dynamic supply random access memory: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the... Agent: Faraday Technology Corporation
20120044780 - Data output circuit of semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an... Agent: Hynix Semiconductor Inc.02/16/2012 > 41 patent applications in 23 patent subcategories. patent applications/inventions, industry category
20120039104 - Method and apparatus for buried word line formation: An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and,... Agent:
20120039105 - Semiconductor device: Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a... Agent: Sony Corporation
20120039106 - Programmable memory cell with shiftable threshold voltage transistor: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted... Agent: Broadcom Corporation
20120039107 - Circuit and system of aggregated area anti-fuse in cmos processes: Gate oxide breakdown anti-fuse suffers notorious soft breakdown that reduces yield and reliability. This invention discloses circuit and system to enhance electrical field by blocking LDD so that the electrical field is higher and more focused near the drain junction, to make electrical field in the channel more uniform by... Agent:
20120039108 - One-time programmable memory cell: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted... Agent: Broadcom Corporation
20120039112 - Hierarchical cross-point array of non-volatile memory: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of... Agent: Seagate Technology LLC
20120039109 - Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of reading to and writing from a memory cell, and methods of programming a memory cell: In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received... Agent:
20120039111 - Polarity dependent switch for resistive sense memory: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a... Agent: Seagate Technology LLC
20120039110 - Semiconductor memory device: A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the... Agent: Kabushiki Kaisha Toshiba
20120039113 - Three dimensionally stacked non volatile memory units: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a... Agent: Seagate Technology LLC
20120039114 - Memcapacitor: A memcapacitor device (100) includes a first electrode (104) and a second electrode (106) and a memcapacitive matrix (102) interposed between the first electrode (104) and the second electrode (106). Mobile dopants (111) are contained within the memcapacitive matrix (102) and are repositioned within the memcapacitive matrix (102) by the... Agent:
20120039115 - Stram with composite free magnetic element: Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a... Agent: Seagate Technology LLC
20120039117 - Destruction of data stored in phase change memory: A mechanism and means by which the data information pattern stored in Phase Change Memory PCM (21) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli(11) by the application of a targeted thermal heat source generated by an internal integrated thermal heater (26), a heat... Agent:
20120039116 - Phase change memory device comprising bismuth-tellurium nanowires: The present invention relates to a phase change memory device comprising bismuth-tellurium nanowires. More specifically, the bismuth-tellurium nanowires having PRAM characteristics may be prepared by using a porous nano template without any high temperature process and said nanowires may be used in the phase change memory device by using their... Agent:
20120039118 - Providing a ready-busy signal from a non-volatile memory device to a memory controller: A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that... Agent:
20120039119 - Method and system for providing magnetic tunneling junction elements having a biaxial anisotropy: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic... Agent: Grandis, Inc.
20120039122 - Multi-bit flash memory device and memory cell array: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.... Agent: Samsung Electronics Co., Ltd.
20120039123 - Multiple level programming in a non-volatile memory device: The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.... Agent: Round Rock Research, LLC
20120039124 - Non-volatile memory and method with improved sensing having bit-line lockout control: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose... Agent:
20120039120 - Non-volatile memory device and method for programming the device, and memory system: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of... Agent: Samsung Electronics Co., Ltd.
20120039125 - Nonvolatile memory with correlated multiple pass programming: A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size,... Agent:
20120039121 - Programming non-volatile memory with high resolution variable initial programming pulse: Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming... Agent:
20120039126 - Method for driving semiconductor memory device: A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120039127 - Flash memory device and method of operating the same: A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has... Agent: Hynix Semiconductor Inc.
20120039128 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent:
20120039129 - Cost saving electrically-erasable-programmable read-only memory (eeprom) array: A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line... Agent: Yield Microelectronics Corp.
20120039130 - Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same: Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting... Agent: Samsung Electronics Co., Ltd.
20120039131 - Low-voltage eeprom array: A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first... Agent: Yield Microelectronics Corp.
20120039132 - Memory device, systems and devices including a memory device, methods of operating a memory device, and/or methods of operating systems and devices including a memory device: In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program... Agent: Samsung Electronics Co., Ltd.
20120039134 - Data output circuit in a semiconductor memory apparatus: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when... Agent:
20120039133 - Semiconductor device performing refresh operation: To provide a semiconductor device including a temperature detection circuit that detects a temperature of the semiconductor device and outputs temperature information, a counter circuit that takes a count of repeated inputs of a refresh command and outputs count information, a comparison circuit that activates a match signal when the... Agent: Elpida Memory, Inc.
20120039135 - Memory cell write: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and... Agent:
20120039136 - Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus: Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a... Agent: Avago Technologies EnterpriseIP(singapore) Pte. Ltd.
20120039137 - Semiconductor integrated circuit with multi test: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat... Agent: Hynix Semiconductor Inc.
20120039138 - Asynchronous pipelined memory access: A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.... Agent:
20120039139 - Memory systems and methods for dividing physical memory locations into temporal memory locations: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies.... Agent: Rambus Inc.
20120039140 - Fuse circuit and semiconductor memory device including the same: A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance... Agent:
20120039142 - Scaleable look-up table based memory: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment,... Agent:
20120039141 - Voltage control method and memory device using the same: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that... Agent: Samsung Electronics Co., Ltd.
20120039144 - Semiconductor device with shortened data read time: A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase... Agent: Elpida Memory, Inc.
20120039143 - Sense amplifier with adjustable back bias: A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.02/09/2012 > 47 patent applications in 30 patent subcategories. patent applications/inventions, industry category
20120033477 - Memory modules having daisy chain wiring configurations and filters: Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used... Agent: Micron Technology, Inc.
20120033478 - Non-volatile memory device and sensing method for forming the same: A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over... Agent: Hynix Semiconductor Inc.
20120033482 - Bit set modes for a resistive sense memory cell array: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group... Agent: Seagate Technology LLC
20120033481 - Memory element with a reactive metal layer: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one... Agent: Unity Semiconductor Corporation
20120033479 - Modification of logic by morphological manipulation of a semiconductor resistive element: An electronic device includes a substrate with a resistive element located thereover. The resistive element includes a semiconductor region. A read module is configured to determine a resistance of the resistive element. A programming module is configured to cause a current to flow through the semiconductor region. The current is... Agent: Lsi Corporation
20120033480 - Semiconductor memory device: A semiconductor memory device according to the embodiment comprises a memory cell array including first line, second line crossing the first line, and memory cell containing variable resistance element provided on the intersection of the first and second lines; a data write unit operative to cause the variable resistance element... Agent: Kabushiki Kaisha Toshiba
20120033485 - Semiconductor device: In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033483 - Semiconductor device and driving method of semiconductor device: A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033484 - Semiconductor device and driving method thereof: The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used,... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033487 - Semiconductor device and driving method thereof: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033488 - Semiconductor device and driving method thereof: A semiconductor device including a memory cell formed using a wide bandgap semiconductor, for example, an oxide semiconductor is provided. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. With the use... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033486 - Semiconductor device and method for driving semiconductor device: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033489 - Memory device, precharge controlling method thereof, and devices having the same: A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global... Agent: Samsung Electronics Co., Ltd.
20120033490 - Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction: A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a... Agent: Qualcomm Incorporated
20120033492 - Data writing method and data storage device: The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage... Agent: Silicon Motion, Inc.
20120033494 - Detecting the completion of programming for non-volatile storage: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when... Agent:
20120033493 - Erase completion recognition: Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively... Agent: Micron Technology, Inc.
20120033495 - Semiconductor device: A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold... Agent: Renesas Electronics Corporation
20120033496 - Semiconductor storage device with volatile and nonvolatile memories: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in... Agent:
20120033497 - Non-volatile memory device having configurable page size: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to... Agent: Mosaid Technologies Incorporated
20120033499 - Flash memory device and reading method thereof: A flash memory device and reading method of the flash memory device. The reading method includes determining a read voltage set of memory cells corresponding to a first word line from at least one of flag cell data of the first word line and flag cell data of a second... Agent:
20120033498 - Semiconductor memory device and method of reading the same: A semiconductor memory device comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of... Agent:
20120033500 - Natural threshold voltage distribution compaction in non-volatile memory: In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase... Agent:
20120033501 - Nonvolatile memory device with 3d memory cell array: Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals,... Agent: Samsung Electronics Co., Ltd.
20120033491 - Programming of memory cells in a nonvolatile memory using an active transition control: An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its... Agent: Texas Instruments Incorporated
20120033502 - Method of reading data in non-volatile memory device, and device thereof: A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the... Agent: Samsung Electronics Co., Ltd
20120033503 - Charge trap flash memory device and an erasing method thereof: An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution... Agent:
20120033504 - Erase voltage reduction in a non-volatile memory device: In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification... Agent: Micron Technology, Inc.
20120033505 - Semiconductor device and method for driving semiconductor device: A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033507 - On die thermal sensor of semiconductor memory device: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a... Agent:
20120033506 - Semiconductor device: A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so... Agent: Elpida Memory, Inc.
20120033508 - Level shifter for use with memory arrays: In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first... Agent: International Business Machines Corporation
20120033509 - Memory data reading and writing technique: A novel circuit for reading data in solid state memory cells is presented. It can be used for any type of memory cell array but more specifically it is particularly suited for volatile memories like SRAM and DRAM. It is based on sensing the current in the ground line of... Agent:
20120033511 - Control circuit of read operation for semiconductor memory apparatus: A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output... Agent: Hynix Semiconductor Inc.
20120033510 - Semiconductor device: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120033512 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The... Agent:
20120033513 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line... Agent: Round Rock Research, LLC
20120033514 - Strobe-offset control circuit: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A... Agent:
20120033515 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word... Agent:
20120033516 - Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device: A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word... Agent:
20120033517 - Adaptive write bit line and word line adjusting mechanism for memory: A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120033518 - Current sink system for source-side sensing: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the... Agent: Macronix International Co., Ltd.
20120033519 - Temperature alert and low rate refresh for a non-volatile memory: A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the... Agent:
20120033520 - Memory with low voltage mode operation: A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning... Agent:
20120033521 - Semiconductor apparatus and its control method: Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First... Agent: Elpida Memory, Inc.
20120033522 - Variation-tolerant word-line under-drive scheme for random access memory: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a... Agent: Faraday Technology Corporation
20120033523 - Input circuit of semiconductor memory apparatus and controlling method thereof: Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area... Agent: Hynix Semiconductor Inc.02/02/2012 > 51 patent applications in 33 patent subcategories. patent applications/inventions, industry category
20120026772 - Memory module and layout method therefor: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied... Agent: Elpida Memory, Inc.
20120026774 - Semiconductor device and method for driving the same: An object is to provide a semiconductor device in which lower power consumption is realized by lowering voltage for data writing without increase in types of power supply potentials. Another object is to provide a semiconductor device in which threshold voltage drop of a selection transistor is suppressed without increase... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120026773 - Semiconductor memory apparatus having sense amplifier: Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array... Agent: Hynix Semiconductor Inc.
20120026775 - Method of operating semiconductor memory device: According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in... Agent: Kabushiki Kaisha Toshiba
20120026780 - Conductive metal oxide structures in non volatile re writable memory devices: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions... Agent: Unity Semiconductor Corporation
20120026776 - Memory resistor having plural different active materials: Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are... Agent:
20120026779 - Nonvolatile memories and reconfigurable circuits: A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode... Agent: Kabushiki Kaisha Toshiba
20120026781 - Resistive memory and method: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.... Agent: Infineon Technologies Ag
20120026778 - Semiconductor storage device: A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable... Agent: Kabushiki Kaisha Toshiba
20120026777 - Variable-resistance memory device: Disclosed herein is a variable-resistance memory device including: a memory-cell array employing a plurality of memory cells each including a storage element having a resistance varying in accordance with the direction of a voltage applied to the storage element and including an access transistor connected in series to the storage... Agent: Sony Corporation
20120026782 - Semiconductor memory device: In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is... Agent: Panasonic Corporation
20120026783 - Latching circuit: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing... Agent: Qualcomm Incorporated
20120026785 - Non-volatile magnetic memory element with graded layer: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded... Agent: Avalanche Technology, Inc.
20120026784 - Random number generator: According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state... Agent: Kabushiki Kaisha Toshiba
20120026787 - Semiconductor device and method for driving the same: A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120026786 - Write operation for phase change memory: Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell.... Agent:
20120026788 - Distortion estimation and cancellation in memory devices: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference... Agent: Anobit Technologies Ltd.
20120026789 - Distortion estimation and cancellation in memory devices: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference... Agent: Anobit Technologies Ltd.
20120026792 - Erase cycle counter usage in a memory device: Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of... Agent: Micron Technology, Inc.
20120026791 - Method for non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of... Agent:
20120026790 - Non-volatile memory device including block state confirmation cell and method of operating the same: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing... Agent:
20120026794 - Method and apparatus of operating a non-volatile dram: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is... Agent: Chip Memory Technology, Inc.
20120026793 - Nonvolatile memory cell with extended well: One embodiment relates to a memory device. The memory device includes a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate. The memory device... Agent: Infineon Technologies Ag
20120026795 - Electronic apparatus and data reading method: In one embodiment, there is provided an electronic apparatus. The apparatus includes: a storage device including a plurality of blocks that are units of data erasure. Each of the blocks includes a plurality of pages that are units of data reading or writing. Each of the pages includes: a data... Agent:
20120026797 - Nonvolatile memory devices, methods of programming the same, and memory systems including the same: A nonvolatile memory device including a bit line connected to a cell string, a page buffer connected to the bit line, the page buffer is configured to output a target bit line forcing voltage level to the bit line during a programming operation, and a bit line forcing voltage clamp... Agent: Samsung Electronics Co., Ltd.
20120026796 - Storage device and method for operating the same: A storage device includes a control unit, a first voltage supply unit for supplying a first working voltage to the control unit, N memory units, a second voltage supply unit for supplying a second working voltage to each memory unit, a logic gate, a first voltage detecting unit and a... Agent:
20120026798 - Semiconductor nonvolatile memory device: s
20120026799 - Non-volatile memory device having reference cells, and related method of setting reference current: A method of setting a reference current of a nonvolatile memory device comprises measuring a noise characteristic of each of multiple reference cells, and selecting at least one of the reference cells as a reference cell for generating a reference current according to the measured noise characteristics.... Agent: Samsung Electronics Co., Ltd.
20120026800 - Semiconductor apparatus and method for transferring control voltage: A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the... Agent: Hynix Semiconductor Inc.
20120026801 - Semiconductor memory apparatus and method for discharging wordline thereof: Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a... Agent: Hynix Semiconductor Inc.
20120026808 - Integrated circuit with low power sram: An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.... Agent: Texas Instruments Incorporated
20120026803 - Data output circuit and method: A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same... Agent:
20120026804 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections... Agent: Kabushiki Kaisha Toshiba
20120026806 - Data input circuit: A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble... Agent: Hynix Semiconductor Inc.
20120026805 - Sram bitcell data retention control for leakage optimization: An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120026807 - Semiconductor memory chip and integrated circuit: A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through... Agent: Hynix Semiconductor Inc.
20120026809 - Multi-bit test circuit of semiconductor memory apparatus: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.... Agent: Hynix Semiconductor Inc.
20120026810 - Semiconductor memory device and antifuse programming method: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit... Agent: Renesas Electronics Corporation
20120026811 - Integrated semiconductor device: Disclosed herein is an integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer... Agent: Sony Corporation
20120026802 - Managed hybrid memory with adaptive power supply: Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply.... Agent:
20120026812 - Memory with termination circuit: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first... Agent: Renesas Electronics Corporation
20120026814 - Circuit for transmitting and receiving data and control method thereof: A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and... Agent:
20120026813 - Semiconductor device changing an active time-out time interval: A device includes a plurality of memory areas each including a plurality of memory cells required to perform refresh of information stored therein by a plurality of sense amplifiers, a first control circuit determining, in connection with one refresh requirement signal at a time, a number of refresh-target memory areas... Agent: Elpida Memory, Inc.
20120026816 - Defective memory block identification in a memory device: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal... Agent: Micron Technology, Inc.
20120026815 - Semiconductor device and method of testing the same: A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control... Agent: Elpida Memory , Inc.
20120026817 - Low cost testing and sorting of integrated circuits: Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is... Agent:
20120026818 - Split bit line architecture circuits and methods for memory devices: Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit... Agent: Tw Semiconductor Manufacturing Company, Ltd.
20120026819 - Fast cyclic decoder circuit for fifo/lifo data buffer: Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable... Agent:
20120026820 - Integrated circuits for providing clock periods and operating methods thereof: An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120026821 - Semiconductor device: A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command.... Agent:
20120026822 - Semiconductor device and method of driving the same: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section... Agent: Sony CorporationPrevious industry: Electric power conversion systems
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