|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval January recently filed with US Patent Office 01/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/26/2012 > 42 patent applications in 27 patent subcategories.
20120020138 - Transistor having an adjustable gate resistance and semiconductor device comprising the same: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a... Agent: Macronix International Co., Ltd.
20120020139 - Apparatus and method for testing one-time-programmable memory: An apparatus and method of testing one-time-programmable memory limits current through a one-time-programmable memory to less than a threshold amplitude, where the memory has a fuse configured to blow upon receipt of a signal having the threshold amplitude. The method also uses blow signal assertion circuitry to attempt to assert... Agent: Analog Devices, Inc
20120020143 - Array operation using a schottky diode as a non ohmic selection device: A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single... Agent: Unity Semiconductor Corporation
20120020142 - Resistive memory: Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or... Agent:
20120020140 - Resistive memory cell and operation thereof, and resistive memory and operation and fabrication thereof: A resistive memory cell is described, including a first electrode, a high-resistance ferroelectric material layer and a second electrode. The ferroelectric material layer has a first interface with the first electrode and has a second interface with the second electrode, wherein the second interface is not parallel with the first... Agent: Industrial Technology Research Institute
20120020141 - Variable-resistance memory device and its driving method: A variable-resistance memory device includes: a memory cell including a memory element being variable in resistance in accordance with a polarity of an application voltage applied to the memory element in a set or reset operation and an access transistor connected to the memory element in series between first and... Agent: Sony Corporation
20120020144 - Semiconductor device having floating body type transistor: A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between... Agent: Elpida Memory, Inc.
20120020145 - Identification circuit and method for generating an identification bit: A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit... Agent: Infineon Technologies Ag
20120020146 - Static random access memory device including negative voltage level shifter: Integrated circuit memory devices include an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines.... Agent:
20120020147 - Magnetic memory element, magnetic memory device, information recording/reproducing apparatus: A magnetic memory element includes a pair of electrodes, a junction layer, at least one carbon nanotube, and at least one nanowire. The at least one nanowire is made of a ferromagnetic material and extends through a hole of each the at least one carbon nanotube with both ends being... Agent: Tdk Corporation
20120020148 - Multi-bit stram memory cells: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer.... Agent: Seagate Technology LLC
20120020150 - Integrated circuits with phase change devices: Embodiments include methods, apparatus, and systems with integrated circuits having phase change devices. One embodiment includes an integrated circuit die and a phase change die having a phase change material that changes phases when a temperature at the integrated circuit die exceeds a threshold for a predetermined amount of time.... Agent:
20120020149 - Semiconductor device: A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the bit line with a... Agent: Elpida Memory, Inc
20120020151 - Storage apparatus and method of manufacturing the same: A storage apparatus including a circuit board, a control circuit element, a terminal module and a storage circuit element is provided. The circuit board includes a first surface, a second surface, a connect part, openings, metal contacts and metal units. The openings pass through the circuit board from the first... Agent: Phison Electronics Corp.
20120020152 - Writable magnetic memory element: The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is parallel or perpendicular to the plane of the central layer, said central... Agent: Universite Joseph Fourier
20120020156 - Method for programming non-volatile memory device and apparatuses performing the method: A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.... Agent: Samsung Electronics Co., Ltd.
20120020155 - Multipage program scheme for flash memory: A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed into one physical page of a flash memory array are stored in page buffers or other storage means on the memory device. The... Agent: Mosaid Technologies Incorporated
20120020153 - Nonvolatile memory devices with highly reliable programming capability and methods of operating same: Programming methods of a non-volatile memory device by which a programming error is less likely to occur. A programming method may involve applying a precharge voltage to a program inhibit cell at a different time according to the threshold voltage of the program inhibit cell. A programming method may involve... Agent:
20120020154 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first... Agent:
20120020157 - Novel high-temperature non-volatile memory design: A method for fabricating a high temperature integrated circuit includes forming a drain/source diffusion and forming a buried diffusion implant containing the drain/source diffusion in a substrate to separate the drain/source diffusion from the substrate and an edge of a field isolation layer to decreases leakage current occurring with high... Agent: Aplus Flash Technology, Inc.
20120020158 - Semiconductor memory device and manufacturing method thereof: A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged... Agent: Kabushiki Kaisha Toshiba
20120020159 - Non-volatile static ram cell circuit and timing method: A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data... Agent: Grandis, Inc.
20120020160 - Nonvolatile semiconductor memory device and writing method thereof: A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be... Agent: Kabushiki Kaisha Toshiba
20120020161 - Multiple plane, non-volatile memory with synchronized control: This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the... Agent: Rambus Inc.
20120020163 - Array architecture for reduced voltage, low power, single poly eeprom: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access... Agent:
20120020162 - Low power, single poly eeprom cell with voltage divider: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal... Agent:
20120020165 - Semiconductor storage device and control method thereof: In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read... Agent: Kabushiki Kaisha Toshiba
20120020164 - Test method for screening manufacturing defects in a memory array: A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell... Agent: Macronix International Co., Ltd.
20120020166 - Nonvolatile semiconductor storage device: In one embodiment, a nonvolatile semiconductor storage device includes a plurality of memory cells, and a setting part in which a setting value for prescribing a relation between a program voltage to be applied to the memory cells and a loop number of application processes of the program voltage is... Agent: Kabushiki Kaisha Toshiba
20120020167 - Flash memory device and a method of programming the same: A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling... Agent:
20120020168 - Power supplies in flash memory devices and systems: Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an... Agent: Mosaid Technologies Incorporated
20120020169 - Two-port sram write tracking scheme: A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120020170 - Reference voltage regulator for edram with vss-sensing: In a method of operating a reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level, an oscillator sends requests for sampling and correction to a control block between accesses of the eDRAM. The control block sends a pulse defining a time interval... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120020172 - Data strobe signal generating device and a semiconductor memory apparatus using the same: A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first dock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate... Agent: Hynix Semiconductor Inc.
20120020171 - Memory system with delay locked loop (dll) bypass control: A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock.... Agent: International Business Machines Corporation
20120020174 - Asynchronous semiconductor memory capable of preventing coupling noise: Disclosed herein is a semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay... Agent: Oki Semiconductor Co., Ltd.
20120020173 - Sense amplifier enable signal generation: System and method for generating a sense amplifier enable (“SAE”) signal having a programmable delay with a feedback loop to control the SAE signal duty cycle, which can be used in SRAM or DRAM, or other kinds of memory cells. An illustrative non-limiting embodiment comprises: a programmable clock chopper, a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120020175 - Method and system for processing a repair address in a semiconductor memory apparatus: A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair... Agent: Hynix Semiconductor Inc.
20120020176 - Generating and amplifying differential signals: Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120020177 - Electrical fuse memory: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column,... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120020178 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a... Agent: Rambus Inc.
20120020179 - Method and apparatus for word line decoder layout: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of... Agent: Taiwan Semiconductor Manufacuring Co., Ltd.01/19/2012 > 50 patent applications in 33 patent subcategories.
20120014156 - Data receiver, semiconductor device and memory device including the same: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and... Agent:
20120014157 - Semiconductor device: A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120014158 - Memory devices: A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120014159 - Memory device: A memory device includes a memory unit including a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines, and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and... Agent:
20120014168 - Dual stage sensing for non-volatile memory: A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory... Agent: Seagate Technology LLC
20120014161 - Memristive negative differential resistance device: A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material.... Agent: Hewlett-packard Development Company, L.p.
20120014169 - Non-volatile data-storage latch: One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a... Agent:
20120014160 - Non-volatile re-programmable memory device: A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs... Agent:
20120014165 - Optimized solid electrolyte for programmable metallization cell devices and structures: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure,... Agent: Axon Technologies Corporation
20120014164 - Resistance-change memory and method of operating the same: According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude... Agent:
20120014166 - Resistive memory: The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch... Agent: Micron Technology, Inc.
20120014167 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said... Agent: Kabushiki Kaisha Toshiba
20120014163 - Semiconductor memory device and method of driving the same: A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a... Agent:
20120014162 - Semiconductor memory device featuring selective data storage in a stacked memory cell structure: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a... Agent:
20120014170 - Capacitive crossbar arrays: A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is interposed between a first conductor (103) within the first set (102) and a second conductor (105) within the second set... Agent: Hewlet- Packard Developement Company L.p.
20120014171 - Schmitt trigger-based finfet sram cell: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the... Agent:
20120014172 - Static random access memory devices having read and write assist circuits therein that improve read and write reliability: Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The. write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to... Agent:
20120014173 - Disturb-free static random access memory cell: A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell.... Agent: Texas Instruments Incorporated
20120014176 - Creating spin-transfer torque in oscillators and memories: A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of... Agent:
20120014175 - Magnetic tunnel junction and memristor apparatus: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor... Agent: Seagate Technology LLC
20120014174 - Programmable write driver for stt-mram: A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is... Agent: Qualcomm Incorporated
20120014177 - Semiconductor switching device: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided... Agent:
20120014178 - Nonvolatile semiconductor memory device and method of reusing same: A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder... Agent: Oki Semiconductor Co., Ltd.
20120014180 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile... Agent: Zeno Semiconductor, Inc.
20120014181 - Nonvolatile semiconductor memory: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is... Agent: Genusion, Inc.
20120014182 - Apparatus for generating a voltage and non-volatile memory device having the same: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at... Agent:
20120014183 - 3 transistor (n/p/n) non-volatile memory cell without program disturb: A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that... Agent:
20120014184 - Programming non-volatile memory with bit line voltage step up: Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up... Agent:
20120014185 - Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory: An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit... Agent: Micron Technology, Inc.
20120014186 - Fast random access to non-volatile storage: Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not discharging bit lines between successive sensing operations. For example, all even bit lines are charged up and odd bit lines are... Agent:
20120014187 - Non-volatile memory device and method of operation therefor: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is... Agent:
20120014179 - Soft program of a non-volatile memory block: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage... Agent:
20120014188 - Method of maintaining the state of semiconductor memory having electrically floating body transistor: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of... Agent:
20120014190 - Refresh signal generating circuit: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal... Agent: Hynix Semiconductor Inc.
20120014189 - Semiconductor memory device and test method thereof: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data... Agent:
20120014191 - Semiconductor memory device: A semiconductor memory device of an embodiment includes memory cells 2, a write-back determining unit 7, and a read controller 8. Each memory cell 2 is capable of writing and reading through different paths. The write-back determining unit 7 determines whether or not to perform the write-back for a non-selected... Agent: Kabushiki Kaisha Toshiba
20120014193 - Charge pump circuit, nonvolatile memory, data processing apparatus, and microcomputer application system: Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate... Agent: Renesas Electronics Corporation
20120014192 - Two stage voltage level shifting: A voltage level shifter for shifting an output signal from a first voltage level to a second voltage level and then to a further boosted second voltage level is disclosed. The voltage level shifter comprises: an input for receiving an input signal; an output for outputting an output signal; a... Agent: Arm Limited
20120014194 - Memory cell with equalization write assist in solid-state memory: A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors... Agent: Texas Instruments Incorporated
20120014195 - Sram with buffered-read bit cells and its testing: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word... Agent:
20120014196 - Processor instruction cache with dual-read modes: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in... Agent:
20120014197 - Semiconductor device and test method thereof: A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of... Agent: Elpida Memory, Inc.
20120014198 - Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the... Agent:
20120014199 - Semiconductor device that performs refresh operation: To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2n... Agent: Elpida Memory, Inc.
20120014200 - Multi-time programmable memory: Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip... Agent: Broadcom Corporation
20120014201 - Dual rail memory: A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120014202 - Memory device and method: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to... Agent: Cypress Semiconductor Corporation
20120014203 - Semiconductor memory apparatus: A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference... Agent: Hynix Semiconductor Inc.
20120014204 - Semiconductor memory device for guaranteeing reliablity of data transmission and semiconductor system including the same: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of... Agent:
20120014205 - Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of... Agent:01/12/2012 > 93 patent applications in 40 patent subcategories.
20120008360 - Multi-chip package and method of operating the same: A multi-chip package includes a plurality of memory chips for performing a content addressable memory (CAM) read operation in response to a command signal for the CAM read operation and an address signal for selecting the memory chips and a controller for outputting the command signal and the address signal... Agent: Hynix Semiconductor Inc.
20120008361 - Semiconductor memory device: A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines for the memory cells, and metal lines coupled to the... Agent: Hynix Semiconductor Inc.
20120008362 - Magnetic spin shift register memory: A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on... Agent: International Business Machines Corporation
20120008363 - Diode-less array for one-time programmable memory: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent... Agent: Macronix International Co., Ltd.
20120008364 - One time programmable memory and the manufacturing method and operation method thereof: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region... Agent: Maxchip Electronics Corp.
20120008365 - Method for operating a nonvolatile switching device: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a... Agent: Panasonic Corporation
20120008373 - Capacitive discharge method for writing to non-volatile memory: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide... Agent:
20120008374 - Data storage using read-mask-write operation: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored... Agent: Seagate Technology LLC
20120008369 - Memory element and drive method for the same, and memory device: A memory element capable of increasing capacity with an improvement of distribution of resistance in the high-resistance state, a drive method therefor, and a memory device are provided. The memory element includes first and second electrodes, and a plurality of resistance change elements electrically connected in series between the first... Agent: Sony Corporation
20120008370 - Memory element and memory device: A memory element and a memory device with improved controllability over resistance change by applied voltage are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and... Agent: Sony Corporation
20120008372 - Resistance change memory device: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell... Agent: Kabushiki Kaisha Toshiba
20120008367 - Resistance change type memory: According to one embodiment, a resistance change type memory includes a memory cell and a capacitor which are provided on a semiconductor substrate. The memory cell includes a resistance change type memory and a select transistor. The resistance change type storage element changes in resistance value in accordance with data... Agent: Kabushiki Kaisha Toshiba
20120008366 - Restive memory using sige material: A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.... Agent: Crossbar, Inc.
20120008368 - Semiconductor device having single-ended sensing amplifier: A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to... Agent: Elpida Memory, Inc.
20120008371 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively... Agent: Kabushiki Kaisha Toshiba
20120008375 - Cmos image sensor with noise cancellation: A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and... Agent: Candela Microsystems, Inc.
20120008379 - Global bit line restore by most significant bit of an address line: An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data... Agent: International Business Machines Corporation
20120008378 - Memory devices and methods having multiple address accesses in same cycle: A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two... Agent: Cypress Semiconductor Corporation
20120008376 - Memory with regulated ground nodes: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120008377 - Static random access memory with data controlled power supply: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.... Agent:
20120008382 - Magnetic recording element: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic... Agent: Fuji Electric Co., Ltd.
20120008381 - Magnetoresistive element: A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material... Agent:
20120008380 - Method for writing in a mram-based memory device with reduced power consumption: A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and... Agent: Crocus Technology Sa
20120008383 - Magnetic device with optimized heat confinement: The present disclosure concerns a magnetic element to be written using a thermally-assisted switching write operation comprising a magnetic tunnel junction formed from a tunnel barrier being disposed between first and second magnetic layers, said second magnetic layer having a second magnetization which direction can be adjusted during a write... Agent: Crocus Technology Sa
20120008387 - Method of twice programming a non-volatile flash memory with a sequence: A method of twice programming a multi-bit per cell non-volatile memory with a sequence is disclosed. At least one page at a given word line is firstly programmed with program data by a controller of the non-volatile memory, and at least one page at a word line preceding the given... Agent: Skymedi Corporation
20120008388 - Non-volatile memory and operation method thereof: An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group... Agent: Macronix International Co., Ltd.
20120008389 - Nonvolatile memory devices, memory systems and methods of performing read operations: Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has... Agent: Samsung Electronics Co., Ltd.
20120008390 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level... Agent:
20120008391 - Voltage switch circuit and nonvolatile memory device using the same: A voltage switch circuit includes a positive voltage supply circuit configured to supply a positive voltage to a control node in response to an enable signal, a negative voltage supply circuit configured to supply a negative voltage to the control node in response to a negative voltage enable signal, a... Agent:
20120008397 - Memory system and method of operating the same: A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation... Agent:
20120008392 - Nonvolatile memory device and method for operating the same: A nonvolatile memory device includes a plurality of memory blocks, a plurality of erasure detection units provided at the plurality of memory blocks, respectively, and configured to each detect erasure of the respective memory blocks, and a control unit configured to determine that a memory block is a bad memory... Agent:
20120008395 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a... Agent: Hynix Semiconductor Inc.
20120008393 - Nonvolatile memory device and operation method thereof: An operation method of a nonvolatile memory device includes reading information of an erase target block, and performing an erase operation by using a starting erase bias corresponding to the information.... Agent:
20120008394 - Nonvolatile memory system and refresh method: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.... Agent: Samsung Electronics Co., Ltd.
20120008396 - Semiconductor memory device and method of erasing the same: A semiconductor memory device includes memory cell blocks having physical pages coupled to memory cells, peripheral circuits configured to program the memory cells or read data stored in the memory cells, and a controller configured to control the peripheral circuits so that a pre-program is performed to make memory cells... Agent:
20120008398 - Nonvolatile memory device: A nonvolatile memory device includes a plurality of global word lines, a plurality of transistors configured to transfer voltages of the global word lines to a plurality of local word lines inside a cell block, and a voltage control unit configured to supply a first negative voltage to a global... Agent:
20120008399 - Methods of operating memories including characterizing memory cell signal lines: Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC... Agent: Micron Technology, Inc.
20120008400 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes: a memory string; a select transistor; and a carrier selection element. The select transistor has one end connected to one end of the memory string. The carrier selection element has one end connected to the other end of the select transistor, and selects a... Agent: Kabushiki Kaisha Toshiba
20120008403 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a boost circuit configured to boost a power supply voltage so as to generate first and second voltages, the second voltage being lower than the first voltage, a load circuit supplied with the first voltage, and a capacitor. The capacitor has first and second diffusion... Agent:
20120008402 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes performing an LSB program operation for selected memory cells while raising a program voltage, when the threshold voltages of some of the selected memory cells reach a target level, storing data, corresponding to a relevant program voltage, in a first flag... Agent: Hynix Semiconductor Inc.
20120008404 - System and method for reducing pin-count of memory devices, and memory device testers for same: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode... Agent: Micron Technology, Inc.
20120008401 - Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system: A method, system and computer-readable medium are provided for reading information from a memory unit. A request may be received to read information from a set of memory cells in the memory unit. At least one read threshold in an initial set of read thresholds may be perturbed to generate... Agent:
20120008405 - Detection of broken word-lines in memory arrays: Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses... Agent:
20120008408 - Non-volatile memory device and operating method of the same: A non-volatile memory device and an operation method of the same are provided. A method for operating a non-volatile memory device includes programming a plurality of memory cells based on a target voltage level, verifying threshold voltage levels of the plurality of memory cells based on a correction voltage level... Agent:
20120008406 - Nonvolatile memory device and method of operating the same: A method of operating a nonvolatile memory device includes programming first memory cells to make threshold voltages of the first memory cells to reach a verification voltage determined based on program data of second memory cells to be programmed, and programming the second memory cells.... Agent:
20120008409 - Reduction of quick charge loss effect in a memory device: Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to... Agent: Micron Technology, Inc.
20120008407 - Semiconductor memory device and method of programming the same: A method of programming a semiconductor memory device includes a first program step for performing a program by supplying a first program voltage, having a specific amount, to a selected word line of the semiconductor memory device for a set time and a second program step for performing a program... Agent: Hynix Semiconductor Inc.
20120008384 - Detection of word-line leakage in memory arrays: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due... Agent:
20120008386 - Determining optimal reference voltages for progressive reads in flash memory systems: A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference... Agent:
20120008385 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array including cell strings each including a plurality of memory cells, bit lines coupled to the respective cell strings, and page buffers configured to compare a reference current and currents of the respective bit line and output sense data corresponding to a... Agent:
20120008410 - Detection of word-line leakage in memory arrays: current based approach: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due... Agent:
20120008411 - Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can... Agent: Btg International Inc.
20120008412 - Nonvolatile memory device and method of erasing the same: A method of erasing a nonvolatile memory device includes the steps of supplying an erase voltage to the P well of a semiconductor substrate having a memory cell block disposed therein; performing a first erase verification operation for verifying the erase state of memory cells coupled to the even bit... Agent: Hynix Semiconductor Inc.
20120008413 - Method for operating semiconductor memory device: A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages... Agent:
20120008414 - Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system: A method, system and computer-readable medium are provided for reading information from a memory unit. A read instruction may be received to read information from a set of memory cells in the memory unit. A data structure storing sets of read thresholds may be searched for a set of read... Agent:
20120008417 - Nonvolatile memory and operation method of the same: A nonvolatile memory includes a first bit line coupled to a first cell string, a second bit line coupled to a second cell string, and a bit line precharge unit configured to precharge the first bit line and the second bit line before a program operation. A bit line selected... Agent:
20120008418 - Semiconductor memory device: A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers... Agent:
20120008415 - Semiconductor memory device and method of erasing the same: A method of erasing a semiconductor memory device includes precharging a channel of a selected memory cell of a selected string including memory cells; boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; and erasing... Agent: Hynix Semiconductor Inc.
20120008416 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed... Agent: Hynix Semiconductor Inc.
20120008419 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages... Agent:
20120008429 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the... Agent: Hynix Semiconductor Inc.
20120008420 - Command generation circuit and semiconductor memory device: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching... Agent: Hynix Semiconductor Inc.
20120008421 - Data outputing method of memory circuit and memory circuit and layout thereof: A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ˜DQ for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data... Agent: Elite Semiconductor Memory Technology Inc.
20120008426 - High speed dram architecture with uniform access latency: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device... Agent: Mosaid Technologies Incorporated
20120008424 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission... Agent: Hynix Semiconductor Inc.
20120008422 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a memory bank configured to output stored data in response to a column selection signal, a plurality of data latching units configured to latch the data outputted from the memory bank in response to an input control signal which is generated according to the column... Agent:
20120008425 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array including a plurality of memory cells, circuits configured to receive program data when a program operation is performed and output a random signal in response to the program data, and a page buffer configured to logically combine the program data and... Agent:
20120008423 - Setting circuit and integrated circuit including the same: A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.... Agent:
20120008427 - Semiconductor memory device to reduce off-current in standby mode: A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal... Agent: Hynix Semiconductor Inc.
20120008428 - Data output circuit for semiconductor memory device: A data output circuit for a semiconductor memory device includes a first driver configured to output a first drive control signal in response to a data signal, a drive controller configured to compare a voltage level of the first drive control signal with a reference voltage and output a second... Agent:
20120008430 - Semiconductor storage device: According to the embodiments, a memory cell stores therein data, a dummy cell replicates an operation of the memory cell, a write control unit makes the dummy cell to perform writing in synchronization with write timing of the memory cell, and a row decoder performs opening and closing of a... Agent: Kabushiki Kaisha Toshiba
20120008431 - Integrated circuit using method for setting level of reference voltage: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit... Agent: Hynix Semiconductor Inc.
20120008432 - Memory cell having reduced circuit area: The present invention relates to a memory cell having a reduced circuit area, which comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled to a readline and controlled by a wordline. The second transistor is coupled between the first transistor... Agent:
20120008437 - Counter circuit, latency counter, semiconductor memory device including the same, and data processing system: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first... Agent: Elpida Memory, Inc.
20120008435 - Delay locked loop: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay... Agent:
20120008439 - Delay locked loop circuit and method: Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter... Agent:
20120008438 - Efficient word lines, bit line and precharge tracking in self-timed memory device: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The... Agent: Freescale Semiconductor, Inc
20120008433 - Semiconductor memory device: A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to... Agent:
20120008434 - Semiconductor system and device, and method for controlling refresh operation of stacked chips: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different... Agent:
20120008436 - Simulating a refresh operation latency: A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to... Agent: Google Inc.
20120008440 - Data retention kill function: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are... Agent: Micron Technology, Inc.
20120008441 - Semiconductor memory device and test method thereof: A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy... Agent:
20120008442 - Semiconductor device and method of testing the same: A semiconductor device according to an aspect of the present disclosure includes a test mode signal generator configured to generate a test mode setup signal, and a controller configured to set a separated test operation in response to the test mode setup signal.... Agent: Hynix Semiconductor Inc.
20120008444 - Dual bit line precharge architecture and method for low power dynamic random access memory (dram) integrated circuit devices and devices incorporating embedded dram: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention... Agent: Promos Technologies Pte.ltd.
20120008445 - Dual bit line precharge architecture and method for low power dynamic random access memory (dram) integrated circuit devices and devices incorporating embedded dram: A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current consumption and low memory array noise spike of VCC/2 precharge techniques. The architecture and technique of the present invention... Agent: Promos Technologies Pte.ltd.
20120008443 - Implementing smart switched decoupling capacitors to efficiently reduce power supply noise: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a... Agent: International Business Machines Corporation
20120008446 - Precharging circuit and semiconductor memory device including the same: A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or... Agent:
20120008447 - Semiconductor device having variable parameter selection based on temperature: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worse... Agent:
20120008448 - Anti-fuse circuit and semiconductor integrated circuit including the same: An anti-fuse circuit includes an anti-fuse coupled to a sensing node, a driving unit configured to rupture the anti-fuse in response to a rupture enable signal, an anti-fuse status detecting unit configured to output an anti-fuse status detecting signal in response to a voltage at the sensing node corresponding to... Agent:
20120008449 - Low power static random access memory: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at... Agent:
20120008450 - Flexible memory architecture for static power reduction and method of implementing the same in an integrated circuit: A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least... Agent: Lsi Corporation
20120008451 - Semiconductor memory device: A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group... Agent:
20120008452 - Semiconductor integrated circuit capable of controlling read command: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a... Agent: Hynix Semiconductor Inc.01/05/2012 > 46 patent applications in 30 patent subcategories.
20120002455 - Miniturization techniques, systems, and apparatus relatng to power supplies, memory, interconnections, and leds: Miniaturization techniques, systems, and apparatus relating to power supplies, memory, interconnections, and LEDS are described herein. Specifically, some aspects of the invention relate to techniques for miniaturization of power supplies. Other aspects relate to systems and methods for optimizing memory performance in a computer device or system. Still further, some... Agent:
20120002456 - Method of arranging pads in semiconductor device, semiconductor memory device using the method, and processing system having mounted therein the semiconductor memory device: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory... Agent: Samsung Electronics Co., Ltd.
20120002458 - Resistance change memory device: A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference... Agent: Kabushiki Kaisha Toshiba
20120002457 - Semiconductor memory device and control method of the same: According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and... Agent:
20120002459 - 5t sram memory for low voltage applications: An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented... Agent: Stmicroelectronics S.r.l.
20120002460 - Dynamically configurable sram cell for low voltage operation: An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable... Agent: Stmicroelectronics S.r.l.
20120002463 - high capacity low cost multi-state magnetic memory: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.... Agent: Avalanche Technology, Inc.
20120002461 - Non-volatile memory with ovonic threshold switch and resistive memory element: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a resistive memory element with an ovonic threshold switch. The ovonic threshold switch may be connected in series with the resistive memory element and may... Agent:
20120002462 - Resistance-change semiconductor memory: According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory... Agent: Kabushiki Kaisha Toshiba
20120002465 - Methods, structures, and devices for reducing operational energy in phase change memory: Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in... Agent: Micron Technology, Inc.
20120002464 - Semiconductor device equipped with a plurality of memory banks and test method of the semiconductor device: A write circuit writes a first data signal that is an input data signal that indicates a first logic level to each memory bank in sequence and writes a second data signal that is an input data signal that indicates a second logic level to each memory bank simultaneously.... Agent: Elpida Memory, Inc.
20120002466 - Storage apparatus: Disclosed herein is a storage apparatus including a cell array configured to include storage devices arranged to form an array. Each of the storage device has: a storage layer for storing information as the state of magnetization of a magnetic substance; a fixed-magnetization layer having a fixed magnetization direction; and... Agent: Sony Corporation
20120002467 - Single transistor memory cell: A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the... Agent: Micron Technology, Inc.
20120002470 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the... Agent: Kabushiki Kaisha Toshiba
20120002469 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells selected by word lines and bit lines, each memory cell being capable of storing N-bit data, a set of n-th bits of a plurality of memory cells selected by one... Agent: Kabushiki Kaisha Toshiba
20120002471 - Memory bit redundant vias: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH... Agent: Texas Instruments Incorporated
20120002472 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device according to an embodiment includes: a data write portion configured to repeat a write loop until data write is complete, the write loop including a program operation of applying a selected word-line with a program voltage necessary for program and a verify operation of applying... Agent: Kabushiki Kaisha Toshiba
20120002473 - Background power consumption reduction of electronic devices: An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one... Agent: Stmicroelectronics S.r.l.
20120002474 - Interleaved memory program and verify method, device and system: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory... Agent: Round Rock Research, LLC
20120002475 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path... Agent:
20120002476 - Semiconductor memory with improved block switching: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are... Agent:
20120002477 - Memories and their formation: Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the... Agent: Micron Technology, Inc.
20120002478 - Non-volatile semiconductor memory device: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated... Agent: Kabushiki Kaisha Toshiba
20120002479 - Circuit for the optimization of the programming of a flash memory: A non volatile memory device is provided. The memory device includes a plurality of memory cells and programming means. The programming circuitry is configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. the... Agent: Stmicroelectronics S.r.l.
20120002481 - Method of programming a non-volatile memory device: A method of programming a non-volatile memory device includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a program operation, wherein the word lines do not include a second word line adjacent to the... Agent: Hynix Semiconductor Inc.
20120002480 - Nonvolatile memory apparatus: A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a... Agent: Hynix Semiconductor Inc.
20120002468 - Cell deterioration warning apparatus and method: Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming... Agent: Micron Technology, Inc.
20120002482 - Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse: Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on... Agent:
20120002483 - Non-volatile memory and method with reduced neighboring field errors: A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same... Agent:
20120002484 - Operation methods for memory cell and array for reducing punch through leakage: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain... Agent: Macronix International Co., Ltd.
20120002485 - Semiconductor memory device: In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation... Agent: Panasonic Corporation
20120002490 - Semiconductor storage device: where Ncell is number of memory cells connected to each of the bit lines, NWL is a unit of number of word lines multiply-selected by the row selector, Cbl is a value obtained by dividing a capacitance of the bit line by Ncell, VDD is a power supply voltage, Tcyc... Agent: Kabushiki Kaisha Toshiba
20120002488 - Current detection method: A current detection method for detecting whether data are stored in a memory unit includes the steps of: (A) respectively inputting two currents into a detection current input end and a reference current end; (B) reading out a current of the detection current input end by a first switching element... Agent: Ipgoal Microelectronics (sichuan) Co., Ltd.
20120002489 - Signal driver circuit having adjustable output voltage for a high logic level output signal: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input... Agent: Micron Technology, Inc.
20120002491 - Test signal generating device, semiconductor memory apparatus using the same and multi-bit test method thereof: A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed.... Agent: Hynix Semiconductor Inc.
20120002492 - Data transfer circuit of semiconductor apparatus: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control... Agent: Hynix Semiconductor Inc.
20120002486 - Nonvolatile memory apparatus and method for processing configuration information thereof: A nonvolatile memory apparatus includes a memory device including a configuration information storage block for storing configuration data groups. A configuration information processing circuit is configured to determine majorities of configuration data groups, which are outputted from the memory device during a first period as an initial stage of a... Agent: Hynix Semiconductor Inc.
20120002487 - Nonvolatile memory apparatus and method for processing configuration information thereof: A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first... Agent: Hynix Semiconductor Inc.
20120002493 - Output enable signal generation circuit of semiconductor memory: An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation... Agent: Hynix Semiconductor Inc.
20120002495 - Memory system, memory test system and method of testing memory system and memory test system: A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal... Agent:
20120002494 - Test mode control circuit in semiconductor memory device and test mode entering method thereof: A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a... Agent:
20120002497 - Circuit and method for controlling standby leakage current in random access memory devices: A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode,... Agent: Elite Semiconductor Memory Technology Inc.
20120002496 - Circuit and method for eliminating bit line leakage current in random access memory devices: A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a... Agent: Elite Semiconductor Memory Technology Inc.
20120002498 - Nonvolatile memory, data processing apparatus, and microcomputer application system: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a... Agent: Renesas Electronics Corporation
20120002499 - Power control of an integrated circuit memory: An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the... Agent:
20120002500 - Multi-voltage level, multi-dynamic circuit structure device: A multi-voltage level, multi-dynamic circuit structure device and method are disclosed. In a particular embodiment, the method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first... Agent: Qualcomm IncorporatedPrevious industry: Electric power conversion systems
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