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Static information storage and retrieval December patent applications/inventions, industry category 12/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/29/2011 > 48 patent applications in 31 patent subcategories.
20110317462 - System for dynamically managing power consumption in a search engine: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during... Agent:
20110317463 - Semiconductor memory device: A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a... Agent: Kabushiki Kaisha Toshiba
20110317464 - Portable information apparatus: The present disclosure provides a portable information apparatus, including, an apparatus main body, an incidental article mounted on the apparatus main body when the portable information apparatus is used, a solid-state magnetic memory provided at a portion of the apparatus main body at which the incidental article is mounted and... Agent: Sony Corporation
20110317465 - Methods and systems for reducing heat flux in memory systems: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus.... Agent:
20110317466 - High read speed memory with gate isolation: Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory... Agent: Spansion LLC
20110317467 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.... Agent: Fujitsu Semiconductor Limited
20110317468 - Non-volatile memory with split write and read bitlines: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in... Agent: Qualcomm Incorporated
20110317469 - Non-volatile sampler: A non-volatile sampler including a row line for receiving an input signal to be sampled, the row line intersecting a number of column lines, non-volatile storage elements being disposed at intersections between the row line and the column lines; a bias voltage source connected to the column lines, the bias... Agent: Hewlett-packard Development Company, L.p.
20110317472 - Nonvolatile semiconductor memory device: A memory cell array having a 1R structure is composed of nonvolatile variable resistive elements each including a variable resistor formed of a metal oxide film whose resistance changes depending on an oxygen concentration in the film, and first and second electrodes sandwiching the variable resistor. The first electrode and... Agent:
20110317471 - Nonvolatile stacked nand memory: A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode... Agent: Macronix International Co., Ltd.
20110317470 - Rectification element and method for resistive switching for non volatile memory device: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of... Agent: The Regents Of The University Of Michigan
20110317473 - System and method for mitigating reverse bias leakage: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of... Agent: Micron Technology, Inc.
20110317475 - Electronic device: A capacitor element is arranged in series with a specific transmission path branching from a predetermined node of a signal transmission path and reaching to a ground plane, the signal transmission path supplying an enable control signal that indicates the validity of a clock signal and a command and address... Agent: Renesas Electronics Corporation
20110317474 - Semiconductor device: A semiconductor device includes a source line, a bit line, and first to m-th (m is a natural number) memory cells connected in series between the source line and the bit line. Each of the first to m-th memory cells includes a first transistor having a first gate terminal, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110317476 - Bit-by-bit write assist for solid-state memory: A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power supply node and ground. One of the... Agent: Texas Instruments Incorporated
20110317477 - Cell structure for dual-port sram: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110317478 - Method and circuit arrangement for performing a write through operation, and sram array with write through capability: An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a... Agent: International Business Machines Corporation
20110317479 - Shared bit line smt mram array with shunting transistors between the bit lines: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair... Agent: Magic Technologies, Inc.
20110317483 - Data programming circuits and memory programming methods: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the... Agent: Nanya Technology Corporation
20110317480 - Phase change memory coding: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after... Agent: Macronix International Co., Ltd,
20110317482 - Phase change memory word line driver: A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word... Agent: Mosaid Technologies Incorporated
20110317481 - Planar phase-change memory cell with parallel electrical paths: A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle... Agent: International Business Machines Corporation
20110317484 - Resistive memory devices using assymetrical bitline charging and discharging: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a... Agent: Samsung Electronics Co., Ltd.
20110317486 - Methods for operating a semiconductor device: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a... Agent: Imec
20110317485 - Structure and method for sram cell circuit: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110317487 - Multiple-bit per cell (mbc) non-volatile memory apparatus and system having polarity control and method of programming same: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize... Agent: Mosaid Technologies Incorporated
20110317488 - Data reading method and control circuit and memory controller using the same: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an... Agent: Phison Electronics Corp.
20110317489 - Nonvolatile memory devices, read methods thereof and memory systems including the nonvolatile memory devices: Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one... Agent: Samsung Electronics Co., Ltd.
20110317490 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected... Agent: Oki Semiconductor Co., Ltd.
20110317491 - Memory read methods, apparatus, and systems: Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number... Agent:
20110317492 - Method of using a nonvolatile memory cell: An electronic device can include a nonvolatile memory cell. In a particular embodiment, during an erase pulse, all unselected lines are at substantially the same voltage, and a row or segment of a row, such as a word, is erased during the erase pulse. In another embodiment, selected control gate... Agent:
20110317493 - Method and apparatus of performing an erase operation on a memory integrated circuit: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient... Agent: Macronix International Co., Ltd.
20110317500 - Semiconductor device and method for driving the same: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110317494 - Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure: Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first... Agent: Hynix Semiconductor Inc.
20110317495 - Memory system and control method therefor: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the... Agent: Elpida Memory, Inc.
20110317496 - Jam latch for latching memory array output data: A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation... Agent: International Business Machines Corporation
20110317497 - Non-volatile memory device: A non-volatile memory device for measuring a read current of a unit cell is disclosed. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection signal, a sense amplifier controlled... Agent: Hynix Semiconductor Inc.
20110317498 - Non-volatile storage device: There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply... Agent: Oki Semiconductor Co., Ltd.
20110317499 - Split voltage level restore and evaluate clock signals for memory address decoding: A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode... Agent: International Business Machines Corporation
20110317501 - Semiconductor device and control method thereof: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the... Agent: Renesas Electronics Corporation
20110317502 - Control of inputs to a memory device: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy... Agent: Micron Technology, Inc.
20110317504 - Memory component having a write-timing calibration mode: In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal... Agent:
20110317503 - Semiconductor device: A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output... Agent: Elpida Memory, Inc.
20110317505 - Internal bypassing of memory array devices: An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic... Agent: International Business Machines Corporation
20110317506 - Method for asymmetric sense amplifier: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110317507 - Semiconductor memory and method for operating the semiconductor memory: A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address ,signal in a second period; a decode circuit that sequentially decodes the first... Agent: Fujitsu Semiconductor Limited
20110317509 - Memory device word line drivers and methods: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such... Agent: Micron Technology, Inc.
20110317508 - Memory write operation methods and circuits: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.... Agent:12/22/2011 > 45 patent applications in 29 patent subcategories.
20110310648 - Semiconductor storage device: A first comparator compares data output to a bit line from a memory cell with first search data by activating a word line. A second comparator compares data output to a bit line from the memory cell with second search data by activating a word line. Data output to a... Agent: Renesas Technology Corporation
20110310649 - Stacked memory module and system: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system.... Agent:
20110310650 - semiconductor memory device and a method of operating thereof: In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the... Agent: Panasonic Corporation
20110310651 - Variable impedance circuit controlled by a ferroelectric capacitor: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second... Agent:
20110310658 - Combined memories in integrated circuits: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may... Agent: Unity Semiconductor Corporation
20110310655 - Composition of memory cell with resistance-switching layers: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at... Agent:
20110310653 - Memory cell with resistance-switching layers: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at... Agent:
20110310654 - Memory cell with resistance-switching layers and lateral arrangement: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The... Agent:
20110310656 - Memory cell with resistance-switching layers including breakdown layer: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A... Agent:
20110310657 - Resistive memory devices including selected reference memory cells operating responsive to read operations: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.... Agent:
20110310652 - Variable resistance devices, semiconductor devices including the variable resistance devices, and methods of operating the semiconductor devices: Methods of operating semiconductor devices that include variable resistance devices, the methods including writing first data to a semiconductor device by applying a reset pulse voltage to the variable resistance device so that the variable resistance device is switched from a first resistance state to a second resistance state, and... Agent: Samsung Electronics Co., Ltd.
20110310659 - Voltage-controlled oscillator and phase-locked loop circuit: A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit... Agent: Samsung Electronics Co., Ltd.
20110310660 - Magnetoresistance element and storage device using the same: A magnetic memory element having a memory cell of size 4F2 is provided that realizes a crosspoint-type memory. In the magnetic memory element, a first magnetic layer, a third magnetic layer (spin polarization enhancement layer), an intermediate layer, a fourth magnetic layer (spin polarization enhancement layer), and a second magnetic... Agent: Fuji Electric Co., Ltd.
20110310661 - Memory sensing devices, methods, and systems: The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and... Agent: Micron Technology, Inc.
20110310662 - Structure and method for biasing phase change memory array for reliable writing: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory... Agent:
20110310663 - Method for driving storage element and storage device: Disclosed herein is a method for driving a storage element that has a plurality of magnetic layers and performs recording by utilizing spin torque magnetization reversal, the method including applying a pulse voltage having reverse polarity of polarity of a recording pulse voltage in application of the recording pulse voltage... Agent: Sony Corporation
20110310665 - Nonvolatile memory device: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor... Agent:
20110310668 - Flash memory device and program method thereof: A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic... Agent:
20110310666 - Programming method for nand flash memory device to reduce electrons in channels: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell... Agent:
20110310667 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality... Agent:
20110310669 - Logic-based multiple time programming memory cell: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located... Agent:
20110310670 - Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings... Agent: Samsung Electronics Co., Ltd.
20110310671 - Reducing the impact of interference during programming: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior... Agent:
20110310672 - Threshold voltage digitizer for array of programmable threshold transistors: A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as... Agent:
20110310664 - Non-volatile memory apparatus and methods: Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus... Agent:
20110310673 - Multi-page program method, non-volatile memory device using the same, and data storage system including the same: A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with... Agent: Samsung Electronics Co., Ltd
20110310674 - System and method for bit-line control: In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal... Agent: Infineon Technologies Ag
20110310675 - Local sensing in a memory device: Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is... Agent: Micron Technology, Inc.
20110310680 - Interleave memory array arrangement: A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that... Agent: International Business Machines Corporation
20110310676 - Memory sensing with secondary buffer: A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the device is enabled by an architecture and method of operation... Agent:
20110310677 - Semiconductor memory device capable of read out mode register information through dq pads: A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a... Agent: Hynix Semiconductor Inc.
20110310678 - Sensing circuit for memory cell supplied with low power: An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory... Agent:
20110310679 - Devices, systems, and methods for a power generator system: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference... Agent: Micron Technology, Inc.
20110310681 - Semiconductor device: A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the... Agent: Renesas Electronics Corporation
20110310682 - Delay-locked loop having loop bandwidth dependency on operating frequency: Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its operating frequency. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its operating frequency. In this... Agent: Hynix Semiconductor Inc.
20110310683 - Non-volatile memory control: Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a... Agent: Micron Technology, Inc.
20110310684 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a P-type MOS transistor and two or more N-type MOS transistors connected together in series between a first and a second power supply, an input terminal connected to a gate terminal of the P-type MOS transistor and gate terminals of the two or more N-type... Agent: Panasonic Corporation
20110310685 - Memory module including parallel test apparatus: A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data for write data including a plurality of... Agent:
20110310686 - Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells).... Agent: Google Inc.
20110310688 - Current mode data sensing and propagation using voltage amplifier: A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from... Agent:
20110310687 - Current sense amplifiers, memory devices and methods: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input... Agent: Micron Technology, Inc.
20110310689 - Power source and power source control circuit: Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control circuit. The input is configured to be coupled to... Agent: Micron Technology, Inc.
20110310690 - Voltage regulators, memory circuits, and operating methods thereof: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110310691 - Multi-port memory using single-port memory cells: A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including... Agent: Lsi Corporation
20110310692 - Sequential-write, random-read memory: In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is... Agent: Fujitsu Limited12/15/2011 > 44 patent applications in 27 patent subcategories.
20110305057 - Semiconductor memory device, memory controller, and data processing system including these: In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip,... Agent: Elpida Memory, Inc.
20110305058 - Nonvolatile memory device and method of fabricating same: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second... Agent: Samsung Electronics Co., Ltd.
20110305059 - Semiconductor memory devices: Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array... Agent: Samsung Electronics Co., Ltd.
20110305060 - Wiring substrate in which equal-length wires are formed: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a... Agent: Murata Manufacturing Co., Ltd.
20110305061 - Ferroelectric memories based on arrays of autonomous memory bits: A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit... Agent:
20110305062 - Memory cell and memory device using the same: Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference... Agent: Electronics And Telecommunications Research Institute
20110305071 - Continuous programming of non-volatile memory: A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control... Agent:
20110305064 - Interface control for improved switching in rram: A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first... Agent: Crossbar, Inc.
20110305065 - Non-volatile variable capacitive device including resistive memory cell: A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed... Agent: Crossbar, Inc.
20110305069 - Nonvolatile memory device using resistance material and memory system including the nonvolatile memory device: A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the... Agent: Samsung Electronics Co., Ltd.
20110305070 - Resistance control method for nonvolatile variable resistive element: A resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device is provided. The device includes a memory cell array in which unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a... Agent:
20110305068 - Resistance random access change memory device: A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends... Agent: Sony Corporation
20110305067 - Semiconductor memory device in which resistance state of memory cell is controllable: According to one embodiment, a semiconductor memory device includes memory cells and sense amplifiers. One end of the memory cell is connected to each of bit lines. The other end of the memory cell is connected to a source line. The sense amplifiers are connected to the bit lines. First... Agent: Kabushiki Kaisha Toshiba
20110305063 - Sense amplifier for reading a crossbar memory array: A sense amplifier for reading the data stored in a crossbar array includes a storage transistor to store a first voltage resulting from an electric current from a column line connected to a target memory element while the target memory element is half-selected, the first voltage resulting from bias voltages... Agent: Hewlett-packard Development Company, L.p.
20110305066 - Write and erase scheme for resistive memory device: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal... Agent: Crossbar, Inc.
20110305072 - Semiconductor memory device: A semiconductor memory device is provided in which erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports. The first write driver applies voltage corresponding to the first write data to the first bit line, when activated. The first write assist... Agent: Renesas Electronics Corporation
20110305073 - Semiconductor memory device: A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second... Agent: Kabushiki Kaisha Toshiba
20110305076 - Phase change memory device: A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged... Agent: Kabushiki Kaisha Toshiba
20110305075 - Programmable resistance memory: A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.... Agent:
20110305074 - Self-aligned bit line under word line memory array: A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and... Agent: Macronix International Co., Ltd.
20110305078 - Low cost multi-state magnetic memory: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current... Agent: Avalanche Technology, Inc.
20110305077 - Memory device: Disclosed herein is a memory device, including: a memory element including a memory layer for holding therein information in accordance with a magnetization state of a magnetic material, a fixed magnetization layer which is provided on the memory layer through a non-magnetic layer and whose direction of a magnetization is... Agent: Sony Corporation
20110305080 - Post-facto correction for cross coupling in a flash memory: A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that... Agent:
20110305081 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result... Agent: Samsung Electronics Co., Ltd.
20110305082 - Methods and apparatus for soft data generation for memory devices: Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics... Agent:
20110305083 - Nonvolatile memory device: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting... Agent: Samsung Electronics Co., Ltd.
20110305084 - Non-volatile memory device: A non-volatile memory device includes; a first well having a first impurity concentration formed in a first region of a semiconductor substrate, a second well having a second impurity concentration different from the first impurity concentration formed in a second region of the semiconductor substrate, an access transistor with floating... Agent: Samsung Electronics Co., Ltd.
20110305085 - Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location... Agent:
20110305086 - Semiconductor memory device: A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to... Agent: Kabushiki Kaisha Toshiba
20110305087 - Flash memory device and reading method thereof: A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and... Agent: Samsung Electronics Co., Ltd.
20110305088 - Hot carrier programming in nand flash: A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot... Agent: Macronix International Co., Ltd.
20110305089 - Threshold detecting method and verify method of memory cells: According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the... Agent:
20110305090 - Memory controller self-calibration for removing systemic influence: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as,... Agent: Micron Technology, Inc.
20110305079 - Nonvolatile memory device including dummy memory cell and program method thereof: A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy... Agent: Samsung Electronics Co., Ltd.
20110305091 - Semiconductor memory device and related methods for performing read and verification operations: A semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a read operation the memory cell array by sensing a bitline in a plurality of reading steps in response to a single read command, and a sensing time controller configured to... Agent: Samsung Electronics Co., Ltd.
20110305092 - Non-volatile memory device with controlled discharge: An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed. The memory device includes a plurality of sectors of memory cells each one being formed in a respective well of the chip; each sector includes a plurality word lines each one for accessing a... Agent: Stmicroelectronics S.r.l.
20110305093 - Data input/output circuit and method of semiconductor memory apparatus: A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the... Agent: Hynix Semiconductor Inc.
20110305094 - Non-volatile memory device with reconnection circuit: An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for... Agent: Stmicroelectronics S.r.i
20110305095 - System and method for memory array decoding: A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in... Agent:
20110305096 - Circuit for reading non-volatile memory cells and memory system comprising the circuit: A circuit for reading memory cells includes: a sense node connectable to a memory cell; a sense device connected to the sense node and configured to be activated in a precharging step which precedes a cell reading step and to provide such an output signal to assume logic values dependant... Agent: Stmicroelectronics S.r.l.
20110305097 - Semiconductor device and data processing system: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line,... Agent: Elpida Memory, Inc.
20110305099 - Hierarchical buffered segmented bit-lines based sram: A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the... Agent: Imec
20110305098 - Semiconductor memory device with sense amplifier and bitline isolation: A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry... Agent:
20110305100 - Semiconductor memory device: A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region... Agent: Samsung Electronics Co., Ltd.12/08/2011 > 42 patent applications in 25 patent subcategories.
20110299315 - Communication circuit for driving a plurality of devices: A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one embodiment of the invention, an electronic system includes a... Agent: Qualcomm Incorporated
20110299314 - Non-volatile memory having 3d array of read/write elements with efficient decoding of vertical bit lines and word lines: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar... Agent:
20110299316 - Memory module, method and memory system having the memory module: The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second... Agent:
20110299317 - Integrated circuit heating to effect in-situ annealing: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a... Agent:
20110299318 - Semiconductor memory cell and manufacturing method thereof, and semiconductor memory devices: A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film... Agent: Panasonic Corporation
20110299323 - Floating source line architecture for non-volatile memory: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a... Agent: Seagate Technology LLC
20110299322 - Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device: A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high... Agent:
20110299319 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write... Agent: Kabushiki Kaisha Toshiba
20110299320 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the... Agent: Kabushiki Kaisha Toshiba
20110299321 - Semiconductor memory device: A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at... Agent: Kabushiki Kaisha Toshiba
20110299324 - Write current compensation using word line boosting circuitry: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device,... Agent: Seagate Technology LLC
20110299327 - Four-transistor and five-transistor bjt-cmos asymmetric sram cells: A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common... Agent: Ndep Technologies Ltd
20110299325 - Sram devices and methods of manufacturing the same: Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be... Agent: Samsung Electronics Co., Ltd.
20110299326 - Tfet based 4t memory devices: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a... Agent: The Penn State Research Foundation
20110299329 - Bottom electrode geometry for phase change memory: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current... Agent: Micron Technology, Inc.
20110299328 - Memory arrays: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into... Agent:
20110299330 - Pseudo page mode memory architecture and method: A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled... Agent: Grandis, Inc.
20110299331 - Flash memory program inhibit scheme: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a... Agent: Mosaid Technologies Incorporated
20110299335 - Memory system and method of accessing a semiconductor memory device: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the... Agent:
20110299333 - Non-volatile memory programming: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices... Agent:
20110299334 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array connected to word lines and bit lines, and formed by arranging a plurality of memory cells in a matrix, each memory cell storing one of n values (n is a natural number of not less than... Agent:
20110299336 - Single-polysilicon layer non-volatile memory and operating method thereof: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate... Agent: Ememory Technology Inc.
20110299338 - Memory system and method of accessing a semiconductor memory device: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the... Agent: Samsung Electronics Co., Ltd.
20110299337 - Methods and apparatus for an isfet: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the... Agent: Freescale Semiconductor, Inc.
20110299339 - Nonvolatile semiconductor memory, method for reading out thereof, and memory card: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said... Agent: Kabushiki Kaisha Toshiba
20110299332 - Test system and high voltage measurement method: Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more... Agent: Samsung Electronics Co., Ltd.
20110299340 - Non-volatile memory having 3d array of read/write elements and read/write circuits and method thereof: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to... Agent:
20110299341 - Method of programming a semiconductor memory device: A method of programming a semiconductor memory device includes the steps of grouping memory cells in accordance with levels of threshold voltages to be programmed, programming the memory cell groups by sequentially applying program voltages to the memory cell groups, and program-verifying the memory cell groups.... Agent:
20110299342 - Flash memory device and systems and reading methods thereof: A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a plurality of coupling compensation parameters;... Agent:
20110299343 - Non-volatile memory device, precharge voltage controlling method thereof, and system including the same: A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured... Agent:
20110299345 - Early read after write operation memory device, system and method: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory... Agent: Rambus Inc.
20110299344 - A new low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense mosfet: A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first... Agent:
20110299346 - Apparatus for source-synchronous information transfer and associated methods: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.... Agent:
20110299347 - Dynamic detection of a strobe signal within an integrated circuit: A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method... Agent: Xilinx, Inc.
20110299348 - Semiconductor memory device and integrated circuit: A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time point of a read command to an end time... Agent: Hynix Semiconductor Inc.
20110299349 - Margin testing of static random access memory cells: A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The... Agent: Texas Instruments Incorporated
20110299350 - Precharge control circuit and integrated circuit including the same: A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for generating an operating voltage for controlling the voltage level of the precharge control signal in response to a first enable signal... Agent: Hynix Semiconductor Inc.
20110299351 - Input/output bank architecture for an integrated circuit: An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled... Agent: Xilinx, Inc.
20110299353 - Power saving memory apparatus, systems, and methods: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage... Agent:
20110299352 - Semiconductor device including memory cells that require refresh operation: A semiconductor device includes a first circuit that generates a self refresh signal in a predetermined cycle asynchronous with a cycle set externally, a second circuit that generates a refresh address in response to the self refresh signal and updates the refresh address and outputs the refresh address, a third... Agent: Elpida Memory, Inc.
20110299354 - Memory array circuit incorporating multiple array block selection and related method: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent:
20110299355 - Word line driver for memory: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal... Agent: Stmicroelectronics Pvt. Ltd.12/01/2011 > 48 patent applications in 30 patent subcategories.
20110292707 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled... Agent: Hynix Semiconductor Inc.
20110292708 - 3d semiconductor device: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only... Agent:
20110292709 - Semiconductor device: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third... Agent: Elpida Memory, Inc.
20110292710 - Semiconductor device and control method therefor: A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially... Agent: Elpida Memory, Inc.
20110292711 - Data encoding scheme to reduce sense current: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses... Agent:
20110292716 - Asymmetric write current compensation using gate overdrive for resistive sense memory cells: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching... Agent: Seagate Technology LLC
20110292712 - Reading a memory element within a crossbar array: A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying... Agent: Hewlett-packard Development Company, L.p.
20110292713 - Reading a memory element within a crossbar array: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage... Agent: Hewlett-packard Development Company, L.p.
20110292715 - Semiconductor memory device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to... Agent:
20110292714 - Structures and methods for a field-reset spin-torque mram: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through... Agent: Everspin Technologies, Inc.
20110292717 - Semiconductor device: A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is... Agent: Elpida Memory, Inc.
20110292718 - Non-volatile logic circuit: A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input... Agent:
20110292721 - Adaptive wordline programming bias of a phase change memory: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused... Agent:
20110292719 - Phase-change memory device: A phase-change memory device includes: a cell array including at least one unit cell; a current sensing unit sensing data stored in the at least one unit cell; and a power generation circuit supplying a power source voltage to the current sensing unit, in which the power generation circuit is... Agent: Hynix Semiconductor Inc.
20110292720 - Phase-change memory device: A phase-change memory device includes: a unit cell including a phase-change resistor; a sense amplifier applying a sensing current to the phase-change resistor; and a switching unit operating in a standby mode or a read mode according to a global line signal and controlling passing presence of the sensing current... Agent: Hynix Semiconductor Inc.
20110292722 - Semiconductor device: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and... Agent: Hitachi, Ltd.
20110292723 - Dram cell utilizing floating body effect and manufacturing method thereof: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N... Agent: Shanghai Institute Of Microsystem And Information Technology Chinese Academy
20110292725 - Flash memory device and system with program sequencer, and programming method: A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program... Agent: Samsung Electronics Co., Ltd.
20110292728 - Integrated circuit of device for memory cell: A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the... Agent: Macronix International Co., Ltd.
20110292726 - Nonvolatile memory device capable of reducing read disturbance and read method thereof: Provided are a nonvolatile memory device and a read method of the same. The read method applying one of a plurality of unselected read voltages to unselected wordlines adjacent to a selected word line. The voltage applied to the unselected word lines being based on which of a plurality of... Agent: Samsung Electronics Co., Ltd.
20110292724 - Nonvolatile memory device, system and programming method with dynamic verification mode selection: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification... Agent: Samsung Electronics Co., Ltd.
20110292727 - Semiconductor memory having electrically erasable and programmable semiconductor memory cells: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to... Agent:
20110292729 - Method of controlling non-volatile memory device: A method of controlling a non-volatile memory device includes comparing the number of banks that are in operating states with a threshold value. If the number of the banks is smaller than the threshold value, data stored in a standby bank is read. If there is no bank having data... Agent:
20110292730 - Semiconductor integrated circuit apparatus having configuration that enables plane area reduction: Various embodiments of a semiconductor integrated circuit apparatus are disclosed. In one exemplary embodiment, the apparatus may include a memory cell array having a plurality of memory cell blocks, a plurality of word line selection sections corresponding to the plurality of memory cell blocks, a block selection unit configured to... Agent: Hynix Semiconductor Inc.
20110292732 - Nand memory device and programming methods: A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. A NAND flash cell is programmed by coupling a first memory array... Agent:
20110292731 - Three-dimensional non-volatile memory devices having highly integrated string selection and sense amplifier circuits therein: Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on... Agent:
20110292733 - Electrically programmable floating common gate cmos device and applications thereof: A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The... Agent: International Business Machines Corporation
20110292734 - Method of programming nonvolatile memory device: A method of programming a semiconductor device includes performing an initial program operation on all memory cells included in a selected memory cell block to set threshold voltages of all the memory cells to a voltage equal to or greater than 0 Volts, erasing memory cells of a selected page... Agent:
20110292735 - Nonvolatile memory device with reduced current consumption: A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and... Agent: Nscore Inc.
20110292736 - Semiconductor memory device and control method thereof: According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data... Agent:
20110292737 - Nonvolatile memory apparatus: A nonvolatile memory apparatus includes: a plurality of drain selection switches coupled to a plurality of memory cell strings, respectively; and a drain selection switch controller configured to selectively drive a drain selection switch coupled to an even bit line or a drain selection switch coupled to an odd bit... Agent: Hynix Semiconductor Inc.
20110292738 - Nand-based 2t2b nor flash array with a diode connection to cell's source node for size reduction using the least number of metal layers: A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be... Agent:
20110292741 - Memory apparatus and associated method: A memory apparatus includes a plurality of first bit columns for constructing a common memory space and at least one reserve second bit column. A column address of a damaged first bit column is recorded as a predetermined column address. When a byte column is accessed, data recorded in the... Agent: Mstar Semiconductor, Inc.
20110292740 - Semiconductor device and method for operating the same: A semiconductor device includes a data alignment unit configured to align serial input data in response to a data strobe signal, a data latching unit configured to latch an output signal of the data alignment unit in response to first and second synchronization pulse signals which are activated according to... Agent:
20110292739 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal, a latching operation control unit configured to receive the data strobe signal, and generate a latching control signal after an interval between a write operation and... Agent:
20110292742 - Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias: A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between... Agent: Samsung Electronics Co., Ltd.
20110292744 - Non-volatile memory device and method for operating the same: A non-volatile memory device includes a plurality of input pads, a buffer configured to buffer data inputted through the plurality of the input pads in synchronization with a write enable signal, an even latch configured to store a first buffered data outputted from the buffer in response to an even... Agent:
20110292743 - Sequential access memory elements: Integrated circuits with sequential access memory cells are provided. A sequential access memory cell may include an inverter-like circuit, an inverter, a preset transistor, an access transistor, and a read circuit. The inverter-like circuit and the inverter are cross-coupled to form a bi-stable latch that is powered by a positive... Agent:
20110292745 - Data transmission device: A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test... Agent: Hynix Semiconductor Inc.
20110292746 - Data transfer circuit, method thereof, and memory device including data transfer circuit: A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed... Agent:
20110292747 - Semiconductor memory device: In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient decoding operation for selecting a repair target address, a test operation of enabling only a word line... Agent:
20110292748 - Implementing low power data predicting local evaluation for double pumped arrays: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the... Agent: International Business Machines Corporation
20110292749 - Non-volatile memory device: A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat,... Agent: Hynix Semiconductor Inc.
20110292750 - Bit line sense amplifier control circuit and semiconductor memory apparatus having the same: A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control... Agent: Hynix Semiconductor Inc.
20110292751 - Methods and apparatus for extending the effective thermal operating range of a memory: Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a... Agent:
20110292752 - Semiconductor memory device having fuse elements programmed by irradiation with laser beam: A relief-address control unit of a semiconductor memory device includes a fuse storage unit and a relief circuit. The fuse storage unit includes a plurality of fuse elements that are made nonconductive by irradiation with a laser beam, and a protective film with an opening directly above the fuse elements... Agent: Elpida Memory, Inc.
20110292753 - Memory leakage and data retention control: A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110292754 - Memory word-line driver having reduced power consumption: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.Previous industry: Electric power conversion systems
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