Static information storage and retrieval patents - Monitor Patents
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents



USPTO Class 365  |  Browse by Industry: Previous - Next | All     monitor keywords
11/2011 | Recent  |  14: Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn |  | 2008 | 2007 |

Static information storage and retrieval November recently filed with US Patent Office 11/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
11/24/2011 > 42 patent applications in 30 patent subcategories. recently filed with US Patent Office

20110286254 - Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line... Agent: Samsung Electronics Co., Ltd.

20110286255 - Magnetic logic circuits formed with tapered magnetic wires: A magnetic circuit in one aspect comprises a plurality of tapered magnetic wires each having a relatively wide input end and a relatively narrow output end, with the output end of a first one of the tapered magnetic wires being coupled to the input end of a second one of... Agent: International Business Machines Corporation

20110286256 - Semiconductor device and method for driving semiconductor device: A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110286257 - Semiconductor memory device and method for driving semiconductor memory device: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory... Agent: Fujitsu Semiconductor Limited

20110286260 - Nonvolatile memory device and method for driving same: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between... Agent: Kabushiki Kaisha Toshiba

20110286258 - Nonvolatile memory device having a transistor connected in parallel with a resistance switching device: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor... Agent: Macronix International Co., Ltd.

20110286259 - Reading memory elements within a crossbar array: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric... Agent: Hewlett-packard Development Company, L.p.

20110286261 - Resistance change memory: According to one embodiment, a resistance change memory includes a memory cell array area and a resistive element area on a substrate. A first memory cell array in the memory cell array area includes a first control line, a second control line above first control line, and a first cell... Agent:

20110286262 - Semiconductor memory device: A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines,... Agent: Elpida Memory, Inc.

20110286263 - Memory device: Memory device, comprising a storage material, a first electrode connected to the storage material; and a second electrode associated to the storage material.... Agent: Sony Corporation

20110286264 - Magnetic random access memory and initializing method: A magnetic random access memory which includes a magnetic record layer which is ferromagnetic; a ferromagnetic magnetization fixed layer whose magnetization is fixed; and a non-magnetic spacer layer provided between the magnetic record layer and the magnetization fixed layer. The magnetic record layer includes a magnetization invertible region whose magnetization... Agent: Renesas Electronics Corporation

20110286266 - Memory semiconductor device and method of operating the same: In a read step or a program (write) verification step of a semiconductor memory device, read voltages different from one another are applied to a pair of word lines respectively disposed on both sides of a selected word line to suppress the enlargement of program distribution.... Agent:

20110286265 - Programming non-volatile storage with synchonized coupling: A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines... Agent:

20110286268 - Nonvolatile semiconductor memory: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the... Agent:

20110286267 - Pattern-sensitive coding of data for storage in multi-level memory cells: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each... Agent:

20110286269 - Non-volatile electronic memory device with nand structure being monolithically integrated on semiconductor: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory... Agent:

20110286270 - Semiconductor memory device and an operating method thereof: A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a... Agent:

20110286271 - Memory systems and methods for reading data stored in a memory cell of a memory device: A memory system is provided. A memory device includes multiple memory cells for storing data. A controller is coupled to the memory device for accessing the memory device. When reading the data stored in a memory cell, the controller receives a digital signal representing content of the data stored in... Agent: Mediatek Inc.

20110286272 - Memory devices and their operation with different sets of logical erase blocks: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a... Agent: Micron Technology, Inc.

20110286273 - Semiconductor device and method of controlling the same: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB... Agent:

20110286274 - Nonvolatile memory device, programming method thereof and memory system including the same: A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a... Agent:

20110286275 - Stacked memory devices and method of manufacturing the same: A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of... Agent: Samsung Electronics Co., Ltd.

20110286278 - Method of storing e-fuse data in flash memory device: Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string... Agent: Samsung Electronics Co., Ltd.

20110286276 - Partial local self boosting for nand: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the... Agent:

20110286277 - Semiconductor memory device and method for driving semiconductor memory device: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory... Agent: Fujitsu Semiconductor Limited

20110286279 - Erase and programming techniques to reduce the widening of state distributions in non-volatile memories: Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or... Agent:

20110286280 - Pulse control for nonvolatile memory: This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it... Agent: Rambus Inc.

20110286281 - Reference current generator used for programming and erasing of non-volatile memory: A reference current generator used for programming and erasing of the non-volatile memory. Wherein, a self-biasing reference generator is used to generate a first reference voltage of a negative temperature coefficient and a second reference voltage of a positive temperature coefficient. A voltage converter receives said first reference voltage and... Agent: Yield Microelectronics Corp.

20110286282 - Semiconductor memory column decoder device and method: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row... Agent: Micron Technology, Inc.

20110286283 - 3d two-bit-per-cell nand flash memory: A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground,... Agent: Macronix International Co., Ltd.

20110286284 - Multi-transistor non-volatile memory element: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating... Agent: Taiwan Semiconductor Manufacturing Company, Ltd., ("tsmc")

20110286290 - Driving method of semiconductor device: A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted.... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110286285 - Semiconductor integrated circuit for generating clock signals: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write... Agent: Hynix Semiconductor, Inc.

20110286286 - Semiconductor integrated circuit for generating clock signals: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write... Agent: Hynix Semiconductor, Inc.

20110286287 - Semiconductor memory device with optimum refresh cycle according to temperature variation: Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature,... Agent: Hynix Semiconductor Inc.

20110286288 - Dynamic adjustment of reference voltage in a computer memory system: A method provides improved signal quality in a computer memory system. In one embodiment, a digital signal is generated having a voltage interpreted with respect to a reference voltage. The reference voltage is dynamically adjusted as a function of the traffic intensity at which the digital signal is directed to... Agent: International Business Machines Corporation

20110286291 - Semiconductor memory device comprising a plurality of static memory cells: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power... Agent: Renesas Electronics Corporation

20110286289 - System and method of selectively varying supply voltage without level shifting data signals: An electronic system implements a plurality of voltage domains, at least one of which has a selectively variable supply voltage, without requiring the use of a large number of level shifters (e.g., for each data and/or address line). The supply voltage for a first domain is set equal or nearly... Agent:

20110286292 - Method of forming a unique number: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word... Agent:

20110286293 - Method of forming a unique number: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word... Agent:

20110286294 - Method of forming a unique number: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word... Agent:

20110286295 - Methods of arranging l-shaped cell blocks in semiconductor devices: Semiconductor devices are provided including a plurality of L-shaped cell blocks each including a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks is oriented in a diagonal direction intersecting the horizontal and vertical directions. Related... Agent:

  
11/17/2011 > 41 patent applications in 25 patent subcategories. recently filed with US Patent Office

20110280059 - Alternating bipolar forming voltage for resistivity-switching elements: A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and may refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. The method... Agent:

20110280057 - Memory device having a local current sink: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line.... Agent: Qualcomm Incorporation

20110280058 - Nonvolatile memory device: A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching... Agent: Macronix International Co., Ltd.

20110280060 - Write buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation

20110280061 - Semiconductor device: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110280064 - Composite resistance variable element and method for manufacturing the same: A composite resistance variable element includes a first resistance variable element in which a resistance value varies corresponding to a direction of inner magnetization, and a second resistance variable element connected in series to the first resistance variable element. A resistance value of the second resistance variable element varies corresponding... Agent: Fujitsu Limited

20110280062 - Semiconductor memory device: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first... Agent:

20110280063 - Spintronic devices with integrated transistors: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in... Agent: Micron Technology, Inc.

20110280065 - Write energy conservation in memory: A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the... Agent: Qualcomm Incorporated

20110280066 - Semiconductor device having a field effect source/drain region: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by... Agent:

20110280071 - Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data... Agent:

20110280069 - Iterative demodulation and decoding for multi-page memory architecture: Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each... Agent: Seagate Technology LLC

20110280068 - Joint encoding of logical pages in multi-page memory architecture: Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of... Agent: Seagate Technology LLC

20110280070 - Nonvolatile memory device, system comprising nonvolatile memory device, and read operation of nonvolatile memory device: A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell... Agent: Samsung Electronics Co., Ltd.

20110280072 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines;... Agent: Fujitsu Semiconductor Limited

20110280073 - Non-volatile static random access memory and operation method thereof: A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a... Agent: Industrial Technology Research Institute

20110280074 - Data writing method and data storage device: The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a... Agent: Silicon Motion, Inc.

20110280076 - Junctionless tft nand flash memory: A non-volatile memory device includes at least one junctionless transistor and a storage region. The junctionless transistor includes a junctionless, heavily doped semiconductor channel having two dimensions less than 100 nm.... Agent: Sandisk Corporation

20110280075 - Memory device and operating method thereof: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory... Agent: Robustflash Technologies Ltd.

20110280078 - Charge pump operation in a non-volatile memory device: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify... Agent: Micron Technology, Inc.

20110280080 - Memory with multi-page read: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.... Agent:

20110280077 - Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same: Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or... Agent: Micron Technology, Inc.

20110280079 - Nand flash memory programming: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices... Agent:

20110280081 - Non-volatile semiconductor memory: When a plurality of non-volatile memory cells in a memory cell array are simultaneously written, bit lines of the plurality of non-volatile memory cells are connected to M data lines, where M is an integer of two or more, based on a column address signal. N switches, where N is... Agent: Panasonic Corporation

20110280082 - Non-volatile memory programming: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a... Agent:

20110280083 - Nonvolatile memory device and program method thereof: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In... Agent: Samsung Electronics Co., Ltd.

20110280067 - Nonvolatile memory device, memory system having the same and programming method thereof: A non-volatile memory device which includes a sensing mode selector configured to select a sensing mode according to environment information. A page buffer senses a data state of a memory cell in one of a plurality of sensing methods, depending upon the selected sensing mode.... Agent:

20110280084 - Determining and using soft data in memory devices and systems: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the... Agent: Micron Technology, Inc.

20110280085 - Memory device having improved programming operation: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.... Agent:

20110280089 - Data bus power-reduced semiconductor storage apparatus: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of... Agent: Micron Technology, Inc.

20110280086 - Semiconductor memory device and semiconductor memory system: A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling... Agent: Samsung Electronics Co., Ltd.

20110280087 - Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein: A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator... Agent: Hynix Semiconductor, Inc.

20110280088 - Single supply sub vdd bitline precharge sram and method for level shifting: A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the... Agent: International Business Machines Corporation

20110280090 - Semiconductor device and test method thereof: For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a... Agent: Elpida Memory, Inc.

20110280091 - Memory repair systems and methods for a memory having redundant memory: Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a... Agent: Micron Technology, Inc.

20110280092 - Multi-bank read/write to reduce test-time in memories: Apparatuses and methods for multi-bank read/write architecture to reduce test time in memory devices are disclosed. A memory device can include a memory cell array including a plurality of memory banks. A bank decoding circuit can include logic configured to simultaneously select each of the plurality of memory banks. An... Agent: Qualcomm Incorporated

20110280093 - Data protective structure, electronic device, and method of erasing data: The present invention includes: a circuit board which is provided with an electronic circuit part; a first case and a second case (7) that cover the electronic circuit part; a fixing screw that fixes the first case and the second case (7); a tamper switch that outputs a signal indicating... Agent: Nec Display Solutions, Ltd.

20110280094 - Boost cell supply write assist: A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM... Agent: International Business Machines Corporation

20110280095 - Memory circuits having a plurality of keepers: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110280096 - Memory circuits having a plurality of keepers: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110280097 - Wordline driver for memory: Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.... Agent:

  
11/10/2011 > 34 patent applications in 25 patent subcategories. recently filed with US Patent Office

20110273919 - Read-only memory (rom) bitcell, array, and architecture: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a... Agent: Broadcom Corporation

20110273920 - Switching element and application of the same: A micro-switching element provided with a first electrode 4 containing an ionic conductor and a second electrode 5 composed of an electric conductor, wherein the first electrode 4 and the second electrode 5 are physically and electrically connected to each other through deposition of a metal ion from the ionic... Agent:

20110273921 - Integratable programmable capacitive device: A circuit with a capacitive device is disclosed. The circuit may comprise a capacitive device connected between a first conductor and a second conductor. The capacitive device may comprise a first electrode connected to the first conductor and a second electrode being connected to the second conductor. A chalcogenide layer... Agent:

20110273923 - Pass-gated bump sense amplifier for embedded drams: A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing... Agent: Stmicroelectronics Pvt.ltd

20110273924 - Semiconductor memory device: A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power... Agent:

20110273922 - Sense amplifier using reference signal through standard mos and dram capacitor: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first... Agent: Stmicroelectronics Pvt. Ltd.

20110273925 - Nonvolatile sram/latch circuit using current-induced magnetization reversal mtj: The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction... Agent: Tokyo Institute Of Technology

20110273926 - Method and apparatus of probabilistic programming multi-level memory in cluster states of bi-stable elements: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic... Agent: Qualcomm Incorporated

20110273927 - Semiconductor device: A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor... Agent: Hitachi, Ltd.

20110273928 - Method and system for providing a magnetic magnetic field aligned spin transfer torque random access memory: A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive... Agent: Grandis, Inc.

20110273929 - Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic... Agent: Micron Technology, Inc.

20110273930 - Diode memory: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.... Agent: Macronix International Co., Ltd.

20110273931 - Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling: Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.... Agent: Micron Technology, Inc.

20110273933 - Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device: An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An... Agent: Micron Technology, Inc.

20110273932 - Non-volatile memory with both single and multiple level cells: Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as... Agent: Micron Technology, Inc.

20110273934 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Apple Inc.

20110273935 - Mitigating channel coupling effects during sensing of non-volatile storage elements: Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established... Agent:

20110273936 - Erase process for use in semiconductor memory device: A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read... Agent: Macronix International Co., Ltd.

20110273941 - Techniques for refreshing a semiconductor memory device: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source... Agent: Innovative Silicon Isi Sa

20110273937 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect... Agent:

20110273938 - Circuit and method for controlling a clock synchronizing circuit for low power refresh operation: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that... Agent: Round Rock Research, LLC

20110273939 - Nonvolatile memory device: A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied... Agent: Kabushiki Kaisha Toshiba

20110273940 - Level shifting circuit: A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage... Agent: Micron Technology, Inc.

20110273942 - Memory array having a programmable word length, and method of operating same: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body... Agent: Micron Technology, Inc.

20110273944 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes first and second planes having a memory cell array that includes a plurality of memory cells coupled to bit lines, and page buffer groups that are coupled respectively to one or more of the bit lines and each include page buffers, and a common input/output... Agent:

20110273943 - System and method to read a memory cell with a complementary metal-oxide-semiconductor (cmos) read transistor: A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a... Agent: Qualcomm Incorporated

20110273945 - Techniques to improve the operations of a memory device: A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of its bit cells and domino logic for each of its bit line. Each bit... Agent:

20110273946 - Universal test structures based sram on-chip parametric test module and methods of operating and testing: An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The... Agent: Texas Instruments Incorporated

20110273948 - Semiconductor device and method of refreshing the same: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh... Agent: Elpida Memory, Inc.

20110273947 - Techniques for refreshing a semiconductor memory device: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of... Agent: Innovative Silicon Isi Sa

20110273949 - Electrical fuse programming time control scheme: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20110273950 - Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power... Agent: Power Integrations, Inc.

20110273951 - Memory circuit and method for controlling memory circuit: A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply... Agent:

20110273952 - Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating... Agent: Renesas Electronics Corporation

  
11/03/2011 > 54 patent applications in 40 patent subcategories. recently filed with US Patent Office

20110267865 - Configurable bandwidth memory devices and methods: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.... Agent:

20110267864 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a... Agent:

20110267866 - Extensible three dimensional circuit having parallel array channels: An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being... Agent: Hewlett-packard Development Company, L.p.

20110267867 - Semiconductor device: A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area... Agent:

20110267868 - Shift register memory device, shift register, and data storage method: According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction... Agent: Kabushiki Kaisha Toshiba

20110267869 - Circuit for verifying the write enable of a one time programmable memory: A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When... Agent:

20110267871 - Contemporaneous margin verification and memory access for memory cells in cross-point memory arrays: Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal... Agent: Unity Semiconductor Corporation

20110267870 - Decoders using memristive switches: A decoding structure employs a main terminal (130), a first memristive switch (112) connected between the main terminal (130) and a first addressable terminal (132), and a second memristive switch (114) connected between the main terminal (130) and a second addressable terminal (134). The second memristive switch (114) is oriented... Agent:

20110267872 - Resistance change memory device: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path... Agent: Kabushiki Kaisha Toshiba

20110267873 - Non-volatile memory with programmable capacitance: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer... Agent: Seagate Technology LLC

20110267874 - Invalid write prevention for stt-mram array: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line... Agent: Qualcomm Incorporated

20110267876 - Nonvolatile memory device using variable resistive element: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that... Agent: Samsung Electronics Co., Ltd.

20110267877 - Semiconductor device: A semiconductor device includes first and second phase-change memory elements (GST1 and GST2), each being programmed by a current supplied from a power supply (Vdd). A set voltage and a reset voltage supplied to a pair of complementary write bit lines (WBT and WBB) are applied respectively to gates of... Agent: Elpida Memory, Inc.

20110267875 - Semiconductor memory device and method for testing the same: A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first power-supply voltage to the memory cell array through the... Agent: Hynix Semiconductor Inc.

20110267878 - Josephson magnetic random access memory system and method: One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary... Agent:

20110267879 - Magnetic memory element and magnetic random access memory: A magnetic memory cell includes: a magnetization recording layer; and a magnetic tunneling junction section. The magnetization recording layer includes a ferromagnetic layer with perpendicular magnetic anisotropy. The magnetic tunneling junction section is used for reading information in the magnetization recording layer. The magnetization recording layer includes two domain wall... Agent: Nec Corporation

20110267880 - Memory circuits having a diode-connected transistor with back-biased control: A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110267881 - Memory array: A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source... Agent: Macronix International Co., Ltd.

20110267882 - Memory array with inverted data-lines pairs: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is... Agent: Micron Technology, Inc.

20110267883 - Dram-like nvm memory array and sense amplifier design for high temperature and high endurance operation: A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the... Agent:

20110267884 - Nonvolatile semiconductor memory system: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory... Agent: Kabushiki Kaisha Toshiba

20110267885 - Non-volatile memory and method with even/odd combined block decoding: A nonvolatile memory array is organized into a plurality of interleaving even and odd blocks. When a block is selected for operation, a set of word line voltages are delivered to the block of word lines by space-efficient decoding circuits and scheme. The plurality of blocks is organized into an... Agent:

20110267886 - Nonvolatile semiconductor memory device: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells... Agent: Kabushiki Kaisha Toshiba

20110267888 - Controlling select gate voltage during erase to improve endurance in non-volatile memory: A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach,... Agent:

20110267887 - Reducing energy consumption when applying body bias to substrate having sets of nand strings: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or... Agent:

20110267889 - A high second bit operation window method for virtual ground array with two-bit memory cells: A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable... Agent: Macronix International Co., Ltd.

20110267890 - Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to... Agent:

20110267891 - Driving circuit for memory device: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells... Agent: Stmicroelectronics S.r.i.

20110267892 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing... Agent:

20110267893 - Non-volatile semiconductor memory and memory system: A non-volatile semiconductor memory determines that a given memory cell in an array is at a predetermined threshold voltage in a determination circuit by comparing a current of the memory cell with a reference current in a sense amplifier circuit. A reference current generation circuit includes a current variable device... Agent: Panasonic Corporation

20110267895 - Method of operating semiconductor memory device: A method of operating a semiconductor memory device includes selecting one of a plurality of word lines, applying a program voltage, gradually dropping from a third level to a first level, to the selected word line, and discharging bit lines whenever a level of the program voltage is changed.... Agent:

20110267894 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a voltage transfer unit configured to transfer a first word line control voltage among a plurality of word line control voltages to an assigned word line in a first operational period, and to transfer a second word line control voltage among the plurality of word... Agent: Hynix Semiconductor Inc.

20110267896 - Non-volatile semiconductor memory with page erase: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A... Agent: Mosaid Technologies Incorporated

20110267897 - Non-volatile memory cells formed in back-end-of-line processes: A method for forming and operating an integrated circuit, including providing a substrate; forming a bottom electrode over the substrate, wherein the bottom electrode is in or over a lowest metallization layer over the substrate; forming a blocking layer over the substrate; forming a charge-trapping layer over the blocking layer;... Agent: Taiwan Semiconductor Manufacturing Company Ltd.

20110267903 - Semiconductor memory device having dram cell mode and non-volatile memory cell mode and operation method thereof: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected... Agent: Samsung Electronics Co., Ltd.

20110267899 - Non-volatile memory device and non-volatile memory system having the same: A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from... Agent:

20110267898 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a clock transmission unit configured to selectively output a data strobe clock signal or a phase correction clock signal based on an operation mode, and a data latch unit configured to latch a plurality of data signals under a control of a clock signal which... Agent: Hynix Semiconductor Inc.

20110267900 - Semiconductor memory device: A semiconductor memory device includes a pad, an impedance calibration circuit configured to provide a first code value corresponding to an impedance value coupled to the pad, a PVT sensing control circuit configured to provide a second code value corresponding to a PVT variation, and an output driver configured to... Agent:

20110267901 - Switched capacitor based negative bitline voltage generation scheme: A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20110267902 - Semiconductor device: A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit,... Agent: Oki Semiconductor Co., Ltd.

20110267904 - High speed interface for multi-level memory: A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of... Agent:

20110267905 - Semiconductor memory device and method for operating the same: A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal... Agent:

20110267906 - Measuring sdram control signal timing: Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to... Agent: International Business Machines Corporation

20110267907 - Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device: A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data... Agent:

20110267909 - Fuse circuit and semiconductor memory device including the same: The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing... Agent: Samsung Electronics Co., Ltd.

20110267908 - Repair circuit and repair method of semiconductor memory apparatus: A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding to the memory block determined to have... Agent: Hynix Semiconductor Inc.

20110267910 - Semiconductor integrated circuit including column redundancy fuse block: A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting... Agent: Hynix Semiconductor Inc.

20110267911 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to a common global line based on the level of a... Agent: Hynix Semiconductor Inc.

20110267912 - Digit line equilibration using access devices at the edge of sub arrays: A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second... Agent: Micron Technology, Inc.

20110267913 - Program method of semiconductor memory device: A program method of a semiconductor memory device may include precharging first bit lines, coupled to first strings, to increase a potential level of the first strings to a first potential level; programming memory cells of a selected word line, wherein the memory cells are coupled to second bit lines;... Agent:

20110267914 - Semiconductor memory device: Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral... Agent: Panasonic Corporation

20110267915 - Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse: Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of... Agent:

20110267916 - Vdd pre-set of direct sense dram: A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period.... Agent: International Business Machines Corporation

20110267917 - Row mask addressing: Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.... Agent:

Previous industry: Electric power conversion systems
Next industry: Agitating


######

RSS FEED for 20140410: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.



Results in 1.02789 seconds

PATENT INFO