|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
10/2011 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval October categorized by USPTO classification 10/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/27/2011 > 39 patent applications in 25 patent subcategories. categorized by USPTO classification
20110261602 - Magnetic memory devices and systems: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a... Agent: Ecole Polytechnique Federale De Lausanne (epfl)
20110261603 - Integrated circuit package with multiple dies and bundling of control signals: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater... Agent: Stmicroelectronics (r&d) Ltd
20110261604 - Memory cell and an associated memory device: A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage... Agent: Himax Technologies Limited
20110261605 - Graphene-based switching elements using a diamond-shaped nano-patch and interconnecting nano-ribbons: The use of diamond-shaped graphene nano-patches as novel non-volatile switching elements exhibiting transitions between high and low conductance states based on changes of magnetic ordering of these states. Non-magnetic reconstructed graphene nano-ribbons are used as non-invasive leads to implement the switching elements as carbon-nanoflake based memories and transistors. Switching of... Agent: The University Corporation, Inc. At California State University, Northridge
20110261606 - Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory... Agent:
20110261607 - Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory... Agent: Micron Technology, Inc.
20110261608 - Self-repairing memristor and method: A self-repairing memristor (300) and methods of operating a memristor (10), (310) and repairing a memristor (10), (310) employ thermal annealing (110). The thermal annealing (110) removes a short circuit in an oxide layer (12), (312) of the memristor (10), (310). Thermal annealing (110) includes heating the memristor (10), (310)... Agent:
20110261609 - Retain-till-accessed power saving mode in high-performance static memories: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example... Agent: Texas Instruments Incorporated
20110261610 - Nonvolatile memory device and method for controlling the same: A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and configured to adjust an amount... Agent: Hynix Semiconductor Inc.
20110261613 - Phase change memory array blocks with alternate selection: A phase change memory is disclosed. The phase change memory has a plurality of block units. The block units are alternately selected. The alternate block unit selection suppresses peak current ground bouncing on sub-wordline and connected ground line through sub-wordline driver transistor. An alternate bitline selection avoids adjacent cell heating... Agent: Mosaid Technologies Incorporated
20110261614 - Semiconductor device: A semiconductor device that needs a relatively long time to control a write operation and the like is reduced in size. The semiconductor device includes: first and second bit line control circuits which are arranged to correspond to first and second memory cell arrays, respectively; a control signal line that... Agent: Elpida Memory, Inc.
20110261615 - Semiconductor device, semiconductor system having the same, and method for operating the semiconductor device: A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to... Agent: Samsung Electronics Co., Ltd.
20110261611 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal, a first write control code generation unit configured to generate first write control codes which are cyclically updated... Agent: Hynix Semiconductor Inc.
20110261612 - Semiconductor memory apparatus and method for generating programming current pulse: A semiconductor apparatus includes a first write control code generation unit configured to generate first write control codes which have fixed value for a first time and are cyclically updated after the first time, a second write control code generation unit configured to generate a second write control code, and... Agent: Hynix Semiconductor Inc.
20110261616 - Write scheme in phase change memory: A method for writing a phase change memory includes receiving an input data corresponding to a plurality of memory cells, while reading a previous data from the plurality of memory cells and comparing the input data with the previous data. Upon determining that the input data is different from the... Agent: Mosaid Technologies Incorporated
20110261618 - Off-die charge pump that supplies multiple flash devices: A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive... Agent: Apple Inc.
20110261619 - Semiconductor memory device capable of lowering a write voltage: A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with... Agent:
20110261620 - Non-volatile static random access memory (nvsram) device: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter... Agent:
20110261621 - Programming and selectively erasing non-volatile storage: A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.... Agent:
20110261622 - Nonvolatile semiconductor memory device and memory system having the same: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein... Agent: Elpida Memory, Inc.
20110261624 - Data line management in a memory device: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such... Agent: Micron Technology, Inc.
20110261623 - Method of erasing semiconductor memory device: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory... Agent:
20110261617 - Semiconductor memory device having memory block configuration: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the... Agent: Renesas Electronics Corporation
20110261625 - Low noise sense amplifier array and method for nonvolatile memory: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then... Agent:
20110261626 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory block comprising cell strings each of which includes a plurality of memory cells, a current measurement circuit measure a current flowing through a selected bit line coupled to a selected cell string when a data read operation or a program verification operation is... Agent:
20110261628 - 256 meg dynamic random access memory: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are... Agent: Round Rock Research, LLC
20110261627 - Semiconductor nonvolatile memory device: In a semiconductor nonvolatile memory device, nonvolatile memory cells are plurally arranged in a memory array portion. An output circuit outputs setting information selected from plural sets of setting information to generate reference currents with different current values. A reference current circuit generates a reference current with a current value... Agent: Oki Semiconductor Co., Ltd.
20110261629 - Reduced power consumption in retain-till-accessed static memories: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias... Agent: Texas Instruments Incorporated
20110261630 - Semiconductor device: A semiconductor device compares potential AF_G at an end of an anti-fuse element with potential VPPR. If potential AF_G is equal to or higher than potential VPPR, then the semiconductor device boosts potential VPPSVT of a power supply line that is connected to the end of the anti-fuse element. If... Agent: Elpida Memory, Inc.
20110261631 - Semiconductor device and data processing system comprising semiconductor device: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components,... Agent: Elpida Memory, Inc.
20110261632 - Combined write assist and retain-till-accessed memory array bias: Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more... Agent: Texas Instruments Incorporated
20110261634 - Differential threshold voltage non-volatile memory and related methods: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.... Agent: Arizona Board Of Regents, For And On Behalf Of Arizona State University
20110261635 - Differential threshold voltage non-volatile memory and related methods: Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.... Agent: Arizona Board Of Regents, For And On Behalf Of Arizona State Unlversity
20110261633 - Memory with improved data reliability: An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory... Agent: Arm Limited
20110261636 - Common memory device for variable device width and scalable pre-fetch and page size: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example,... Agent:
20110261637 - Increased dram-array throughput using inactive bitlines: A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to... Agent: Oracle International Corporation
20110261638 - Method for storing data into a memory: A method for storing data into a memory is provided. In this method, at first, data desired to be written into the memory is provided, wherein the data comprises a plurality of data records. Then, a memory space of the memory for storing the data is provided. Thereafter, a data-writing... Agent: Htc Corporation
20110261639 - Semiconductor memory circuit: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of... Agent: Renesas Electronics Corporation
20110261640 - Semiconductor memory device and data processing system including the semiconductor memory device: A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving... Agent: Elpida Memory, Inc.10/20/2011 > 41 patent applications in 30 patent subcategories. categorized by USPTO classification
20110255322 - Encoding data for storage in a content addressable memory: An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the... Agent:
20110255323 - Memory/logic conjugate system: There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including... Agent:
20110255324 - Semiconductor integrated circuit device capable of securing gate performance and channel length: A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing... Agent: Hynix Semiconductor Inc.
20110255325 - Semiconductor device: An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor. The memory cell includes... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110255326 - Semiconductor device: The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110255327 - Method and system for split threshold voltage programmable bitcells: Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer... Agent:
20110255328 - Semiconductor memory device: The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and... Agent: Panasonic Corporation
20110255331 - Memory cells with rectifying device: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor.... Agent:
20110255330 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array configured by memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies to any one of the memory cells through... Agent: Kabushiki Kaisha Toshiba
20110255329 - Nonvolatile semiconductor memory device, method of supplying voltage in the same, and semiconductor device: A memory cell array is configured as an arrangement of memory cells. A first voltage generating circuit is configured to, during a write operation on the memory cells, generate and supply to the memory cell array a first voltage from a constant voltage, and to, during a read operation on... Agent: Kabushiki Kaisha Toshiba
20110255332 - Semiconductor memory device: A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to... Agent: Renesas Electronics Corporation
20110255333 - Phase change memory device with improved performance that minimizes cell degradation: A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data.... Agent: Hynix Semiconductor Inc.
20110255335 - Charge trap memory having limited charge diffusion: Subject matter disclosed herein relates to flash memory, and more particularly to a charge trap memory and a process flow to form same.... Agent:
20110255334 - Flash memory having multi-level architecture: Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.... Agent:
20110255336 - Semiconductor memory device: A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory... Agent: Kabushiki Kaisha Toshiba
20110255338 - Flash memory device and system including the same: The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to... Agent:
20110255339 - Method and system for accessing a flash memory device: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the... Agent: Mosaid Technologies Incorporated
20110255340 - Nonvolatile semiconductor memory and method for testing the same: A nonvolatile semiconductor memory, includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a code output circuit that outputs any... Agent: Renesas Electronics Corporation
20110255344 - Charge loss compensation during programming of a memory device: A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed.... Agent: Micron Technology, Inc.
20110255342 - Memory voltage cycle adjustment: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an... Agent: Micron Technology, Inc.
20110255343 - Programming in a memory device: Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of... Agent: Micron Technology, Inc.
20110255341 - Programming methods for a memory device: Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial programming is verified by applying a ramped voltage having a first voltage range (e.g., where the first voltage... Agent: Micron Technology, Inc.
20110255345 - Programming non-volatile storage includng reducing impact from other memory cells: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior... Agent:
20110255346 - Sub volt flash memory system: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other... Agent: Microchip Technology, Inc.
20110255347 - Semiconductor memory: A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a... Agent: Fujitsu Semiconductor Limited
20110255349 - Method of operating non-volatile memory cell: A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a... Agent: Macronix International Co., Ltd.
20110255348 - Non-volatile memory cell with btbt programming: m
20110255350 - Method of operating memory cell: A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the... Agent: Macronix International Co., Ltd.
20110255337 - Flash memory device and method of operation: A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a... Agent: Ocz Technology Group, Inc.
20110255351 - Level shifter with embedded logic and low minimum voltage: In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than... Agent:
20110255352 - Electronic circuit: An electronic circuit for which a coil 22 is disposed overlapping with a memory array region to carry out communications by inductive coupling between stacked and mounted chips by the coil 22. Because intersections 1 and 2 between the coil 22 and a bit line 15 are located at a... Agent: Keio University
20110255353 - Semiconductor integrated circuit: A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a... Agent: Panasonic Corporation
20110255354 - Semiconductor integrated circuit: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output... Agent: Renesas Electronics Corporation
20110255355 - Leakage and nbti reduction technique for memory: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that... Agent:
20110255356 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down... Agent:
20110255357 - Dynamic random access memory (dram) refresh: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more... Agent: Freescale Semiconductor, Inc.
20110255358 - Semiconductor device having floating body type transistor: A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the transistor, and the first signal changes between... Agent: Elpida Memory, Inc.
20110255359 - Sense-amplification with offset cancellation for static random access memories: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels... Agent:
20110255360 - Semiconductor memory device and method for controlling the same: A semiconductor memory device includes a memory cell array having plural memory cells that require a refresh operation when retaining data; a read/write control unit that performs read-access or write-access of memory cell address specified for the memory cell array based on instructions from the outside; a refresh control unit... Agent: Renesas Electronics Corporation
20110255361 - Multi-port memory having a variable number of used write ports: A multi-port memory is operated according to a method. Data is written, in a first mode, to a storage node of a memory cell from a first port through a first conductance. The first mode is characterized by a power supply voltage being applied at a power node at a... Agent:
20110255362 - Read command triggered synchronization circuitry: A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized... Agent: Round Rock Research, LLC10/13/2011 > 46 patent applications in 29 patent subcategories. categorized by USPTO classification
20110249480 - Nonvolatile memory device: Disclosed is a nonvolatile memory device including a memory cell array including main and redundant memory cells, content addressable memory cells configured to store a defective column address corresponding to a defective memory cell among the main cells, and a repair controller configured to compare the defective column address with... Agent:
20110249481 - Generating rom bit cell arrays: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells... Agent: Arm Limited
20110249482 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first active area in a semiconductor substrate, memory cells on the semiconductor substrate, first bit lines, first line, a second line, a third line, and a fourth line. The first line extends in a direction that intersects with the first... Agent:
20110249483 - Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line.... Agent: Samsung Electronics Co., Ltd.
20110249484 - Semiconductor memory device: An object is to provide a semiconductor memory device which stores data with the use of a transistor having small leakage current between a source and a drain in an off state as a writing transistor. In a matrix including a plurality of memory cells, gates of the writing transistors... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110249486 - Resistance variable memory apparatus: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a... Agent: Panasonic Corporation
20110249485 - Resistance-change memory: According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements... Agent: Kabushiki Kaisha Toshiba
20110249488 - Data cells with drivers and methods of making and operating the same: Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In... Agent: Micron Technology, Inc.
20110249487 - Semiconductor memory device and semiconductor device: A semiconductor memory device or a semiconductor device which has high reading accuracy is provided. A bit line, a word line, a memory cell placed in an intersection portion of the bit line and the word line, and a reading circuit electrically connected to the bit line are provided. The... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110249489 - Nanowire circuits in matched devices: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.... Agent: International Business Machines Corporation
20110249490 - Asymmetric write scheme for magnetic bit cell elements: Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a... Agent: Qualcomm Incorporated
20110249491 - Method and apparatus for programming a magnetic tunnel junction (mtj): A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ... Agent: Avalanche Technology, Inc.
20110249494 - Multiple select gates with non-volatile memory cells: Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series... Agent: Micron Technology, Inc.
20110249493 - Nand flash memory: In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory... Agent: Kabushiki Kaisha Toshiba
20110249495 - Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device: A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding... Agent:
20110249496 - Program method of multi-bit memory device and data storage system using the same: Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of... Agent:
20110249499 - Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively... Agent: Micron Technology, Inc.
20110249497 - Stacked package of semiconductor device: Provided is a nonvolatile memory device. The nonvolatile memory device includes a substrate including a first region and a second region, which are spaced from each other. A string line group is disposed on the substrate in the first region, and a bias interconnection group is disposed above the substrate... Agent:
20110249498 - Three-dimensionally stacked nonvolatile semicondutor memory: A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the... Agent:
20110249500 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device includes a unit cell with a transistor and a capacitor. The transistor is disposed on a substrate having a tunneling region and a channel region and includes a floating gate crossing both the tunneling region and the channel region. The capacitor is coupled to the floating... Agent:
20110249501 - Dynamic polarization for reducing stress induced leakage current: Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.... Agent:
20110249502 - Semiconductor device: The semiconductor device includes the read circuit which reads data written to a memory cell. The read circuit includes a first transistor, a second transistor, a first switch, and a second switch. A first terminal of the first transistor is electrically connected to a gate of the first transistor, and... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110249505 - Method of programming a semiconductor memory device: A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word... Agent:
20110249504 - Saw-shaped multi-pulse programming for program noise reduction in memory: In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which... Agent:
20110249503 - Select gate programming in a memory device: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts... Agent: Micron Technology, Inc.
20110249506 - Semiconductor storage device: A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an... Agent: Kabushiki Kaisha Toshiba
20110249507 - Sensing memory cells: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at... Agent: Micron Technology, Inc.
20110249492 - Semiconductor storage device and boosting circuit: A boosting circuit includes a clock control circuit which outputs a first reference clock signal by controlling the clock signal, and which outputs a second reference clock signal having a same period as that of the first reference clock signal, the second reference clock signal shifted in phase from the... Agent: Kabushiki Kaisha Toshiba
20110249508 - Nonvolatile semiconductor storage device: According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a... Agent:
20110249509 - Semiconductor memory device capable of executing high-speed page copy: According to one embodiment, a semiconductor memory device includes a memory cell array, first and second data caches, and a control circuit. The control circuit is configured to control, with use of the first and second data caches, a read operation of reading data from the selected memory cell of... Agent:
20110249510 - Embedded storage apparatus and test method thereof: An embedded storage apparatus including a control unit, a storage unit, and a signal processing and measurement unit is provided. The control unit outputs a plurality of signals, wherein the signals include a mode selection signal and a plurality of control signals. The storage unit is controlled by the control... Agent: Novatek Microelectronics Corp.
20110249511 - Semiconductor device: A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of... Agent:
20110249512 - Memory chip and multi-chip package: s
20110249513 - Transmitting/receiving methods and systems with simultaneous switching noise reducing preambles: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given... Agent:
20110249514 - Methods and apparatus for strobe signaling and edge detection thereof: A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions... Agent:
20110249515 - Dimm memory module reference voltage switching circuit: A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied... Agent: Agiga Tech Inc.
20110249516 - Internal voltage generation device: An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage... Agent: Hynix Semiconductor Inc.
20110249517 - Wordline driving circuit of semiconductor memory device: Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response... Agent:
20110249518 - Circuits, systems, and methods for dynamic voltage level shifting: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and... Agent: Qualcomm Incorporated
20110249519 - Data reproduction circuit: This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a... Agent: Fujitsu Limited
20110249520 - Data strobe signal output driver for a semiconductor memory apparatus: A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The predriver block is... Agent: Hynix Semiconductor Inc.
20110249521 - Semiconductor device: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling... Agent: Elpida Memory, Inc.
20110249522 - Method and circuit for calibrating data capture in a memory controller: A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that... Agent:
20110249523 - Semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected... Agent:
20110249524 - Programmable tracking circuit for tracking semiconductor memory read current: One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking... Agent: Qualcomm Incorporated
20110249525 - Circuits, systems and methods for adjusting clock signals based on measured performance characteristics: Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to... Agent: Qualcomm Incorporated10/06/2011 > 61 patent applications in 29 patent subcategories. categorized by USPTO classification
20110242872 - Semiconductor device: A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT0, MT1 are provided respectively at points of intersection of global bit line GBL0 and global word lines GWL00B, GWL01B. Word lines WL000 of MT0, MT1 are commonly connected to an output from a word-line... Agent: Hitachi, Ltd.
20110242870 - Stacked memory and devices including the same: In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory... Agent: Samsung Electronics Co., Ltd.
20110242869 - Three-dimensional stacked semiconductor integrated circuit and control method thereof: A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a... Agent: Hynix Semiconductor Inc.
20110242871 - Vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers: A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element.... Agent: Unity Semiconductor Corporation
20110242873 - Photo-responsive memory resistor and method of operation: An optically-controlled memory resistor, comprising (1) a memory resistor comprising a first electrode, a second electrode, and a photo-responsive active layer disposed between the first and second electrodes, and (2) a light source in cooperation with the memory resistor, the light source configured to controllably illuminate the memory resistor for... Agent:
20110242876 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation
20110242877 - Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is... Agent:
20110242878 - Methods for operating memory elements: Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of... Agent: Micron Technology, Ins.
20110242875 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory... Agent: Kabushiki Kaisha Toshiba
20110242874 - Resistive memory and method for controlling operations of the same: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer... Agent: Macronix International Co., Ltd.
20110242880 - Memory elements with soft error upset immunity: Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and... Agent:
20110242882 - Semiconductor memory device including sram cell: A semiconductor memory device includes: a first word line and a second word line; a plurality of first SRAM cells; a plurality of second SRAM cells; and a mediating cell. Each first SRAM cell includes the first word line and the second word line and is connected to the first... Agent: Renesas Electronics Corporation
20110242881 - Sram device: An object of the present invention is to provide an SRAM device which can set a threshold voltage of a selection transistor appropriate for all the cells on an SRAM array. The SRAM device uses a field effect transistor as the selection transistor, the field effect transistor comprising a gate... Agent: National Institute Of Advanced Industrial Science And Technology
20110242879 - Two word line sram cell with strong-side word line boost for write provided by weak-side word line: An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected... Agent: Texas Instruments Incorporated
20110242883 - Thermally assisted multi-bit mram: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.... Agent: Seagate Technology LLC
20110242886 - Apparatus and systems using phase change memories: Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver... Agent:
20110242887 - Programmable resistance memory with feedback control: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory... Agent:
20110242884 - Programming at least one multi-level phase change memory cell: A method of applying at least one programming pulse to the a PCM cell for programming the PCM cell to have a respective definite cell state, the definite cell state being defined by a definite resistance level using an annealing pulse or a melting pulse. The respective definite cell state... Agent: International Business Machines Corporation
20110242885 - Three-dimensional phase change memory: A memory device includes a stack of semiconductor layers. A circuit is on a layer of the stack of semiconductor layers. A primary memory array is on another layer of the stack of semiconductor layers different from the layer comprising the circuit. A plurality of electrical communication paths are between... Agent: Mosaid Technologies Incorporated
20110242888 - Semiconductor device and manufacturing method thereof: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over... Agent: Renesas Electronics Corporation
20110242889 - Programming non-volatile memory with high resolution variable initial programming pulse: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a... Agent:
20110242890 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the... Agent:
20110242891 - Operation methods for memory cell and array for reducing punch through leakage: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain... Agent: Macronix International Co., Ltd.
20110242892 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate... Agent: Kabushiki Kaisha Toshiba
20110242895 - Memory device, manufacturing method for memory device and method for data writing: A memory device to which an electron beam is irradiated to store data therein is provided. The memory device includes a plurality of floating electrodes that store data through irradiation of the electron beam thereto, a charge amount detecting section that detects data stored in each of the floating electrodes... Agent: Advantest Corporation
20110242894 - Method and system to isolate memory modules in a solid state drive: A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that... Agent:
20110242893 - Non-volatile memory unit cell with improved sensing margin and reliability: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating... Agent: Ememory Technology Inc.
20110242897 - Program and read trim setting: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.... Agent:
20110242896 - Semiconductor integrated circuit device: A semiconductor device includes a booster circuit and a detector. The booster circuit is configured to boost an input voltage and output an output voltage, and the detector is configured to output the output voltage, which is output from the booster circuit, and control the booster circuit to generate a... Agent: Fujitsu Semiconductor Limited
20110242898 - 4-transistor non-volatile memory cell with pmos-nmos-pmos-nmos structure: A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and... Agent:
20110242899 - Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage: An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage... Agent:
20110242901 - Lifetime markers for memory devices: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read... Agent: Micron Technology, Inc.
20110242900 - Memory cell sensing devices and methods: The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An... Agent: Micron Technology, Inc.
20110242902 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array including a plurality of memory cells; a plurality of word lines each connected in common to memory cells arranged in a corresponding one of rows among the plurality of memory cells; a voltage generator including a clock signal cycle controller... Agent: Kabushiki Kaisha Toshiba
20110242903 - Semiconductor memory device capable of shortenin erase time: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation,... Agent:
20110242904 - Read only memory and operating method thereof: A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second... Agent: Taiwan Semiconductor Manufacturing Co, Ltd.
20110242905 - Semiconductor module including module control circuit and method for controlling the same: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal... Agent: Hynix Semiconductor Inc.
20110242906 - Dual function compatible non-volatile memory device: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output... Agent: Mosaid Technologies Incorporated
20110242908 - Command decoder and a semiconductor memory device including the same: A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that generates an internal snoop read command by... Agent: Hynix Semiconductor Inc.
20110242910 - Data strobe clock buffer in semiconductor memory apparatus, method of controlling the same, and semiconductor apparatus having the same: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal... Agent: Hynix Semiconductor, Inc.
20110242909 - Semiconductor device and system: A system includes a data transmitting device and a data receiving device. The data transmitting device includes a data strobe signal generation unit configured to generate first and second data strobe signals in response to an output enable signal, and a data output unit configured to transmit data in synchronization... Agent: Hynix Semiconductor Inc.
20110242907 - Semiconductor memory apparatus and read/write control method thereof: A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; and a plurality of ranks configured to perform a write... Agent: Hynix Semiconductor Inc.
20110242914 - Clock delay adjustment circuit for semiconductor integrated circuit and control method of the same: A clock signal adjustment circuit in a semiconductor integrated circuit includes: multiple circuit blocks; multiple clock delay circuits supplying delayed clock signals of the input clock signals under the control of the delay control signals to the corresponding circuit blocks; a control circuit conducting a delay test of the circuit... Agent: Renesas Electronics Corporation
20110242911 - Column command buffer and latency circuit including the same: A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate... Agent: Hynix Semiconductor Inc.
20110242915 - Method and apparatus for reducing oscillation in synchronous circuits: Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase... Agent: Micron Technology, Inc.
20110242912 - Random access memory devices having word line drivers therein that support variable-frequency clock signals: Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a... Agent:
20110242913 - Self refresh circuit: A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse... Agent: Hynix Semiconductor Inc.
20110242916 - On-die termination circuit, data output buffer and semiconductor memory device: An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in... Agent: Samsung Electronics Co., Ltd.
20110242917 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according... Agent:
20110242918 - Global line sharing circuit of semiconductor memory device: A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit... Agent:
20110242919 - Precharge voltage supplying circuit: A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied, and a resistance element connected in parallel to... Agent: Hynix Semiconductor Inc.
20110242920 - Voltage sensing circuit capable of controlling a pump voltage stably generated in a low voltage environment: Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of... Agent:
20110242921 - Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween,... Agent:
20110242922 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and... Agent: Hynix Semiconductor Inc.
20110242923 - Semiconductor memory device including clock control circuit and method for operating the same: A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being... Agent:
20110242925 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values... Agent: Micron Technology, Inc.
20110242924 - Semiconductor memory device and method of controlling the same: A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic... Agent: Samsung Electronics Co., Ltd.
20110242927 - Encoded read-only memory (rom) decoder: Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing... Agent: Broadcom Corporation
20110242926 - Pseudo-inverter circuit on seo1: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region... Agent:
20110242928 - Address delay circuit of semiconductor memory apparatus: An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses... Agent: Hynix Semiconductor Inc.
20110242929 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse... Agent: Hynix Semiconductor Inc.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.21579 seconds