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Static information storage and retrieval September class, title,number 09/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
09/29/2011 > 75 patent applications in 38 patent subcategories. class, title,number

20110235385 - Semiconductor memory apparatus with power-meshed structure: A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular... Agent: Hynix Semiconductor Inc.

20110235386 - Semiconductor memory device and manufacturing method of the same: The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate... Agent: Renesas Electronics Corporation

20110235387 - Semiconductor memory device: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory... Agent: Renesas Electronics Corporation

20110235388 - Nonvolatile semiconductor storage device: According to an embodiment of the invention, a nonvolatile semiconductor storage device includes a first memory cell and a second memory cell. A first fuse element in which data can be electrically written only once is provided in the first memory cell. A second fuse element in which data can... Agent: Kabushiki Kaisha Toshiba

20110235389 - Semiconductor device: An object is reduction in power consumption of a semiconductor device including a memory circuit. In the semiconductor device including a memory circuit, the memory circuit includes a memory cell including a semiconductor element and a memory cell that does not include a semiconductor element in a region defined by... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110235390 - High density memory device: A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal... Agent: International Business Machines Corporation

20110235403 - Method and apparatus managing worn cells in resistive memories: A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive... Agent: Samsung Electronics Co., Ltd.

20110235397 - Non-volatile semiconductor memory device: A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first... Agent: Kabushiki Kaisha Toshiba

20110235399 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array configured by plural memory cells each including a variable resistor and each provided between first and second lines. A control circuit applies to a memory cell through the first and second lines a writing voltage for... Agent: Kabushiki Kaisha Toshiba

20110235401 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage... Agent: Kabushiki Kaisha Toshiba

20110235392 - Nonvolatile semiconductor storage device: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit... Agent: Kabushiki Kaisha Toshiba

20110235393 - Nonvolatile storage device: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a... Agent: Sony Corporation

20110235405 - Programming non-volatile storage element using current from other element: A non-volatile storage apparatus includes a set of Y lines, a common X line, multiple storage elements each of which is connected to the common X line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable... Agent:

20110235404 - Pulse reset for non-volatile storage: A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse... Agent:

20110235391 - Reference cell write operations at a memory: A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at... Agent: Qualcomm Incorporated

20110235394 - Semiconductor memory device: A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an... Agent: Kabushiki Kaisha Toshiba

20110235402 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing... Agent: Kabushiki Kaisha Toshiba

20110235400 - Semiconductor memory device and method for controlling the same: According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing... Agent:

20110235398 - Semiconductor memory device and operation method thereof: A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at an intersection of first lines and second lines; and a control circuit configured to execute a read operation, thereby determining a resistance state of the selected one of the memory cells.... Agent: Kabushiki Kaisha Toshiba

20110235396 - Semiconductor memory device and semiconductor device: A semiconductor memory device includes a memory cell array, a first control circuit, and a second control circuit. The first control circuit is configured to apply a first voltage to a selected first line. The second control circuit is configured to apply a second voltage having a voltage value higher... Agent: Kabushiki Kaisha Toshiba

20110235395 - Semiconductor memory device and writing method thereof: A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured... Agent: Kabushiki Kaisha Toshiba

20110235406 - Low-power 5t sram with improved stability and reduced bitcell size: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically... Agent: Industry-academic Cooperation Foundation, Yonsei University

20110235407 - Semiconductor memory device and a method of manufacturing the same: A semiconductor memory device including a substrate, wherein the substrate includes first, second and third well regions, the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second... Agent:

20110235408 - Semiconductor memory device: For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the... Agent: Hitachi, Ltd.

20110235409 - Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells... Agent:

20110235412 - Controlling ac disturbance while programming: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate... Agent: Spansion LLC

20110235410 - Device and method to read data subject to a disturb condition: A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and... Agent: Sandisk Il Ltd.

20110235413 - Nonvolatile semiconductor memory device and method of controlling nonvolatile semiconductor memory device: A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially... Agent: Kabushiki Kaisha Toshiba

20110235414 - Semiconductor memory device: According to one embodiment, a semiconductor memory device comprises a memory cell array, a controller. A memory cell array comprises bit lines, and memory cells configured to store different states, i.e., m values or n values. When storing the n values in a memory cell, the controller performs a first... Agent:

20110235415 - Read method for nonvolatile memory device, and data storage system using the same: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method... Agent:

20110235417 - Nand flash memory: A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units... Agent: Kabushiki Kaisha Toshiba

20110235416 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device for raising operating speed is provided. The nonvolatile semiconductor memory device includes plural bit lines extending in a first direction, and a memory cell that includes plural blocks each having plural NAND strings each of which includes a group of memory cells connected in series... Agent: Kabushiki Kaisha Toshiba

20110235418 - Determining memory page status: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.... Agent: Micron Technology, Inc.

20110235419 - Non-volatile semiconductor storage device: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected... Agent: Renesas Electronics Corporation

20110235422 - Apparatus having a string of memory cells: Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target... Agent: Micron Technology, Inc.

20110235424 - Hierarchical common source line structure in nand flash memory: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line... Agent: Mosaid Technologies Incorporated

20110235421 - Nonvolatile semiconductor memory device: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a... Agent: Kabushiki Kaisha Toshiba

20110235420 - Simultaneous multi-state read or verify in non-volatile storage: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a... Agent:

20110235423 - Verification process for non-volatile storage: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.... Agent:

20110235426 - Flash memory system having a plurality of serially connected devices: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits... Agent: Mosaid Technologies Incorporated

20110235425 - Method of directly reading output voltage to determine data stored in a non-volatile memory cell: An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.... Agent:

20110235427 - Channel hot electron injection programming method and related device: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple... Agent:

20110235428 - Compensation of non-volatile memory chip non-idealities by program pulse adjustment: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse... Agent:

20110235429 - Method and apparatus for programming flash memory: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.... Agent:

20110235411 - Fast programming memory device: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line,... Agent:

20110235430 - Memory device and method: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to... Agent: Spansion LLC.

20110235432 - Method of erasing in non-volatile memory device: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are... Agent:

20110235431 - Nonvolatile semiconductor memory and method of operating the same: According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier... Agent:

20110235433 - Verifying an erase threshold in a memory device: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well... Agent: Micron Technology, Inc.

20110235435 - Non-volatile memory and method for power-saving multi-pass sensing: A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles... Agent:

20110235434 - Systems and methods for refreshing non-volatile memory: Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved... Agent: Apple Inc.

20110235436 - Semiconductor memory device: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be... Agent: Kabushiki Kaisha Toshiba

20110235437 - Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using pip or mim coupling capacitor for cell size reduction and simultaneous vpp and vnn for write voltage reduction: A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a... Agent:

20110235443 - Voltage stabilization circuit and semiconductor memory apparatus using the same: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in... Agent: Hynix Semiconductor Inc.

20110235438 - Temporal alignment of data unit groups in a switch: Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit... Agent: Infinera Corporation

20110235439 - Static memory cell having independent data holding voltage: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage... Agent: Renesas Electronics Corporation

20110235440 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain... Agent: Renesas Electronics Corporation

20110235441 - High voltage generating circuit and semiconductor memory device having the same and method thereof: A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to... Agent:

20110235442 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent:

20110235444 - Sram writing system and related apparatus: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing... Agent: Faraday Technology Corporation

20110235445 - Method and system to lower the minimum operating voltage of register files: A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS... Agent:

20110235446 - Write strobe generation for a memory interface controller: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data... Agent: Juniper Networks, Inc.

20110235447 - Low power memory array column redundancy mechanism: A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value... Agent:

20110235448 - Using differential signals to read data on a single-end port: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110235450 - Current mode sense amplifier with passive load: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop... Agent: Micron Technology, Inc.

20110235449 - Dual sensing current latched sense amplifier: A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a... Agent: Qualcomm Incorporated

20110235451 - Dynamic random access memory and method of driving dynamic random access memory: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage... Agent: Elite Semiconductor Memory Technology Inc.

20110235453 - Fuse circuit and repair control circuit using the same: A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between... Agent:

20110235452 - Semiconductor memory device and method for operating the same: A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.... Agent:

20110235454 - High-voltage selecting circuit which can generate an output voltage without a voltage drop: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when... Agent:

20110235456 - Power supply control circuit and semiconductor apparatus including the same: A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of... Agent: Hynix Semiconductor Inc.

20110235457 - Semicondcutor integrated circuit device: According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having... Agent: Kabushiki Kaisha Toshiba

20110235455 - Voltage regulators, amplifiers, memory devices and methods: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The... Agent: Micron Technology, Inc.

20110235458 - Electric device: In one embodiment, an electric device includes a memory, first and second generators, a limit unit, and a reduction unit. The first generator generates the chip select signal representing an inactive mode or an active mode according to a potential of an enable terminal and a input potential The second... Agent: Toshiba Tec Kabushiki Kaisha

20110235459 - Clock-forwarding low-power signaling system: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal,... Agent: Rambus Inc.

  
09/22/2011 > 48 patent applications in 27 patent subcategories. class, title,number

20110228580 - Methods and apparatus for sum of address compare write recode and compare reduction: Techniques are described for sum address compare (A+B=K) operation for use in translation lookaside buffers and content addressable memory devices, for example. Address input signals A and B are supplied as input to the A+B=K operation and K is a previous value stored in a plurality of memory cells. In... Agent: Qualcomm Incorporated

20110228582 - Stacked memory device and method of fabricating same: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory... Agent: Samsung Electronics Co., Ltd.

20110228581 - Stacked memory device and method of repairing same: A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.... Agent: Samsung Electronics Co., Ltd.

20110228583 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a... Agent: Kabushiki Kaisha Toshiba

20110228584 - Semiconductor memory device: In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110228593 - Memristive device based on current modulation by trapped charges: A memristive device (200) includes a first electrode (104); a second electrode (102); a junction (106) between the first electrode (104) and the second electrode (102), the junction (106) including a semiconductor matrix (230) and particles (240) embedded in the semiconductor matrix (230), the particles (240) being configured to hold... Agent:

20110228588 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device includes a memory cell array having multiple memory cells, a data input/output buffer for temporarily storing data to be stored in the memory cells, and a data scanner for scanning the data stored temporarily in the data input/output buffer. The nonvolatile memory device further includes control... Agent: Samsung Electronics Co., Ltd.

20110228587 - Nonvolatile semiconductor memory and manufacturing method of nonvolatile semiconductor memory: According to one embodiment, a nonvolatile semiconductor memory includes word lines, bit lines, memory cells, a dummy word line, a dummy bit line and dummy cells. The word lines and the bit lines cross. The memory cells are provided for each intersection of the word lines and bit lines. Each... Agent:

20110228586 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials... Agent:

20110228592 - Programmable bipolar electronic device: A configurable memristive device (300) for regulating an electrical signal includes a memristive matrix (350) containing a first dopant species; emitter (320), collector (310), and a base electrodes (330, 340) which are in contact with the memristive matrix (350); and a mobile dopant species contained within a central region (360)... Agent:

20110228589 - Resistance change memory: A memory includes memory cells each includes a resistance change element and a diode. The diode comprises areas which is provided in order of a first semiconductor area with a first conductivity type, a second semiconductor area with the first conductivity type, and a third semiconductor area with a second... Agent:

20110228590 - Resistance change memory: A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of... Agent:

20110228591 - Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating... Agent:

20110228585 - Variable resistance memory device and related method of operation: A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a... Agent: Samsung Electronics Co., Ltd.

20110228595 - Memory cell that includes multiple non-volatile memories: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including... Agent: Qualcomm Incorporated

20110228594 - Multi-port non-volatile memory that includes a resistive memory element: A system and method to access a multi-port non-volatile memory that includes a resistive memory element is disclosed. In a particular embodiment, a multi-port non-volatile memory device is disclosed that includes a resistive memory cell and multiple ports coupled to the resistive memory cell.... Agent: Qualcomm Incorporated

20110228596 - Spin memory and spin transistor: Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse... Agent: Kabushiki Kaisha Toshiba

20110228597 - Static magnetic field assisted resistive sense element: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to... Agent: Seagate Technology LLC

20110228598 - Transmission gate-based spin-transfer torque memory unit: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line... Agent: Seagate Technology LLC

20110228600 - Memory programming: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits... Agent: International Business Machines Corporation

20110228599 - Non-volatile memory cell with programmable unipolar switching element: A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed... Agent: Seagate Technology LLC

20110228601 - Mlc self-raid flash data protection scheme: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the... Agent:

20110228603 - Fusion memory: According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a... Agent:

20110228602 - Memory device and semiconductor device: One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110228605 - Nonvolatile memory: A nonvolatile memory includes a memory cell array comprising an object block which includes a first data bit region capable of storing input data and a first flag bit region capable of storing first flag information, a redundant block which includes a second data bit region capable of storing input... Agent: Kabushiki Kaisha Toshiba

20110228604 - Preloading data into a flash storage device: Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous... Agent: Sandisk Il Ltd.

20110228607 - Adjusting program and erase voltages in a memory device: A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level... Agent: Micron Technolgy, Inc.

20110228606 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device comprises a first block, a second block, a storage circuit, a controller. A first block comprises a first select gate and a first word line. A second block comprises a second select gate and a second word line. A storage circuit... Agent:

20110228608 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first... Agent:

20110228609 - Correcting for over programming non-volatile storage: A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line).... Agent:

20110228610 - Non-volatile semiconductor memory device and a programming method thereof: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by... Agent: Kabushiki Kaisha Toshiba

20110228611 - System and method for bit-line control: In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit... Agent:

20110228613 - Device and method for achieving sram output characteristics from drams: A method is provided for achieving SRAM output characteristics from DRAMs, in which a plurality of DRAMs are arranged connected in parallel to a controller in such a way as to be able to obtain SRAM output characteristics using the DRAMs, comprising a process in which data is output to... Agent:

20110228614 - Memory system topologies including a buffer device and an integrated circuit memory device: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices... Agent: Rambus Inc.

20110228612 - Semiconductor memory and semiconductor memory test method: According to the embodiments, a read circuit is connected to the other end of the bit line for reading out data from read data storing memory cells and test data storing memory cells via the bit line, and a read control circuit makes data to be read out from the... Agent: Kabushiki Kaisha Toshiba

20110228615 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes unit structures. Each unit structure includes bit lines, memory cells, sense amplifiers, a first data line, a computing circuit, a second data line, and data latches. The bit lines are connected to memory cells. The sense amplifiers are connected to respective... Agent:

20110228616 - Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency: A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores... Agent: Rambus, Inc.

20110228617 - Techniques for reducing a voltage swing: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one... Agent: Micron Technology, Inc.

20110228618 - System with controller and memory: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... Agent: Elpida Memory, Inc.

20110228619 - Memory control apparatus and mask timing adjusting method: A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of... Agent:

20110228621 - Semiconductor device and method for testing the same: A semiconductor device and a method for testing the same are disclosed, relating to a technology for simultaneously screening an off-leakage-current fail caused by a passing gate effect and a neighbor gate effect. The semiconductor device includes a memory cell configured to read and write data; a sense amplifier configured... Agent: Hynix Semiconductor Inc.

20110228620 - Testing method for semiconductor memory device: A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory... Agent: Elite Semiconductor Memory Technology Inc.

20110228623 - Power-up circuit: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to... Agent: Elite Semiconductor Memory Technology Inc.

20110228622 - Voltage regulator bypass in memory device: A memory chip comprises an internal voltage regulator that is selectively enabled/disabled to regulate an external voltage used by the memory chip subunit.... Agent: International Business Machines Corporation

20110228624 - Sub-word-line driving circuit, semiconductor memory device having the same, and method of controlling the same: Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected... Agent:

20110228625 - Write command and write data timing circuit and methods for timing the same: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases... Agent:

20110228626 - Synchronization circuit and method with transparent latches: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the... Agent:

20110228627 - Double data rate memory device having data selection circuit and data paths: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd... Agent: Elite Semiconductor Memory Technology Inc.

  
09/15/2011 > 35 patent applications in 21 patent subcategories. class, title,number

20110222328 - Distributed semiconductor device methods, apparatus, and systems: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice,... Agent:

20110222329 - Semiconductor device having its standby current reduced: A semiconductor device includes a plurality of drain lines each being commonly connected to first nodes of a plurality of memory cells, a plurality of bit lines respectively connected to second nodes of the memory cells, a source line, a transistor that connects the drain lines to the source line,... Agent: Elpida Memory, Inc.

20110222330 - Nonvolatile memory device comprising one-time-programmable lock bit register: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell.... Agent: Samsung Electronics Co., Ltd.

20110222331 - Semiconductor memory device: A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at respective intersections of first lines and second lines; and a control circuit configured to apply a first pulse voltage multiple times to selected one of the first lines and selected one... Agent: Kabushiki Kaisha Toshiba

20110222332 - Fully balanced dual-port memory cell: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2)... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110222333 - Magnetic memory cell and magnetic random access memory: Provided is a highly-integrated magnetic memory which employs applied spin torque magnetization reversal and does not require the switching of the current direction at the time of rewrite. The magnetic memory includes a memory cell in which a fixed layer made of a ferromagnetic material, a nonmagnetic layer, a recording... Agent:

20110222335 - Magnetoresistive element and magnetoresistive random access memory including the same: The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between... Agent: Kabushiki Kaisha Toshiba

20110222334 - Spin transfer torque mram, and write method and read method therefor: A method of writing data into a memory cell of spin transfer torque magnetoresistive random access memory includes writing a first data into a first memory cell that includes a first magnetic-tunnel-junction element and a first selection transistor wherein an end of the first memory cell is connected to a... Agent: Fujitsu Limited

20110222336 - Semiconductor device: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110222337 - Floating-body/gate dram cell: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field... Agent: University Of Florida Research Foundation, Inc.

20110222342 - Data storage system having multi-bit memory device and operating method thereof: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external... Agent: Samsung Electronics Co., Ltd.

20110222344 - Method for modifying data more than once in a multi-level cell memory location within a memory array: A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the... Agent:

20110222341 - Multi-level cell programming speed improvement through program level exchange: A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time.... Agent: Macronix International Co., L

20110222345 - Non-volatile memory and method with power-saving read and program-verify operations: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation... Agent:

20110222343 - Semiconductor memory device: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit... Agent: Kabushiki Kaisha Toshiba

20110222346 - Nand-type flash memory: A NAND-type flash memory has a bit line; a source line; and a NAND string that is configured by connecting a plurality of memory cells, into which data can be electrically rewritable, in series. The NAND-type flash memory has a drain-side selection gate transistor that has a gate to which... Agent: Kabushiki Kaisha Toshiba

20110222352 - Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect: A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data.... Agent: Micron Technology, Inc.

20110222350 - Multi-level cell access buffer with dual function: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory... Agent: Mosaid Technologies Incorporated

20110222347 - Nand nonvolatile semiconductor memory device and write method for nand nonvolatile semiconductor memory device: According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control... Agent:

20110222348 - Nonvolatile memory devices having memory cell arrays with unequal-sized memory cells and methods of operating same: Nonvolatile memory devices include a two-dimensional array of nonvolatile memory cells having a plurality of memory cells of unequal size therein. These memory cells may include those that have unequal channel widths associated with respective word lines and those having unequal channel lengths associated with respective bit lines that are... Agent:

20110222351 - Semiconductor memory device: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit... Agent: Fujitsu Semiconductor Limited

20110222349 - Transfer circuit, nonvolatile semiconductor device using the same, and transfer method of the same: According to one embodiment, a transfer circuit includes a first inverter, a second inverter, a first line, a second line, a first holder, and a second holder. The first inverter inverts data at a first node and transfers the inverted data to a second node. The second inverter inverts the... Agent:

20110222353 - Sensing operations in a memory device: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells... Agent: Micron Technology, Inc.

20110222340 - Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than... Agent:

20110222338 - Method of handling reference cells in nvm arrays: A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage... Agent:

20110222339 - Nonvolatile memory device for reducing interference between word lines and operation method thereof: Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line... Agent:

20110222354 - Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of... Agent: Micron Technology, Inc.

20110222356 - Techniques for providing a semiconductor memory device: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and... Agent: Innovative Silicon Isi Sa

20110222355 - Control voltage generation circuit and nonvolatile storage device having the same: Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit... Agent: Sony Corporation

20110222358 - Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the... Agent: Rambus Inc.

20110222357 - Process and temperature tolerant non-volatile memory: A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory... Agent: Agerre Systems, Inc.

20110222359 - Apparatus and method for transmitting/receiving signals at high speed: A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data... Agent:

20110222360 - Semiconductor storage device and its cell activation method: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control... Agent: Renesas Electronics Corporation

20110222361 - Nano-sense amplifier: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense... Agent:

20110222362 - Semiconductor memory device: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a... Agent: Elpida Memory, Inc.

  
09/08/2011 > 53 patent applications in 37 patent subcategories. class, title,number

20110216569 - Content addressable memory device: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage... Agent: Renesas Electronic Corporation

20110216570 - Rank select using a global select pin: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in... Agent: Micron Technology, Inc.

20110216571 - Semiconductor memory device and semiconductor device: A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110216572 - Electrically programmable fuse bit: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories,... Agent: Kilopass Technology, Inc.

20110216576 - Information recording/reproducing device: According to one embodiment, an information recording/reproducing device includes a recording layer and a driver section. The recording layer has a first layer including a first compound. The first compound includes a mixed crystal of a first oxide containing a first metallic element and a second oxide. The second oxide... Agent: Kabushiki Kaisha Toshiba

20110216575 - Nonvolatile memory device and nonvolatile memory apparatus: According to one embodiment, a nonvolatile memory device includes a recording layer and a conductive first layer. The recording layer includes a main group element, a transition element, and oxygen. The recording layer is capable of recording information by changing reversibly between a high resistance state and a low resistance... Agent: Kabushiki Kaisha Toshiba

20110216574 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the... Agent: Kabushiki Kaisha Toshiba

20110216573 - Semiconductor integrated circuit: According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has... Agent: Kabushiki Kaisha Toshiba

20110216577 - Variable resistance nonvolatile storage device: The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable... Agent: Panasonic Corporation

20110216579 - Semiconductor device: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.... Agent: Renesas Electronics Corporation

20110216578 - System for retaining state data: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains... Agent: Broadcom Corporation

20110216580 - Mram-based memory device with rotated gate: A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of... Agent: Crocus Technology Sa

20110216581 - Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling: A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be... Agent: Micron Technology, Inc.

20110216582 - Information recording and reproducing device: According to one embodiment, an information recording and reproducing device includes a recording layer and a driving unit. The recording layer includes a first layer containing a first compound. The first compound includes a first positive ion element. The first positive ion element is made of a transition metal element... Agent: Kabushiki Kaisha Toshiba

20110216583 - Semiconductor device: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which... Agent: Hitachi, Ltd.

20110216584 - Electromechanical switch, storage device comprising such an electromechanical switch and method for operating the same: An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch... Agent: Thomson Licensing

20110216585 - Metal containing materials: Metal containing materials and methods of forming the same are disclosed. One such method includes substantially concurrently feeding a flow of precursor gas containing a metal of a metal containing material and a flow of source gas containing a reducing agent so that the precursor gas and the source gas... Agent: Micron Technology, Inc.

20110216586 - Methods and apparatus for intercell interference mitigation using modulation coding: Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value... Agent:

20110216589 - Flash memory device, memory system and method of operating the same: A memory system includes a memory device and a data converting device. The memory device includes a memory cell array which includes a plurality of memory cells. The data converting device includes an encoding device. The encoding device converts input data into converted data by changing a bandwidth corresponding to... Agent:

20110216588 - Multi-bit cell memory devices using error correction coding and methods of operating the same: A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones... Agent: Samsung Electronics Co., Ltd.

20110216590 - Nonvolatile memory device using interleaving technology and programmming method thereof: A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2N threshold voltage states to N-bit data where N is 2 or a natural number greater than 2, a second controller configured to set a difference between adjacent... Agent:

20110216587 - Nonvolatile memory device, methods of programing the nonvolatile memory device and memory system including the nonvolatile memory device: Embodiments of the inventive concept provide a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a read/write circuit, and a backup circuit. The memory cell array includes a first memory block including a first word line having first memory cells and a second word line having... Agent:

20110216591 - Programming rate identification and control in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement... Agent: Micron Technology, Inc.

20110216593 - Nand flash memory: A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block... Agent:

20110216592 - Nonvolatile semiconductor memory device and memory system: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block,... Agent:

20110216594 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Kabushiki Kaisha Toshiba

20110216595 - Nand flash memory of using common p-well and method of operating the same: A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a... Agent:

20110216598 - Memory system and operating method thereof: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time... Agent: Samsung Electronics Co., Ltd

20110216597 - Nonvolatile semiconductor memory device: A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality... Agent: Kabushiki Kaisha Toshiba

20110216596 - Reliability protection for non-volatile memories: A non-volatile memory cell having enhanced protection against mobile ions. The electric field within the memory cell is controlled in a manner that minimizes migration of mobile ions toward the floating gate. Each conductive layer in the memory cell is biased to reduce the flow of mobile ions toward the... Agent: Mosys, Inc.

20110216599 - Semiconductor memory device and control method thereof: According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a... Agent:

20110216600 - Drain select gate voltage management: Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different... Agent:

20110216601 - Current sink system based on sample and hold for source side sensing: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a... Agent: Macronix International Co., Ltd.

20110216602 - Flash memory devices with selective bit line discharge paths and methods of operating the same: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line,... Agent: Samsung Electronics Co., Ltd.

20110216603 - Non-volatile memory device, erasing method thereof, and memory system including the same: Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage... Agent: Samsung Electronics Co., Ltd.

20110216604 - Method for operating semiconductor memory device: According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first... Agent: Kabushiki Kaisha Toshiba

20110216605 - Techniques for providing a semiconductor memory device having hierarchical bit lines: Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The... Agent: Innovative Silicon Isi Sa

20110216606 - Data output circuit of semiconductor memory device: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the... Agent:

20110216607 - Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.... Agent: Macronix International Co., L

20110216608 - Techniques for reading from and/or writing to a semiconductor memory device: Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second... Agent: Innovative Silicon Isi Sa

20110216609 - Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory... Agent: Micron Technology, Inc.

20110216610 - Semiconductor device and data processor: Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static... Agent: Renesas Electronics Corporation

20110216611 - Method and apparatus for calibrating write timing in a memory system: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a... Agent: Rambus Inc.

20110216612 - Device: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a... Agent: Elpida Memory, Inc.

20110216613 - Low power termination for memory modules: An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module... Agent: Intel Corporation

20110216614 - Semiconductor device enabling refreshing of redundant memory cell instead of defective memory cell: A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal... Agent: Elpida Memory, Inc.

20110216615 - Semiconductor memory device highly integrated in direction of columns: First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets.... Agent: Renesas Electronics Corporation

20110216616 - Semiconductor memory device: A semiconductor memory device includes a first and second memory cell array region, a first and second sense amplifier region interposed between the first and second memory cell array regions, a first column selection region interposed between the first sense amplifier region and the first memory cell array region and... Agent:

20110216617 - Techniques for sensing a semiconductor memory device: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the... Agent: Innovative Silicon Isi Sa

20110216618 - Voltage compensated tracking circuit in sram: Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further,... Agent: Texas Instruments Incorporated

20110216619 - Memory power management systems and methods: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an... Agent:

20110216620 - Decoder circuit: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input... Agent: Renesas Electronics Corporation

20110216621 - Synchronous command-based write recovery time auto precharge control: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous... Agent: Micron Technology Inc.

  
09/01/2011 > 36 patent applications in 26 patent subcategories. class, title,number

20110211382 - High density and low variability read only memory: A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to... Agent: Freescale Semiconductor, Inc.

20110211383 - Integrated circuit having variable memory array power supply voltage: An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor... Agent:

20110211385 - Semiconductor device: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix,... Agent: Renesas Electronics Corporation

20110211384 - Static random-access memory with boosted voltages: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate... Agent:

20110211386 - Low leakage high performance static random access memory cell using dual-technology transistors: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and... Agent: Qualcomm Incorporated

20110211388 - High gmr structure with low drive fields: Multi-period structures exhibiting giant magnetoresistance (GMR) are described in which the exchange coupling across the active interfaces of the structure is ferromagnetic.... Agent: Integrated Magnetoelectronics Corp.

20110211389 - Magnetoresistive element and magnetoresistive random access memory including the same: The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between... Agent: Kabushiki Kaisha Toshiba

20110211387 - Scalable nonvolatile memory: Various magnetoresistive memory cells and architectures are described which enable nonvolatile memories having high information density.... Agent: Integrated Magnetoelectronics Corp.

20110211391 - Programmable resistance memory: A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.... Agent:

20110211390 - Semiconductor device and its manufacturing method: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a... Agent: Renesas Technology Crop.

20110211393 - Flash memory device and set-up data initialization method: A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a... Agent: Samsung Electronics Co., Ltd.

20110211394 - Field effect transistors for a flash memory comprising a self-aligned charge storage region: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode... Agent:

20110211395 - Nonvolatile semiconductor memory device: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers... Agent: Kabushiki Kaisha Toshiba

20110211392 - Cell string of a memory cell array and method of erasing the same: A cell string included in a memory cell array of a nonvolatile memory device includes a plurality of memory cells, a string select transistor, and a ground select transistor. The plurality of memory cells are connected in series. The string select transistor is connected between a bitline and the plurality... Agent: Samsung Electronics Co., Ltd.

20110211396 - Nonvolatile semiconductor memory device and operation method thereof: The erase operation of a nonvolatile semiconductor memory is executed by a method including applying an erase pulse to a data erase area in a memory cell array, determining whether the threshold voltage of a memory cell arranged in the data erase area reaches an erase level and outputting a... Agent: Renesas Electronics Corporation

20110211399 - Method of manufacturing a vertical-type semiconductor device and method of operating a vertical-type semiconductor device: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower... Agent: Samsung Electronics Co., Ltd.

20110211397 - Pipe latch circuit and method for operating the same: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially... Agent:

20110211398 - Memory device and associated main word line and word line driving circuit: A main word line driving circuit for driving word lines in a memory device comprises first and second level shifting units and an inverting unit. The first level shifting unit is configured to convert a decode signal into a first operative signal, and the second level shifting unit is configured... Agent: Elite Semiconductor Memory Technology Inc.

20110211400 - Global bit select circuit interface with false write through blocking: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with... Agent: International Business Machines Corporation

20110211401 - Global bit select circuit interface with simplified write bit line precharging: A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented... Agent: International Business Machines Corporation

20110211402 - Low power floating body memory cell based on low-bandgap-material quantum well: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.... Agent:

20110211403 - Bimodal memory controller: A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically... Agent: Rambus Inc.

20110211404 - Recalibration systems and techniques for electronic memory applications: A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an... Agent: Qualcomm Incorporated

20110211406 - Address delay circuit: An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured... Agent: Hynix Semiconductor Inc.

20110211405 - External signal input circuit of semiconductor memory: In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal... Agent: Hynix Semiconductor Inc.

20110211407 - Semiconductor memory device and associated local sense amplifier: A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data... Agent: Elite Semiconductor Memory Technology Inc.

20110211408 - Semiconductor storage device: A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage... Agent: Panasonic Corporation

20110211409 - Embedded memory databus architecture: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers... Agent: Mosaid Technologies Incorporated

20110211410 - Semiconductor memory device: A semiconductor memory device having an open bit line structure includes a normal memory cell block, a reference memory cell block, and a sense amplifier. The normal memory cell block includes a plurality of normal memory cells and a driving bit line connected to the normal memory cells. The reference... Agent:

20110211411 - Semiconductor device, information processing system including same, and controller for controlling semiconductor device: To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with... Agent: Elpida Memory, Inc.

20110211412 - Table lookup voltage compensation for memory cells: Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of... Agent:

20110211415 - Integrated circuit memory device, system and method having interleaved row and column control: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to... Agent: Rambus Inc.

20110211413 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank... Agent:

20110211414 - Semiconductor memory module: A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit... Agent: Elpida Memory, Inc.

20110211416 - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality... Agent:

20110211417 - Memory device with pseudo double clock signals and the method using the same: A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and... Agent: Elite Semiconductor Memory Technology Inc.

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