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Static information storage and retrieval September class, title,number 09/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/29/2011 > 75 patent applications in 38 patent subcategories. class, title,number
20110235385 - Semiconductor memory apparatus with power-meshed structure: A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular... Agent: Hynix Semiconductor Inc.
20110235386 - Semiconductor memory device and manufacturing method of the same: The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate... Agent: Renesas Electronics Corporation
20110235387 - Semiconductor memory device: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory... Agent: Renesas Electronics Corporation
20110235388 - Nonvolatile semiconductor storage device: According to an embodiment of the invention, a nonvolatile semiconductor storage device includes a first memory cell and a second memory cell. A first fuse element in which data can be electrically written only once is provided in the first memory cell. A second fuse element in which data can... Agent: Kabushiki Kaisha Toshiba
20110235389 - Semiconductor device: An object is reduction in power consumption of a semiconductor device including a memory circuit. In the semiconductor device including a memory circuit, the memory circuit includes a memory cell including a semiconductor element and a memory cell that does not include a semiconductor element in a region defined by... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110235390 - High density memory device: A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal... Agent: International Business Machines Corporation
20110235403 - Method and apparatus managing worn cells in resistive memories: A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive... Agent: Samsung Electronics Co., Ltd.
20110235397 - Non-volatile semiconductor memory device: A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first... Agent: Kabushiki Kaisha Toshiba
20110235399 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array configured by plural memory cells each including a variable resistor and each provided between first and second lines. A control circuit applies to a memory cell through the first and second lines a writing voltage for... Agent: Kabushiki Kaisha Toshiba
20110235401 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage... Agent: Kabushiki Kaisha Toshiba
20110235392 - Nonvolatile semiconductor storage device: According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit... Agent: Kabushiki Kaisha Toshiba
20110235393 - Nonvolatile storage device: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a... Agent: Sony Corporation
20110235405 - Programming non-volatile storage element using current from other element: A non-volatile storage apparatus includes a set of Y lines, a common X line, multiple storage elements each of which is connected to the common X line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable... Agent:
20110235404 - Pulse reset for non-volatile storage: A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse... Agent:
20110235391 - Reference cell write operations at a memory: A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at... Agent: Qualcomm Incorporated
20110235394 - Semiconductor memory device: A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an... Agent: Kabushiki Kaisha Toshiba
20110235402 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing... Agent: Kabushiki Kaisha Toshiba
20110235400 - Semiconductor memory device and method for controlling the same: According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing... Agent:
20110235398 - Semiconductor memory device and operation method thereof: A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at an intersection of first lines and second lines; and a control circuit configured to execute a read operation, thereby determining a resistance state of the selected one of the memory cells.... Agent: Kabushiki Kaisha Toshiba
20110235396 - Semiconductor memory device and semiconductor device: A semiconductor memory device includes a memory cell array, a first control circuit, and a second control circuit. The first control circuit is configured to apply a first voltage to a selected first line. The second control circuit is configured to apply a second voltage having a voltage value higher... Agent: Kabushiki Kaisha Toshiba
20110235395 - Semiconductor memory device and writing method thereof: A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured... Agent: Kabushiki Kaisha Toshiba
20110235406 - Low-power 5t sram with improved stability and reduced bitcell size: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically... Agent: Industry-academic Cooperation Foundation, Yonsei University
20110235407 - Semiconductor memory device and a method of manufacturing the same: A semiconductor memory device including a substrate, wherein the substrate includes first, second and third well regions, the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second... Agent:
20110235408 - Semiconductor memory device: For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the... Agent: Hitachi, Ltd.
20110235409 - Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells... Agent:
20110235412 - Controlling ac disturbance while programming: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate... Agent: Spansion LLC
20110235410 - Device and method to read data subject to a disturb condition: A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and... Agent: Sandisk Il Ltd.
20110235413 - Nonvolatile semiconductor memory device and method of controlling nonvolatile semiconductor memory device: A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially... Agent: Kabushiki Kaisha Toshiba
20110235414 - Semiconductor memory device: According to one embodiment, a semiconductor memory device comprises a memory cell array, a controller. A memory cell array comprises bit lines, and memory cells configured to store different states, i.e., m values or n values. When storing the n values in a memory cell, the controller performs a first... Agent:
20110235415 - Read method for nonvolatile memory device, and data storage system using the same: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method... Agent:
20110235417 - Nand flash memory: A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units... Agent: Kabushiki Kaisha Toshiba
20110235416 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device for raising operating speed is provided. The nonvolatile semiconductor memory device includes plural bit lines extending in a first direction, and a memory cell that includes plural blocks each having plural NAND strings each of which includes a group of memory cells connected in series... Agent: Kabushiki Kaisha Toshiba
20110235418 - Determining memory page status: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.... Agent: Micron Technology, Inc.
20110235419 - Non-volatile semiconductor storage device: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected... Agent: Renesas Electronics Corporation
20110235422 - Apparatus having a string of memory cells: Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target... Agent: Micron Technology, Inc.
20110235424 - Hierarchical common source line structure in nand flash memory: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line... Agent: Mosaid Technologies Incorporated
20110235421 - Nonvolatile semiconductor memory device: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a... Agent: Kabushiki Kaisha Toshiba
20110235420 - Simultaneous multi-state read or verify in non-volatile storage: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a... Agent:
20110235423 - Verification process for non-volatile storage: When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.... Agent:
20110235426 - Flash memory system having a plurality of serially connected devices: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits... Agent: Mosaid Technologies Incorporated
20110235425 - Method of directly reading output voltage to determine data stored in a non-volatile memory cell: An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling.... Agent:
20110235427 - Channel hot electron injection programming method and related device: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple... Agent:
20110235428 - Compensation of non-volatile memory chip non-idealities by program pulse adjustment: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse... Agent:
20110235429 - Method and apparatus for programming flash memory: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.... Agent:
20110235411 - Fast programming memory device: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line,... Agent:
20110235430 - Memory device and method: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to... Agent: Spansion LLC.
20110235432 - Method of erasing in non-volatile memory device: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are... Agent:
20110235431 - Nonvolatile semiconductor memory and method of operating the same: According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier... Agent:
20110235433 - Verifying an erase threshold in a memory device: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well... Agent: Micron Technology, Inc.
20110235435 - Non-volatile memory and method for power-saving multi-pass sensing: A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles... Agent:
20110235434 - Systems and methods for refreshing non-volatile memory: Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved... Agent: Apple Inc.
20110235436 - Semiconductor memory device: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be... Agent: Kabushiki Kaisha Toshiba
20110235437 - Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using pip or mim coupling capacitor for cell size reduction and simultaneous vpp and vnn for write voltage reduction: A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a... Agent:
20110235443 - Voltage stabilization circuit and semiconductor memory apparatus using the same: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in... Agent: Hynix Semiconductor Inc.
20110235438 - Temporal alignment of data unit groups in a switch: Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit... Agent: Infinera Corporation
20110235439 - Static memory cell having independent data holding voltage: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage... Agent: Renesas Electronics Corporation
20110235440 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain... Agent: Renesas Electronics Corporation
20110235441 - High voltage generating circuit and semiconductor memory device having the same and method thereof: A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to... Agent:
20110235442 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent:
20110235444 - Sram writing system and related apparatus: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing... Agent: Faraday Technology Corporation
20110235445 - Method and system to lower the minimum operating voltage of register files: A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS... Agent:
20110235446 - Write strobe generation for a memory interface controller: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data... Agent: Juniper Networks, Inc.
20110235447 - Low power memory array column redundancy mechanism: A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value... Agent:
20110235448 - Using differential signals to read data on a single-end port: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110235450 - Current mode sense amplifier with passive load: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop... Agent: Micron Technology, Inc.
20110235449 - Dual sensing current latched sense amplifier: A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a... Agent: Qualcomm Incorporated
20110235451 - Dynamic random access memory and method of driving dynamic random access memory: A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage... Agent: Elite Semiconductor Memory Technology Inc.
20110235453 - Fuse circuit and repair control circuit using the same: A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between... Agent:
20110235452 - Semiconductor memory device and method for operating the same: A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.... Agent:
20110235454 - High-voltage selecting circuit which can generate an output voltage without a voltage drop: A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when... Agent:
20110235456 - Power supply control circuit and semiconductor apparatus including the same: A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of... Agent: Hynix Semiconductor Inc.
20110235457 - Semicondcutor integrated circuit device: According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having... Agent: Kabushiki Kaisha Toshiba
20110235455 - Voltage regulators, amplifiers, memory devices and methods: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The... Agent: Micron Technology, Inc.
20110235458 - Electric device: In one embodiment, an electric device includes a memory, first and second generators, a limit unit, and a reduction unit. The first generator generates the chip select signal representing an inactive mode or an active mode according to a potential of an enable terminal and a input potential The second... Agent: Toshiba Tec Kabushiki Kaisha
20110235459 - Clock-forwarding low-power signaling system: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal,... Agent: Rambus Inc.09/22/2011 > 48 patent applications in 27 patent subcategories. class, title,number
09/15/2011 > 35 patent applications in 21 patent subcategories. class, title,number
09/08/2011 > 53 patent applications in 37 patent subcategories. class, title,number
09/01/2011 > 36 patent applications in 26 patent subcategories. class, title,number
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