|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
08/2011 | Recent | 14: Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval August inventions list 08/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/25/2011 > 59 patent applications in 40 patent subcategories. inventions list
20110205775 - Semiconductor device: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is formed using a material capable of sufficiently reducing the off-state current of a transistor, such as... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110205777 - Semiconductor memory device having vertical transistors: A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding... Agent: Elpida Memory, Inc.
20110205774 - Semiconductor memory device, driving method thereof, and method for manufacturing semiconductor device: A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110205776 - Semiconductor storage circuit: The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers,... Agent: Oki Semiconductor Co., Ltd.
20110205778 - Current detection circuit for detecting read current from a memory cell: A current detection circuit that can normally perform a current detection operation to detect a current in a memory cell of a memory device even if an applied power supply voltage is a low voltage, includes a current detection means which comprises first and second MOS transistors of a same... Agent: Oki Semiconductor Co., Ltd.
20110205781 - Non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device includes: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line, wherein, the memory cell includes: a variable resistance element; and a negative... Agent: Kabushiki Kaisha Toshiba
20110205784 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and... Agent: Kabushiki Kaisha Toshiba
20110205780 - Semiconductor integrated circuit: In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected... Agent:
20110205783 - Semiconductor memory device: A semiconductor memory device comprises a plurality of first row lines arranged in parallel; a plurality of column lines intersecting the first row lines; a plurality of storage elements arranged at intersections of the first row lines and the column lines; a plurality of second row lines arranged in parallel... Agent:
20110205779 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The memory cell array has memory cells arranged therein at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a variable resistance... Agent: Kabushiki Kaisha Toshiba
20110205782 - Step soft program for reversible resistivity-switching elements: A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a... Agent:
20110205785 - Semiconductor device and driving method of semiconductor device: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110205787 - Dual-rail sram with independent read and write ports: A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of... Agent: Nxp B.v.
20110205786 - Memory design: An improved memory design is described which removes the need to read firmware from ROM into RAM on start-up. A SRAM memory element comprises an influencing element which sets the state of the memory cells within the memory element on start-up to defined values. These defined values are set at... Agent: Cambridge Silicon Radio Ltd.
20110205788 - Spin-torque bit cell with unpinned reference layer and unidirectional write current: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between... Agent: Seagate Technology LLC
20110205790 - Phase-change memory device: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective... Agent: Kabushiki Kaisha Toshiba
20110205789 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among... Agent: Hynix Semiconductor Inc.
20110205791 - Temperature compensation in memory devices and systems: The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current... Agent: Micron Technology, Inc.
20110205793 - Method for accessing multi-level non-volatile memory cell: A method for accessing a multi-level non-volatile memory cell includes the following steps: determining at least one target word line voltage according to a target bit to be read from a plurality of bits stored in the multi-level non-volatile memory cell; and applying the at least one target word line... Agent:
20110205794 - Nonvolatile semiconductor memory device having protection function for each memory block: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When... Agent:
20110205795 - Memory device: With a serial interface memory device of this invention, a read-out rate of data is increased, while an increase in a size of a circuit is suppressed. An EEPROM is provided with a memory cell array storing data, a row address decoder and a column address decoder that select an... Agent: On Semiconductor Trading, Ltd.
20110205796 - Nonvolatile memory device and system performing repair operation for defective memory cell: A nonvolatile memory device comprises a main memory cell array, a redundancy memory cell array, and a controller. The main memory cell array comprises a plurality of bit lines each connected to a plurality of strings arranged perpendicular to a substrate. The redundancy memory cell array comprises a plurality of... Agent: Samsung Electronics Co., Ltd.
20110205798 - High speed operation method for twin monos metal bit array: The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates... Agent: Halo Lsi, Inc.
20110205797 - Method and apparatus for performing multi-block access operation in nonvolatile memory device: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The... Agent: Samsung Electronics Co., Ltd.
20110205799 - Operation method of memory device: A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a... Agent: Acer Incorporated
20110205800 - Memory devices having strings of series-coupled memory cells selectively coupled to different bit lines: Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same... Agent: Micron Technology, Inc.
20110205802 - Nonvolatile memory device and method of reading the same: Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of... Agent: Samsung Electronics Co., Ltd.
20110205801 - Semiconductor memory device: In writing operation, charge pumps of a memory apply any of first to n-th voltages which are different from each other. An application-voltage selector selects voltages to be applied to WLs among the first to n-th voltages. A word-line number register stores the number of WLs to which each of... Agent: Kabushiki Kaisha Toshiba
20110205803 - Random telegraph signal noise reduction scheme for semiconductor memories: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on... Agent: Micron Technology, Inc.
20110205792 - Memory device reference cell programming method and apparatus: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference... Agent: Micron Technology, Inc.
20110205804 - High speed sense amplifier array and method for non-volatile memory: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An... Agent:
20110205805 - Nonvolatile semiconductor memory device and memory system: A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is created such that pieces of x-bit data assigned to adjacent threshold distributions have only a one-bit difference therebetween and an alignment of data on... Agent: Kabushiki Kaisha Toshiba
20110205806 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column... Agent:
20110205807 - Semiconductor memory device and data write method thereof: A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other... Agent:
20110205808 - Semiconductor memory and system: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the... Agent: Fujitsu Semiconductor Limited
20110205809 - Bit line decoder architecture for nor-type memory array: An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state... Agent:
20110205810 - Nonvolatile semiconductor storage device: According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a... Agent: Kabushiki Kaisha Toshiba
20110205816 - Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device and method of operating a vertical semiconductor device: A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar... Agent:
20110205811 - Semiconductor device and method of controlling the same: A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a... Agent:
20110205812 - Semiconductor device: A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the... Agent: Elpida Memory, Inc.
20110205813 - Power-off apparatus, systems, and methods: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to... Agent:
20110205815 - Decoder circuit of semiconductor storage device: The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of... Agent: Oki Semiconductor Co., Ltd.
20110205814 - Sense amplifier and method of sensing data using the same: Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110205817 - Method and apparatus for managing open blocks in nonvolatile memory device: A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller... Agent: Samsung Electronics Co., Ltd.
20110205818 - Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command: A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according... Agent:
20110205819 - Redundancy data storage circuit, redundancy data control method and repair determination circuit of semiconductor memory: A redundancy data storage circuit of a semiconductor memory includes a memory cell array; a write driver configured to write redundancy data in the memory cell array in response to a test signal; and a sense amplifier configured to detect and output the redundancy data written in the memory cell... Agent: Hynix Semiconductor Inc.
20110205820 - Semiconductor device: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second... Agent:
20110205822 - Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell: A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and... Agent: Samsung Electronics Co., Ltd.
20110205821 - Semiconductor device having sense amplifiers: A semiconductor device includes a plurality of memory cells connected to a word line, sense amplifiers arranged correspondingly to the memory cells, and a sense-amplifier control circuit that activates the sense amplifiers in response to selection of the word line and temporarily reduces driving performance of the sense amplifiers in... Agent: Elpida Memory, Inc.
20110205823 - Non-volatile storage with temperature compensation based on neighbor state information: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target... Agent:
20110205824 - Data processing system: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first... Agent: Elpida Memory, Inc
20110205825 - Reduced signal interface memory device, system, and method: A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one.... Agent:
20110205826 - Storage control device, storage device and storage device system: Disclosed herein is a storage control device that includes a temperature sensor, temperature information selection section, refresh command reception section and trigger issuance frequency setting section.... Agent: Sony Corporation
20110205827 - Semiconductor integrated circuit: A system LSI (100) having a logic circuit (104) and a plurality of SRAM macros (103) includes a power supply circuit (102) configured to receive a voltage (VDDP) supplied from the outside of the system LSI (100), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An... Agent:
20110205828 - Semiconductor memory with memory cell portions having different access speeds: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the... Agent: Qimonda Ag
20110205830 - Semiconductor control line address decoding circuit: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero... Agent: Seagate Technology LLC
20110205829 - Semiconductor memory device: In order to latch and store a word line reset level voltage (negative voltage) which is set during reset operation, a word line driver includes PMOS transistors and NMOS transistors. The word line driver further includes a stress-reducing PMOS transistor and an NMOS transistor, and also a word line bias... Agent: Panasonic Corporation
20110205831 - System and method for processing signals in high speed dram: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at... Agent: Micron Technology, Inc.
20110205832 - On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination: An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination... Agent:08/18/2011 > 49 patent applications in 32 patent subcategories. inventions list
20110199803 - Semiconductor device with a selection circuit selecting a specific pad: A semiconductor device includes a selection circuit for selecting a specific pad of a semiconductor memory. The semiconductor device is configured to produce a signal determined by a pin array by the selection circuit.... Agent: Elpida Memory, Inc.
20110199804 - Three-dimensional semiconductor device and related method of operation: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical... Agent: Samsung Electronics Co., Ltd.
20110199805 - Selective access memory circuit: A selective access memory circuit (SAMC) is described. The SAMC is a class of complex programmable memory device (CPMD) that reconfigures access to memory cells by using gates in an integrated gate array mechanism configured at regular intervals in memory arrays. CPMDs are applied to embedded controllers, microprocessors, DSPs and... Agent:
20110199806 - Universal structure for memory cell characterization: An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes,... Agent: Texas Instruments Incorporated
20110199808 - Memory device from which dummy edge memory block is removed: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit... Agent: Samsung Electronics Co., Ltd.
20110199807 - Semiconductor device and method for driving the same: A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110199809 - Security circuit having an electrical fuse rom: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.... Agent: Samsung Electronics Co., Ltd.
20110199810 - Data holding device: A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NAND3 and NAND4) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion... Agent: Rohm Co., Ltd.
20110199813 - Non-volatile memory device having 3d structure and method for fabricating the same: A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stacked over a substrate, a plurality of pillar-type vertical electrodes configured to protrude from the... Agent:
20110199811 - Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device: According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series... Agent: Kabushiki Kaisha Toshiba
20110199812 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory element in which a rate of charge discharge between two electrodes of the memory element differs according to a logical value of stored information; cell wiring connected to one electrode of the memory element; a sense amplifier having a sense node connected... Agent: Sony Corporation
20110199814 - Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line... Agent:
20110199815 - Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming: A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another... Agent:
20110199816 - Semiconductor device and driving method of the same: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110199817 - Robust local bit select circuitry to overcome timing mismatch: An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second... Agent: International Business Machines Corporation
20110199818 - Method of initializing magnetic memory element: An initialization method is provided for a magnetic memory element including: a data recording layer having perpendicular magnetic anisotropy which includes: a first magnetization fixed region, a second magnetization fixed region, and a magnetization free region coupled to the first magnetization fixed region and the second magnetization fixed region, the... Agent:
20110199819 - Apparatus and method for extended nitride layer in a flash memory: A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer... Agent: Spansion LLC
20110199822 - Method and apparatus for controlling page buffer of non-volatile memory device: A method of managing a page buffer of a non-volatile memory device comprises programming least significant bit (LSB) page data from an LSB page buffer into a page of memory cells, and retaining the LSB page data in the LSB page buffer until most significant bit (MSB) page data corresponding... Agent: Samsung Electronics Co., Ltd.
20110199823 - Preloading data into a flash storage device: Programmer's data that is transferred from a programming device (160) to a storage device (100) is initially stored in a memory device (120) of the storage device (100) by using a durable data-retention storage setup (210). After the storage device is embedded in a host device (170), the programmer's data... Agent: Sandisk Il Ltd.
20110199826 - Charge loss compensation methods and apparatus: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and... Agent: Micron Technology, Inc.
20110199825 - Nonvolatile memory device, operating method thereof, and memory system including the same: Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and... Agent: Samsung Electronics Co., Ltd.
20110199824 - Storing operational information in an array of memory cells: The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a... Agent: Micron Technology, Inc.
20110199827 - Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source select gate: Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the... Agent: Micron Technology, Inc.
20110199828 - Nonvolatile memory device and method of operating same: A nonvolatile memory device comprises a bulk region and a plurality of memory cells connected to a source line and a plurality of wordlines. The method comprises applying a source line voltage to the source line with a first magnitude, applying a bulk voltage to the bulk region with a... Agent: Samsung Electronics Co., Ltd.
20110199829 - Nonvolatile memory device, programming method thereof and memory system including the same: Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two... Agent: Samsung Electronics Co., Ltd.
20110199831 - Coarse and fine programming in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse... Agent: Micron Technology, Inc.
20110199830 - Flotox-based, bit-alterable, combo flash and eeprom memory: A non-volatile memory array having FLOTOX-based memory cells connected by a plurality of word lines and a plurality of bit lines is disclosed. In the memory array, the FLOTOX-based memory cells in a common word line do not share a common source line. Instead, the FLOTOX-based memory cells associated with... Agent:
20110199832 - Magnetic floating gate memory: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.... Agent: Seagate Technology LLC
20110199820 - Non-volatile semiconductor memory having multiple external power supplies: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes... Agent:
20110199821 - Power management chip furnished with voltage controller: A power management IC includes a first IC having a boost converter IC which generates a second voltage using a first voltage supplied from an outside and supplies the second voltages to a charge pump, a reference voltage generation circuit, and an EEPROM; and a second IC configured to be... Agent: Silicon Works Co., Ltd
20110199833 - Non-volatile memory devices, operating methods thereof and memory systems including the same: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages... Agent: Samsung Electronics Co., Ltd.
20110199834 - Method for driving a nonvolatile semiconductor memory device: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage... Agent: Kabushiki Kaisha Toshiba
20110199835 - No-disturb bit line write for improving speed of edram: A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199836 - Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect: The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a... Agent:
20110199837 - High voltage word line driver: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control... Agent: International Business Machines Corporation
20110199838 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes a three-dimensional memory cell array, write drivers, and a program voltage control circuit. In the three-dimensional memory cell array, memory cells are three-dimensionally arranged. The write drivers are arranged to be distributed under the three-dimensional memory cell array and apply a... Agent: Kabushiki Kaisha Toshiba
20110199839 - Weak bit compensation for static random access memory: A static random access memory (SRAM) includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage,... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199841 - Semiconductor memory device having low power consumption type column decoder and read operation method thereof: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder... Agent: Hynix Semiconductor Inc.
20110199840 - Semiconductor storage device: A device includes a memory cell array having a plurality of memory cells; sense amplifiers, which are arranged adjacent to the memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells; readout signal lines; a plurality of connection circuits for selectively connecting... Agent: Elpida Memory, Inc.
20110199842 - Dram cell utilizing floating body effect and manufacturing method thereof: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on... Agent: Shanghai Institute Of Microsysem And Information Techno.ogy. Chinese Academy
20110199844 - Semiconductor memory device suitable for mounting on a portable terminal: A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect... Agent: Renesas Technology Corp.
20110199843 - Strobe offset in bidirectional memory strobe configurations: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training... Agent: International Business Machines Corporation
20110199845 - Redundancy circuits and operating methods thereof: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO)... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199846 - Y-decode controlled dual rail memory: An embodiment of the invention is related to a memory that includes a memory array having a plurality of memory banks, each of which includes a plurality of rows and a plurality of columns of memory cells. Each memory column includes a switch circuit providing a first voltage and a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199847 - Sense amplifier with low sensing margin and high device variation tolerance: In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199848 - Techniques for controlling a semiconductor memory device: Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying... Agent: Innovative Silicon Isi Sa
20110199849 - Sense amplifier for controlling flip error and driving method thereof: A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit line from a sense amplifying... Agent:
20110199850 - Memory readout scheme using separate sense amplifier voltage: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110199851 - Memory controller, semiconductor storage device, and memory system including the memory controller and the semiconductor storage device: A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes... Agent: Elpida Memory, Inc.08/11/2011 > 46 patent applications in 30 patent subcategories. inventions list
20110194325 - Error detection in a content addressable memory (cam): A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for... Agent:
20110194326 - Memory dies, stacked memories, memory devices and methods: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged... Agent:
20110194327 - Semiconductor device and method of driving semiconductor device: The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110194330 - Memory array with read reference voltage cells: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage... Agent: Seagate Technology LLC
20110194329 - Memory component, memory device, and method of operating memory device: A memory component includes: a first electrode; a memory layer; and a second electrode which are provided in that order, wherein the memory layer includes an ion source layer containing aluminum (Al) together with at least one chalcogen element selected from the group consisting of tellurium (Te), sulfur (S), and... Agent: Sony Corporation
20110194328 - Variable resistance memory device and related method of operation: A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that... Agent: Samsung Electronics Co., Ltd.
20110194332 - Semiconductor device: An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110194331 - Semiconductor device and method of driving semiconductor device: The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110194334 - Diode assisted switching spin-transfer torque memory unit: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured... Agent: Seagate Technology LLC
20110194335 - Magnetic memory with phonon glass electron crystal material: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron... Agent: Seagate Technology LLC
20110194336 - Memory cells, memory cell constructions, and memory cell programming methods: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through... Agent:
20110194338 - Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second... Agent:
20110194337 - Non-volatile memory cell with precessional switching: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive... Agent: Seagate Technology LLC
20110194333 - System and method to select a reference cell: A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of... Agent: Qualcomm Incorporated
20110194339 - Microelectronic programmable device and methods of forming and programming the same: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the... Agent: Axon Technologies Corporation
20110194340 - Phase change device with offset contact: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.... Agent:
20110194342 - Nonvolatile memory circuit using spin mos transistors: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the... Agent: Kabushiki Kaisha Toshiba
20110194341 - Spin-torque based memory device with read and write current paths modulated with a non-linear shunt resistor: A spin-torque based memory device includes a write portion including a fixed ferromagnetic spin-polarizing layer, a spin-transport layer having a spin accumulation region formed above the fixed ferromagnetic spin-polarizing layer. The memory device further includes a read portion in electrical contact with the spin-transport layer. The read portion includes a... Agent: International Business Machines Corporation
20110194343 - Stram with compensation element and method of making the same: Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic... Agent: Seagate Technology LLC
20110194344 - Semiconductor device: To provide a semiconductor device that can suppress deterioration in transistors and has a small layout area. In a nonvolatile semiconductor memory device according to the present invention, a control voltage (4 V) between a write voltage (10 V) and a reference voltage (0 V) is applied to a gate... Agent: Renesas Electronics Corporation
20110194348 - Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution: A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage... Agent:
20110194346 - Flash memory device using adaptive program verification scheme and related method of operation: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a... Agent: Samsung Electronics Co., Ltd.
20110194347 - Nonvolatile memory devices having improved read reliability: Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages... Agent:
20110194349 - Nonvolatile semiconductor memory device: In one embodiment, a nonvolatile semiconductor memory device includes a substrate provided with a memory cell part and sense amplifiers on a surface of the substrate, first isolation regions and first device regions disposed in the substrate under the memory cell part, and second isolation regions and second device regions... Agent: Kabushiki Kaisha Toshiba
20110194350 - Compensation of back pattern effect in a memory device: In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge... Agent: Micron Technology, Inc.
20110194351 - Source side asymmetrical precharge programming scheme: A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to... Agent: Mosaid Technologies Incorporated
20110194353 - Method of programming memory cells for a non-volatile memory device: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a... Agent: Samsung Electronics Co., Ltd
20110194354 - Non-volatile semiconductor memory device: When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a... Agent:
20110194352 - Programming methods and memories: Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.... Agent: Micron Technology, Inc.
20110194345 - Nonvolatile semiconductor storage device including failure detection circuit and method of detecting failure on nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device includes: a word line; a reading circuit; and a failure detection circuit. The word line is connected to gates of a plurality of nonvolatile memory cell transistors. The reading circuit is connected to one end of the word line and supplies one of a reading... Agent: Renesas Electronics Corporation
20110194355 - Verify while write scheme for non-volatile memory cell: A verify while write (VWW) scheme for a non-volatile memory (NVM) cell is provided. The VWW scheme conducts simultaneous write and verify operation by sensing the memory cell current during the write pulse at exactly the same write bias condition in contrast to the “verify+retry-write” write algorithm in the prior... Agent: Ememory Technology Inc.
20110194356 - Methods of forming and operating semiconductor device: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper... Agent: Seoul National University Industry Foundation
20110194357 - Nonvolatile memory devices, operating methods thereof and memory systems including the same: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to... Agent: Samsung Electronics Co., Ltd.
20110194363 - Semiconductor memory cell and array using punch-through to program and read same: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part,... Agent: Micron Technology, Inc.
20110194358 - Semiconductor memory device using internal high power supply voltage in self-refresh operation mode and related method of operation: A semiconductor memory device comprises a memory cell array comprising a plurality of memory banks. The semiconductor memory device performs refresh operations on the memory cell array using a normal refresh operation mode and a self-refresh operation mode. In the normal refresh operation mode, the semiconductor memory device performs refresh... Agent: Samsung Electronics Co., Ltd.
20110194359 - Semiconductor device and semiconductor module: A semiconductor device according to the present invention performs, when a first word structure is designated, control such that input and output of data is performed from a first data input/output terminal and from a second data input/output terminal in response to a first strobe signal and a second strobe... Agent: Elpida Memory, Inc.
20110194360 - Semiconductor device and method of detecting abnormality on semiconductor device: A semiconductor device includes: a plurality of word lines; a word line driver; a first detection circuit; and a control circuit. The plurality of word lines is connected to gates of a plurality of memory cell transistors, respectively. The word line driver supplies one of a selection voltage and a... Agent: Renesas Electronics Corporation
20110194361 - Semiconductor device: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along... Agent:
20110194362 - Word-line driver using level shifter at local control circuit: A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20110194364 - Nvm overlapping write method: The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by... Agent: Infineon Technologies Ag
20110194365 - Bridge device architecture for connecting discrete memory devices to a system: Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface... Agent: Mosaid Technologies Incorporated
20110194366 - Nonvolatile data storage devices, program methods thereof, and memory systems including the same: Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected memory blocks may include a first memory block that is to be programmed and a second memory block that is to... Agent: Samsung Electronics Co., Ltd.
20110194367 - Systems, memories, and methods for refreshing memory arrays: Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to the digit line of at least one section of the memory cell array and coupled to... Agent: Micron Technology, Inc.
20110194368 - Regulator and semiconductor device: A regulator including a differential amplifier including a differential input stage that differentially receives a reference voltage and an output terminal voltage of the regulator, a drive transistor that has an output connected to an output terminal of the regulator and that has a control terminal connected to an output... Agent: Renesas Electronics Corporation
20110194369 - Variable memory refresh devices and methods: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D... Agent:
20110194370 - Memory having asynchronous read with fast read output: A memory circuit is disclosed. The memory circuit includes memory cells and asynchronous read decode logic configured to decode a received address and to select particular ones of the memory cells for reading. The read decode logic may be comprised of static, combinational logic, and thus the decoding of the... Agent:08/04/2011 > 55 patent applications in 30 patent subcategories. inventions list
20110188283 - Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some... Agent: Unity Semiconductor Corporation
20110188284 - Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional... Agent: Unity Semiconductor Corporation
20110188281 - Local bit lines and methods of selecting the same to access memory elements in cross-point arrays: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated... Agent: Unity Semiconductor Corporation
20110188282 - Memory architectures and techniques to enhance throughput for cross-point arrays: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments,... Agent: Unity Semiconductor Corporation
20110188286 - Electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart... Agent: Samsung Electronics Co., Ltd.
20110188285 - Permanent solid state memory: A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The data... Agent:
20110188287 - High speed fram including a deselect circuit: High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of ferroelectric capacitors of unselected memory cell while a plate line of the ferroelectric capacitors is forced to... Agent:
20110188288 - Semiconductor memory device and driving method therefor: A memory includes a first conductive-type first diffusion layer on the semiconductor substrate; second conductive-type bodies on the first diffusion layer(s); first conductive-type second diffusion layers on the bodies; first gate dielectric films comprising ferroelectric films and provided on first side surfaces of the bodies; second gate dielectric films comprising... Agent: Kabushiki Kaisha Toshiba
20110188289 - Access signal adjustment circuits and methods for memory cells in a cross-point array: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a... Agent: Unity Semiconductor Corporation
20110188294 - Multiplexer/de-multiplexer memristive device: A multiplexing/de-multiplexing memristive device (300) includes a memristive matrix (370) containing mobile dopants; and programming electrodes (310, 320) which apply programming electrical field such that the mobile dopants selectively form a conductive band (380) which connects a first signal electrode (330) to one of a plurality of second electrodes (350).... Agent:
20110188293 - Non-volatile memory cell with non-ohmic selection layer: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to... Agent: Seagate Technology LLC
20110188291 - Preservation circuit and methods to maintain values representing data in one or more layers of memory: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power.... Agent: Unity Semiconductor Corporation
20110188290 - Semiconductor devices including variable resistance materials and methods of operating the same: Semiconductor devices including variable resistance materials and methods of operating the semiconductor devices. The semiconductor devices use variable resistance materials with resistances that vary according to applied voltages as channel layers.... Agent: Samsung Electronics Co., Ltd.
20110188292 - Variable resistance memory, operating method and system: Provided is an operating method of a variable resistance memory device. The operating method applies a set pulse to a plurality of memory cells to be written in a set state, and applies a reset pulse to a plurality of memory cells to be written in a reset state. The... Agent: Samsung Electronics Co., Ltd.
20110188295 - High performance edram sense amplifier: Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state.... Agent: International Business Machines Corporation
20110188296 - Semiconductor memory device and semiconductor device: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110188299 - Data storage device: A data storage device (2) comprising a plurality of stacked layers (4) of memory cells (6) is disclosed. Each memory cell comprises a first magnetic layer (5), including an elongate curved portion (10), and a second magnetic layer. The first magnetic layer is adapted to be selectively magnetised to adopt... Agent:
20110188297 - Magnetic memory element, driving method for same, and nonvolatile storage device: In accordance with one aspect of the invention, a magnetic memory element records information in a spin valve structure having a free layer, a pinning layer, and a nonmagnetic layer sandwiched therebetween. The magnetic memory element further has, on the free layer, a separate nonmagnetic layer and a magnetic change... Agent:
20110188298 - Magnetoresistance element, mram, and initialization method for magnetoresistance element: A magnetoresistance element is provided with: a magnetization recording layer that is a ferromagnetic layer. The magnetization recording layer includes: a magnetization reversal region having a reversible magnetization; a first magnetization fixed region connected to a first boundary of the magnetization reversal region and having a magnetization direction fixed in... Agent:
20110188300 - Non-volatile memory with stray magnetic field compensation: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that... Agent: Seagate Technology LLC
20110188301 - Shared bit line and source line resistive sense memory structure: A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line... Agent: Seagate Technology LLC
20110188302 - Method of driving phase change memory device capable of reducing heat disturbance: A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as... Agent: Hynix Semiconductor Inc.
20110188304 - Multiple level cell phase-change memory devices having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices: A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time... Agent: Samsung Electronics Co., Ltd.
20110188303 - Phase change memory device generating program current and mehtod thereof: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of... Agent:
20110188306 - Increased magnetic damping for toggle mram: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one... Agent: International Business Machines Corporation
20110188305 - Read disturb free smt mram reference cell circuit: An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance.... Agent: Magic Technologies, Inc.
20110188307 - Nonvolatile semiconductor memory device and method for driving same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets... Agent: Kabushiki Kaisha Toshiba
20110188309 - Semiconductor device: According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from... Agent: Kabushiki Kaisha Toshiba
20110188310 - Nonvolatile memory devices with common source line voltage compensation and methods of operating the same: A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line... Agent: Samsung Electronics Co., Ltd.
20110188311 - Efficient memory sense architecture: Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are... Agent: Texas Instruments Incorporated
20110188313 - Data retention of last word line of non-volatile memory arrays: Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the... Agent:
20110188312 - Method for memory cell erasure with a programming monitor of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on... Agent: Micron Technology, Inc.
20110188314 - Bit line stability detection: A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read... Agent:
20110188315 - Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control: A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during... Agent: Kabushiki Kaisha Toshiba
20110188316 - Semiconductor memory device: This invention offers a semiconductor memory device, with which a resolution to read-out data is not reduced even at the time of verify and a stable read-out operation is possible even when a power supply voltage is reduced. A read-out circuit is provided with a current-voltage conversion circuit, that converts... Agent: Sanyo Semiconductor Co., Ltd.
20110188318 - Flash memory device and a method of verifying the same: Provided are a flash memory device and a method of verifying the same. The flash memory device includes: a memory cell for storing data; a sense amplifier for reading information of the memory cell; a load current input device for providing a load current to the sense amplifier; and a... Agent:
20110188320 - Memory devices and methods of their operation including selective compaction verify operations: Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify operation indicates compaction is desired,... Agent: Micron Technology, Inc.
20110188317 - Non-volatile memory with fast binary programming and reduced power consumption: In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0”... Agent:
20110188319 - Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage... Agent: Kabushiki Kaisha Toshiba
20110188321 - Nonvolatile semiconductor memory device and method for driving the same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film, a first insulating film provided adjacent to one surface of the charge storage film, a second insulating film provided adjacent to one other surface of... Agent: Kabushiki Kaisha Toshiba
20110188308 - Over erase correction method of flash memory apparatus: An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the... Agent: Elite Semiconductor Memory Technology Inc.
20110188323 - Data output circuit of semiconductor memory and related method: Various embodiments of a data output circuit of a semiconductor memory and related method are disclosed. In one exemplary embodiment, a data output circuit may include a plurality of global lines, a sense amplifier block configured to output a plurality of data to the plurality of global lines at different... Agent: Hynix Semiconductor Inc.
20110188322 - Memory device with data paths for outputting compressed data: A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the... Agent: Elite Semiconductor Memory Technology Inc.
20110188324 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data... Agent: Hynix Semiconductor Inc.
20110188325 - Semiconductor device and data processing system: A semiconductor device comprises a bit line transmitting a signal to be sensed, a single-ended sense amplifier sensing and amplifying the signal transmitted from the bit line to the input node, and a reference voltage supplying circuit outputting a reference voltage. The sense amplifier includes a first transistor for charge... Agent: Elpida Memory, Inc.
20110188326 - Dual rail static random access memory: A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110188327 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with... Agent: Panasonic Corporation
20110188329 - Semiconductor integrated circuit: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under... Agent: Renesas Electronics Corporation
20110188328 - Systems and methods for writing to multiple port memory circuits: A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word... Agent: Qualcomm Incorporated
20110188330 - Semiconductor storage device: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable... Agent: Renesas Electronics Corporation
20110188331 - Semiconductor apparatus: A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column... Agent: Hynix Semiconductor Inc.
20110188332 - Semiconductor memory device having regular area and spare area: Memory arrays ARY0 and ARY1 each include a regular area 108 and spare area 110. Fuse circuits FS0 and FS1 each store a relief address. Relief determination circuits RJ0 and RJ1 are provided so as to correspond to the fuse circuits FS0 and FS1, respectively. The relief determination circuits RJ0... Agent: Elpida Memory, Inc.
20110188333 - Semiconductor memory device and method of driving the same: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for... Agent: Samsung Electronics Co., Ltd.
20110188334 - Fuse circuit and semiconductor device having the same: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of... Agent:
20110188335 - Hierarchical multi-bank multi-port memory organization: A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests... Agent: Mosys, Inc.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140710:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.02113 seconds