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Static information storage and retrieval July category listing 07/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/28/2011 > 34 patent applications in 19 patent subcategories. category listing
20110182098 - Integrated circuits and methods for forming the same: An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110182100 - Semiconductor device having multiport memory: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed... Agent: Renesas Electronics Corporation
20110182099 - Semiconductor memory device for reducing bit line coupling noise: A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying... Agent:
20110182101 - Semiconductor memory device with security function and control method thereof: A semiconductor memory device includes a security controller. When a one time programmable (OTP) device is programmed, the semiconductor memory device prohibits lock-status information pre-stored in an OTP lock register from being changed to an unlock status, such that it increases the stability of data stored in an OTP area.... Agent: Hynix Semiconductor Inc.
20110182102 - Semiconductor memory device: A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate... Agent: Kabushiki Kaisha Toshiba
20110182106 - Current cancellation for non-volatile memory: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of... Agent: Seagate Technology LLC
20110182103 - Gcib-treated resistive device: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material... Agent: Micron Technology, Inc.
20110182105 - Memory system with sectional data lines: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage... Agent:
20110182107 - Memristive device: A memristive routing device (200) includes a memristive matrix (240), mobile dopants (255) moving with the memristive matrix (240) in response to programming electrical fields and remaining stable within the memristive matrix (240) in the absence of the programming electrical fields; and at least three electrodes (210, 220, 230) surrounding... Agent: Hewlett-packard Development Company, L.p.
20110182108 - Memristive device and methods of making and using the same: A memristive device is disclosed herein. The device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two mobile species are present in the active region. Each of the at least two mobile species is configured to define a... Agent: Hewlett-packard Development Company, L.p.
20110182104 - Method of implementing memristor-based multilevel memory using reference resistor array: The present invention relates to a memristor, and more particularly, to a method of implementing a memristor-based multilevel memory using a reference resistor array and a write-in circuit and a read-out/restoration circuit for the memristor-based multilevel memory, in which a memristor can be used as a multilevel memory. In the... Agent:
20110182109 - Variable resistance nonvolatile memory device and programming method for same: A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are... Agent:
20110182111 - Electromechanical switch and method of forming the same: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the... Agent:
20110182110 - Semiconductor memory device and driving method thereof: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110182112 - 10t sram cell with near dual port functionality: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which... Agent: Texas Instruments Incorporated
20110182115 - Method for fabricating indium (in)-antimony (sb)-tellurium (te) nanowires and phase-change memory device comprising the nanowires: Disclosed herein is a method for manufacturing (In)—(Sb)—(Te) (IST) nanowires and a phase-change memory device comprising the nanowires. The method comprises providing a substrate and vapors of In, Sb and Te precursors in a chamber and allowing the vapors to react with each other on the substrate in the chamber... Agent: The Industry & Academic Cooperation In Chungnam National University (iac)
20110182113 - Semiconductor memory device: A semiconductor memory device prevents a faulty operation of a program operation, and increases the reliability of operation. The semiconductor memory device includes a unit cell including a memory element configured to have a different resistance value in response to data, and a write driver configured to output a program... Agent: Hynix Semiconductor Inc.
20110182114 - Semiconductor memory device and control method thereof: A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and... Agent: Hynix Semiconductor Inc.
20110182117 - Method of programming nonvolatile semiconductor memory device: A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This... Agent:
20110182119 - Apparatus, system, and method for determining a read voltage threshold for solid-state storage media: An apparatus, system, and method are disclosed for determining a read voltage threshold for solid-state storage media. A data set read module reads a data set from storage cells of solid-state storage media. The data set is originally stored in the storage cells with a known bias. A deviation module... Agent: Fusion-io, Inc.
20110182120 - Non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation... Agent: Samsung Electronics Co., Ltd.
20110182121 - Data recovery for non-volatile memory based on count of data state-specific fails: An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements.... Agent:
20110182122 - Dynamic soft program trims: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory... Agent: Micron Technology, Inc.
20110182118 - Adaptive dynamic reading of flash memories: Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two... Agent: Ramot At Tel Aviv University Ltd.
20110182116 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a... Agent:
20110182123 - Flash memory and manufacturing method and operating method thereof: A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure... Agent: Macronix International Co., Ltd.
20110182124 - Non-volatile memory low voltage and high speed erasure method: A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage... Agent: Yield Microelectronics Corp.
20110182126 - Flash memory array of floating gate-based non-volatile memory cells: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of... Agent: Intersil Americas Inc.
20110182125 - Semiconductor memory device, semiconductor device, and method of data erase in the semiconductor memory device: A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of... Agent: Kabushiki Kaisha Toshiba
20110182127 - Semiconductor integrated circuit device: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit... Agent: Renesas Electronics Corporation
20110182128 - Asynchronous/synchronous interface: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on... Agent: Micron Technology, Inc.
20110182130 - Low current wide vref range input buffer: A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.... Agent: Round Rock Research, LLC
20110182129 - Sense amplifier having loop gain control: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive... Agent: Micron Technology, Inc.
20110182131 - Semiconductor device including internal voltage generation circuit: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is... Agent: Renesas Electronics Corporation07/21/2011 > 37 patent applications in 22 patent subcategories. category listing
20110176345 - Electronic apparatus: An electronic apparatus is provided. A PCB has first and second signal paths therein. First and second fingers are disposed on the first and second signal paths, respectively. A controller is coupled to a first memory via the first finger and a second memory via the second finger, and accesses... Agent: Mediatek Inc.
20110176346 - Semiconductor memory device: According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host... Agent: Kabushiki Kaisha Toshiba
20110176349 - Low-cost high-density rectifier matrix memory: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.... Agent:
20110176348 - Semiconductor device: An object is to provide a semiconductor device in which stored data can be retained even when power is not supplied, and there is no limitation on the number of write cycles. The semiconductor device includes a source line, a bit line, a first signal line, a second signal line,... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110176347 - Semiconductor integrated circuit including semiconductor memory: According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array,... Agent:
20110176353 - Memristive device having a porous dopant diffusion element: A memristive device (400) includes: a first electrode (405); a second electrode (425); a memristive matrix (415) interposed between the first electrode (405) and the second electrode (425); a porous dopant diffusion element (410) in physical contact with the memristive matrix (415) and in proximity to the first electrode (405)... Agent:
20110176352 - Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material: A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material,... Agent:
20110176351 - Nonvolatile memory device and method for manufacturing same: According to one embodiment, a nonvolatile memory device includes a memory layer and a control unit. The memory layer includes a first conductive layer, a second conductive layer and a resistance change layer. The resistance change layer is provided between the first and second conductive layers and transits between a... Agent: Kabushiki Kaisha Toshiba
20110176350 - Resistance-based memory with reduced voltage input/output device: A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor... Agent: Industry-academic Cooperation Foundation, Yonsei University
20110176354 - Semiconductor device: An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line,... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110176356 - Semiconductor device and data processing system: A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit... Agent: Elpida Memory Inc.
20110176355 - Semiconductor device and driving method thereof: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110176357 - Signal processing circuit and method for driving the same: It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110176358 - Reading phase change memories: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to... Agent: Ovonyx, Inc.
20110176359 - Carbon nanotube-based neural networks and methods of making and using same: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the... Agent: Nantero, Inc.
20110176360 - Magnetic random access memory (mram) utilizing magnetic flip-flop structures: Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable... Agent: Seagate Technology LLC
20110176363 - Junction leakage suppression in memory devices: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a... Agent: Spansion LLC
20110176361 - Method and apparatus for increasing memory programming efficiency through dynamic switching of bit lines: A method of efficiently programming charge-trapping memory cells includes sense amplifiers being dynamically connected to cells to be programmed, by switching bit lines. The method increases a number of cells that can be programmed simultaneously, such that an optimal use of sense amplifier resources is obtained.... Agent:
20110176362 - Semiconductor storage device capable of reducing erasure time: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is... Agent:
20110176364 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units... Agent:
20110176365 - Two terminal programmable hot channel electron non-volatile memory: A programmable two terminal non-volatile device uses a floating gate that can be programmed by a hot electron injection induced by a potential between a source and drain. The floating gate layer can also function as a FET gate for other circuits in an integrated circuit containing an array of... Agent:
20110176367 - Nonvolatile semiconductor memory device and operation method thereof: A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the... Agent: Kabushiki Kaisha Toshiba
20110176366 - Semiconductor storage device and reading method thereof: An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common... Agent: Kabushiki Kaisha Toshiba
20110176368 - Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for a general purpose cmos technology with thick gate oxide: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The... Agent: Intersil Americas Inc.
20110176369 - Erase verification method of flash memory apparatus: A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns... Agent: Elite Semiconductor Memory Technology Inc.
20110176370 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory comprises a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected... Agent: Kabushiki Kaisha Toshiba
20110176372 - Memory interface: The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable... Agent: Panasonic Corporation
20110176371 - Memory module including memory buffer and memory system having the same: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on... Agent:
20110176373 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a... Agent: Kabushiki Kaisha Toshiba
20110176374 - Bist ddr memory interface circuit and method for testing the same: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test... Agent: Texas Instruments Incorporated
20110176376 - Low power synchronous memory command address scheme: A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a... Agent:
20110176375 - Semiconductor memory device for reducing ripple noise of back-bias voltage and method of driving semiconductor memory device: A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first... Agent: Samsung Electronics Co., Ltd.
20110176377 - Semiconductor memory device: A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110176378 - Memory program discharge circuit: A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.... Agent: Macronix International Co., Ltd.
20110176379 - Semiconductor memory device having memory cell array of open bit line type and control method thereof: A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a... Agent:
20110176381 - Memory having a disabling circuit and method for disabling the memory: A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the... Agent:
20110176380 - Paired programmable fuses: A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the... Agent: International Business Machines Corporation07/14/2011 > 42 patent applications in 28 patent subcategories. category listing
20110170327 - Devices and methods for comparing data in a content-addressable memory: The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to... Agent:
20110170328 - Semiconductor memory device: A semiconductor memory device according to the present invention includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in... Agent:
20110170330 - Graphene memory cell and fabrication methods thereof: The disclosed memory cell (10) comprises a graphene layer (16) having controllable resistance states representing data values of the memory cell (10) In one exemplary embodiment a non-volatile memory is provided by having a ferroelectric layer (18) control the resistance states. In the exemplary embodiment, binary ‘0’s and ‘1’s are... Agent: National University Of Singapore
20110170329 - Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line,... Agent:
20110170333 - Data read/write device: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two... Agent:
20110170332 - Methods of driving nonvolatile memory devices that utilize read/write merge circuits: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write... Agent:
20110170334 - Nonvolatile memory, memory system, and method of driving: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a... Agent: Samsung Electronics Co., Ltd.
20110170331 - Semiconductor devices and methods of driving the same: Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch... Agent:
20110170335 - Vertical non-volatile switch with punchthrough access and method of fabrication therefor: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to... Agent: Seagate Technology LLC
20110170336 - Dram device and manufacturing method thereof: The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word... Agent:
20110170337 - Transistor with reduced charge carrier mobility and associated methods: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower... Agent:
20110170339 - Magnetoresistive device: A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric... Agent:
20110170338 - System and method to control a direction of a current applied to a magnetic tunnel junction: A system and method to control a direction of a current applied to a magnetic tunnel junction is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier. The sense amplifier is coupled to a first path and to a second... Agent: Qualcomm Incorporated
20110170342 - Electronic devices utilizing spin torque transfer to flip magnetic orientation: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing... Agent: Seagate Technology LLC
20110170341 - Method and system for providing magnetic tunneling junctions usable in spin transfer torque magnetic memories: A method and system for providing a magnetic junction are described. The method and system include providing a free layer, a symmetry filter, and a pinned layer. The free layer has a first magnetic moment switchable between stable states when a write current is passed through the magnetic junction. The... Agent:
20110170340 - Read direction for spin-torque based memory device: A spin-torque based memory device includes a plurality of magnetic storage cells in an array, each magnetic storage cell includes at least one magnetic tunnel junction (MTJ) element, and at least one bit line and at least one bit complement line corresponding to the plurality of magnetic storage cells. Each... Agent: International Business Machines Corporation
20110170343 - Dram memory cell having a vertical bipolar injector: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar... Agent:
20110170344 - Semiconductor device including sub word line driver: A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A... Agent:
20110170345 - Methods, devices, and systems relating to memory cells having a floating body: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate... Agent: Micron Technology, Inc.
20110170348 - Analog interface for a flash memory die: A flash disk controller includes an input operable to receive analog signals from a flash memory die. The flash memory die includes multiple flash memory cells. The analog signals represent data values stored in the flash memory cells. An analog-to-digital conversion module is coupled to the input to convert received... Agent: Apple Inc.
20110170347 - Semiconductor memory device capable of accurate reading even when erasure level changes: According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are... Agent:
20110170349 - Drift compensation in a flash memory: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds... Agent:
20110170350 - Semiconductor memory device capable of increasing writing speed: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit... Agent:
20110170351 - Memory cell array of memory: A memory cell array of a memory comprises a main memory cell array, including local bit lines, word lines and memory cells, and a selected array, including a global bit line, a bit line transistor (BLT) control line, a transistor and a fixed value memory cell. The local bit lines... Agent: Macronix International Co., Ltd.
20110170352 - Nand flash memory having multiple cell substrates: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during... Agent: Mosaid Technologies Incorporated
20110170353 - Access line dependent biasing schemes: The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the... Agent: Micron Technology, Inc.
20110170354 - Method and system to access memory: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in... Agent: Atmel Corporation
20110170356 - Methods of programming data in a non-volatile memory device and methods of operating a nand flash memory device using the same: Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed... Agent:
20110170357 - Nonvolatile memory with a unified cell structure: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,... Agent: Abedneja Assets Ag L.L.C.
20110170355 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent:
20110170358 - Programming non-volatile storage with fast bit detection and verify skip: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one... Agent:
20110170359 - Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line... Agent: Micron Technology, Inc.
20110170346 - Non-volatile semiconductor memory device, signal processing system, method for controlling signal processing system, and method for reprogramming non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array including a data storage area and a reprogram information storage area, and a reprogram information holder circuit configured to store data read from the reprogram information storage area. A reference level switch circuit selects one from a plurality of read... Agent: Panasonic Corporation
20110170360 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device comprises a bit line voltage set-up step of receiving a program command and data to be programmed and setting up a voltage of a selected bit line according to a state of program data; a program step of supplying a program voltage... Agent:
20110170361 - Electronic device comprising non volatile memory cells and corresponding programming method: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first... Agent:
20110170362 - Semiconductor integrated circuit: Disclosed is a semiconductor integrated circuit in which the number of bus lines is reduced and current consumption during operation can be lessened. The semiconductor integrated circuit includes a circuit unit (e.g., a memory cell array plate) which is divided into a plurality of banks (bank 1, bank 2) and... Agent: Renesas Electronics Corporation
20110170363 - Bit line precharge voltage generation circuit for semiconductor memory apparatus: Various embodiments of a bit line precharge voltage generation circuit for a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a bit line precharge voltage generation circuit may include a voltage division block for dividing an internal voltage to generate a first division voltage and a second division voltage,... Agent: Hynix Semiconductor Inc.
20110170364 - Capacitor-less memory cell, device, system and method of making same: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line.... Agent: Micron Technology, Inc.
20110170365 - Row addressing: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row... Agent: Micron Technology, Inc.
20110170366 - Temperature detector in an integrated circuit: A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function... Agent: Mosaid Technologies Incorporated
20110170367 - Dynamic random access memory with fully independent partial array refresh function: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing.... Agent: Mosaid Technologies Incorporated
20110170368 - Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump: Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a... Agent: International Business Machines Corporation07/07/2011 > 21 patent applications in 16 patent subcategories. category listing
20110164444 - Resistance change memory: According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance... Agent:
20110164445 - Semiconductor memory device including plurality of memory chips: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a... Agent: Samsung Electronics Co., Ltd.
20110164446 - Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the... Agent: Micron Technology, Inc.
20110164447 - Current steering element, storage element, storage device, and method for manufacturing current steering element: A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance... Agent:
20110164448 - Tunneling magnetoresistance (tmr) device, its manufacture method, magnetic head and magnetic memory using tmr device: A barrier layer is disposed over a pinned layer made of ferromagnetic material having a fixed magnetization direction, the barrier layer having a thickness allowing electrons to transmit therethrough by a tunneling phenomenon. A first free layer is disposed over the barrier layer, the first free layer being made of... Agent: Fujitsu Limited
20110164449 - Programming based on controller performance requirements: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual... Agent: Micron Technology, Inc.
20110164450 - Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated... Agent: Unity Semiconductor Corporation
20110164451 - Semiconductor integrated circuit including programmable fuse: A semiconductor integrated circuit comprises a plurality of fuses arranged to be spaced apart from one another by predetermined intervals, and a page buffer electrically connected to the plurality of fuses and configured to determine whether to disconnect the fuses. The fuses comprise a NAND flash string. The NAND flash... Agent: Hynix Semiconductor Inc.
20110164452 - Memory device: Systems (100) and methods (600) for reading data from a memory device (106). The methods involve (606) receiving first read request signals (118, 120, 122, 126, 128) for first data stored in the memory device. In response to the first read request signals, (608) retrieving a first page of data... Agent: Spansion LLC
20110164453 - System and memory for sequential multi-plane page memory operations: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the... Agent: Round Rock Research, LLC
20110164455 - Memory cell operation: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the... Agent: Micron Technology, Inc.
20110164457 - Method of operating nonvolatile memory device: Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase... Agent:
20110164456 - Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage: Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less... Agent: Micron Technology, Inc.
20110164454 - Nonvolatile memory device, operating method thereof, and memory system including the same: A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number... Agent: Samsung Electronics Co., Ltd.
20110164458 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent:
20110164459 - List structure control circuit: A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for... Agent: Fujitsu Limited
20110164460 - Semiconductor device and method of controlling the same: A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the... Agent: Elpida Memory, Inc.
20110164461 - Memory device: A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.... Agent: Macronix International Co., Ltd.
20110164462 - Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay... Agent:
20110164463 - Structure and method for decoding read data-bus with column-steering redundancy: A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when... Agent: International Business Machines Corporation
20110164464 - Semiconductor memory device and method of testing the same: A semiconductor device includes the following elements. A sense amplifier amplifies signal on a bit line. A column switch is between the bit line and a local input-output line. A sub-amplifier amplifies signal on the local input-output line. A write switch is between the local input-output line and a main... Agent: Elpida Memory, Inc.Previous industry: Electric power conversion systems
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