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Static information storage and retrieval June invention type 06/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
06/30/2011 > patent applications in patent subcategories. invention type

20110157951 - 3d chip selection for shared input packages: A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the... Agent: Marconix International Co., Ltd.

20110157950 - Memory chips and judgement circuits thereof: A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indicates which mode the memory... Agent:

20110157953 - Memory device having data paths: Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between... Agent: Micron Technology, Inc.

20110157952 - Semiconductor memory device having improved voltage transmission path and driving method thereof: Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the... Agent:

20110157954 - Sram memory device: An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input... Agent: Stmicroelectronics S.r.l.

20110157955 - Magnetic shift register memory: A magnetic shift register memory includes a magnetic track and a reference magnetic region. The magnetic track has multiple magnetic domains. Each of the magnetic domains stores one bit data. One end of the magnetic domains is set with a first data injection domain for storing a first data, and... Agent: Industrial Technology Research Institute

20110157956 - Method and apparatus for increasing yield: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific... Agent:

20110157960 - Nonvolatile memory devices and related methods and systems: Nonvolatile memory devices are provided including a memory cell array having a plurality of stacked memory layers and a rectifier configured to select memory cells constituting each memory layer sharing a word line or a bit line with another adjacent memory layer. The nonvolatile memory devices including a word line... Agent:

20110157957 - Nonvolatile semiconductor integrated circuit for controlling sensing voltage: A nonvolatile semiconductor integrated circuit includes a memory cell array configured to include each of memory cells having a variable resistor; a current sensing unit configured to convert a current which depends on the variable resistor of a corresponding memory cell, into a sensing voltage; and a voltage control unit... Agent: Hynix Semiconductor Inc.

20110157958 - Semiconductor memory device and method of operating the same: According to one embodiment, a semiconductor memory device comprises a memory cell array and a control circuit. The control circuit applies a certain potential difference to a selected one of the memory cells. The control circuit comprises a current mirror circuit, a reference current generating circuit, and a detecting circuit.... Agent: Kabushiki Kaisha Toshiba

20110157959 - Semiconductor storage device, memory cell array, and a fabrication method and drive method of a semiconductor storage device: A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode (106) is formed to sandwich an insulating film (105) with a p-type semiconductor region (102). A first n-type semiconductor region (103) and a second n-type... Agent:

20110157962 - Bias sensing in dram sense amplifiers through voltage-coupling/decoupling device: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time... Agent: Micron Technology, Inc.

20110157961 - Semiconductor device: The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110157964 - Memory cell using leakage current storage mechanism: A memory cell comprises a storage element including a transistor and an inverter. The inverter has an input coupled to a first source/drain of the transistor at a first node and has an output coupled to a gate of the transistor at a second node. The transistor has a second... Agent:

20110157965 - Semiconductor device: The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in... Agent: Renesas Electronics Corporation

20110157963 - Sram word-line coupling noise restriction: A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows.... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20110157967 - Magnetic random access memory, method of initializing magnetic random access memory and method of writing magnetic random access memory: A magnetic memory includes a magnetization recording layer, a first terminal, a second terminal, a magnetization pinned layer and a non-magnetic layer. The magnetization recording layer has a vertical magnetic anisotropy and includes a ferromagnetic layer. The first terminal is connected to one end of a first region in the... Agent: Nec Corporation

20110157966 - Nonvolatile memory device: A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line.... Agent: Hynix Semiconductor Inc.

20110157970 - Phase change memory that switches between crystalline phases: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change... Agent:

20110157969 - Semiconductor memory apparatus, and circuit and method for controlling faulty address therein: A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based... Agent: Hynix Semiconductor Inc.

20110157968 - Semiconductor memory device: A semiconductor memory device measures a leakage current generated when a unit cell is accessed during a test process. The semiconductor memory device includes a unit cell configured to include a memory element, a word line configured to be coupled to one end of the unit cell, and a bit... Agent: Hynix Semiconductor Inc.

20110157971 - Magnetic random access memories and methods of operating the same: A spin transfer torque magnetic random access memory (STT-MRAM) and includes: a memory cell and a reference cell configured to operate as a reference when data stored in the memory cell is read. The memory cell includes: a first magnetic tunneling junction (MTJ) element and a first transistor connected to... Agent: Samsung Electronics Co., Ltd.

20110157973 - Non-volatile semiconductor memory device capable of preventing over-programming: According to one embodiment, a semiconductor memory device includes a memory cell array, a data memory circuit, a power generation circuit, and a controller. In the memory cell array, a plurality of memory cells which store two-or-more-bit data are arrayed in a matrix. When data is written to all memory... Agent:

20110157978 - Nonvolatile semiconductor memory device and method of reading data from nonvolatile semiconductor memory device: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application... Agent: Elpida Memory, Inc.

20110157981 - Flash memory system having cross-coupling compensation during read operation: A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell.... Agent:

20110157982 - Novel high speed high density nand-based 2t-nor flash memory design: A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor... Agent:

20110157983 - Semiconductor memory device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory... Agent:

20110157980 - Technique to reduce fg-fg interference in multi bit nand flash memory in case of adjacent pages not fully programmed: A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that... Agent:

20110157984 - Block decoder of semiconductor memory device: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node... Agent: Hynix Semiconductor Inc.

20110157986 - Memory and operating method thereof: A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could... Agent: Macronix International Co., Ltd.

20110157987 - Non-volatile memory with redundancy data buffered in remote buffer circuits: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has... Agent:

20110157985 - Nonvolatile semiconductor memory device: A semiconductor memory device includes a memory region including memory cells configured to store data, a redundant region including memory cells configured to store data, and a control unit. The control unit is responsive to an erase command to execute, prior to an erase operation corresponding to the erase command,... Agent: Samsung Electronics Co., Ltd.

20110157972 - Ftp memory device programmable and erasable at cell level: An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of... Agent: Stmicroelectronics S.r.l.

20110157988 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory blocks each comprising a plurality of memory cells formed over a semiconductor substrate having a P well, a first voltage generator supplying operating voltages to an selected block of the memory blocks, and a second voltage generator generating a negative voltage to the P... Agent: Hynix Semiconductor Inc.

20110157990 - Control device for nonvolatile memory and method of operating control device: A device comprises a nonvolatile memory cell array, a buffer circuit, a program control circuit, and a read control circuit. The nonvolatile memory cell array comprises a plurality of memory cells. The program control circuit stores program data in the buffer circuit. The read control circuit reads data from a... Agent: Samsung Electronics Co., Ltd.

20110157989 - Non-volatile semiconductor memory device and semiconductor device: A control circuit is configured to erase a selected block in the erase operation by applying a predetermined potential to the source-line and the third conductive layer to generate a current to increase a potential of the first columnar semiconductor layer and by providing a first voltage to the first... Agent: Kabushiki Kaisha Toshiba

20110157992 - Apparatus, system, and method for biasing data in a solid-state storage device: An apparatus, system, and method are disclosed for improving performance in a non-volatile solid-state storage device. Non-volatile solid-state storage media includes a plurality of storage cells. The plurality of storage cells is configured such that storage cells in an empty state store initial binary values that satisfy a bias. An... Agent: Fusion-io, Inc.

20110157991 - Eeprom device: A stable and reliable EEPROM device includes an EEPROM cell having first, second and third control voltage terminals for performing operations for programming, reading and erasing data, respectively, a first transistor configured to supply a programming operation voltage to the first control voltage terminal during the programming operation, a second... Agent:

20110157994 - Nand-type flash memory and nand-type flash memory controlling method: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of... Agent: Kabushiki Kaisha Toshiba

20110157993 - Semiconductor memory device and read method thereof: A read method using a semiconductor memory device includes reading data of a cell adjacent to a cell to be read and storing the data in a first latch of a first page buffer, sending the data, stored in the first latch, to a second latch of a second page... Agent: Hynix Semiconductor Inc.

20110157995 - Nand memory programming method using double vinhibit ramp for improved program disturb: A method of applying an inhibit bias to an unselected word line when programming a NAND memory device is provided. The method may include ramping the inhibit bias to the unselected word line to a first predetermined voltage and ramping the inhibit bias to the unselected word line to a... Agent:

20110157975 - Ftp memory device with programing and erasing based on fowler-nordheim effect: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a... Agent: Stmicroelectronics S.r.i.

20110157977 - Ftp memory device with single selection transistor: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of... Agent: Stmicroelectronics S.r.l.

20110157974 - Novel cell array for highly-scalable , byte-alterable, two-transistor flotox eeprom non-volatile memory: Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with... Agent: Aplus Flash Technology, Inc.

20110157979 - Semiconductor memory device, method of manufacturing the same, and cell array of semiconductor memory device: A semiconductor memory device, a method of manufacturing the same, and a cell array of a semiconductor memory device are provided. The semiconductor memory device includes: a first gate insulation layer and a second gate insulation layer, being spaced a predetermined distance from each other, on a portion of a... Agent: Dongbu Hitek Co., Ltd.

20110157976 - Voltage stabilization device and semiconductor device including the same, and voltage generation method: Integrated circuit memory devices include multiple voltage regulators configured to generate respective boosted voltages, which are provided to a memory cell block. A first voltage regulator is configured to increase a well voltage (Vwell) from a first level to an elevated second level during a pull-up time interval when a... Agent:

20110157996 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and... Agent:

20110157999 - Method of operating semiconductor memory device: A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and... Agent: Hynix Semiconductor Inc.

20110157997 - Non-volatile semiconductor memory device, method of reading data therefrom, and semiconductor device: A control circuit is configured to performs, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation... Agent: Kabushiki Kaisha Toshiba

20110158001 - Programming method for nonvolatile memory device: A programming method for a nonvolatile memory device includes inputting least significant bit (LSB) data and most significant bit (MSB) data to each of different latches of a page buffer and in the state in which the LSB data and the MSB data have been inputted to the page buffer,... Agent: Hynix Semiconductor Inc.

20110157998 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device comprises performing a third program such that threshold voltages of third memory cells, from among memory cells of a selected page, are higher than a third level, after the third program loop is completed, performing a second program loop such that threshold... Agent: Hynix Semiconductor Inc.

20110158000 - Semiconductor memory device and method of programming the same: A semiconductor memory device includes a voltage generator configured to supply a program voltage, a sub-verification voltage, or a target verification voltage to memory cells selected during a program operation, page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with... Agent:

20110158002 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory string coupled between a common source line and a bit line, a page buffer configured to supply a first precharge voltage to the bit line and to latch data corresponding to a threshold voltage level of a memory cell of the memory string,... Agent:

20110158003 - Method of erasing memory cell: An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well... Agent: Micron Technology, Inc.

20110158004 - Semiconductor device capable of detecting defect of column selection line: To include a comparison circuit that generates comparison results by comparing plural pieces of data simultaneously read via data lines with expected values, an AND gate that activates a first determination signal in response to a fact that at least one of the comparison results indicates a mismatch, and an... Agent: Elpida Memory, Inc.

20110158005 - Data access apparatus and associated method for accessing data using internally generated clocks: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching... Agent: Mstar Semiconductor, Inc.

20110158006 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data... Agent: Kabushiki Kaisha Toshiba

20110158007 - Multi-power domain design: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110158008 - Semiconductor storage device and data readout method: According to one embodiment, in a semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the... Agent: Kabushiki Kaisha Toshiba

20110158009 - Apparatus for generating output data strobe signal: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to... Agent:

20110158011 - Semiconductor memory interface device and method: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and... Agent:

20110158010 - Skew detector and semiconductor memory device using the same: A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation... Agent:

20110158013 - Fuse set of semiconductor memory and repair determination circuit using the same: A fuse set of a semiconductor memory includes a first fuse array and a second fuse array each configured to designate a column redundancy address; and a unit fuse circuit configured to select one of the first fuse array and the second fuse array based on a row address.... Agent: Hynix Semiconductor Inc.

20110158012 - Semiconductor memory device having redundancy circuit for repairing defective unit cell: A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second... Agent:

20110158014 - Burst address generator and test apparatus including the same: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased... Agent:

20110158015 - Device and method for generating test mode signal: A test mode signal generation device includes a pulse address generation unit configured to convert test address signals into pulse signals and generate pulse address signals, a pulse address split unit configured to generate converted test address signals in response to the pulse address signals, and a test mode signal... Agent: Hynix Semiconductor Inc.

20110158016 - Integrated solution for identifying malfunctioning components within memory devices: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells... Agent: Stmicroelectronics S.r.i.

20110158017 - Method for memory cell characterization using universal structure: A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals,... Agent: Texas Instruments Incorporated

20110158018 - Structure and methods for measuring margins in an sram bit: Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array... Agent: Texas Instruments Incorporated

20110158020 - Circuit and method for controlling precharge in semiconductor memory apparatus: A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal,... Agent: Hynix Semiconductor Inc.

20110158021 - Reducing peak currents required for precharging data lines in memory devices: A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a... Agent: Arm Limited

20110158019 - Semiconductor memory device and operation method thereof: A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The semiconductor memory device includes a power source supplier configured to supply a power source of a main... Agent:

20110158022 - Semiconductor memory device having a reduced noise interference: A semiconductor memory device having a reduced noise interference is presented. The semiconductor memory device includes a first switch and a second switch. The first switch is disposed in a sub hole region or an edge region and is configured to be turned on in response to a first pre-control... Agent: Hynix Semiconductor Inc.

20110158023 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit... Agent:

20110158024 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring... Agent:

20110158026 - Fuse circuit and control method thereof: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.... Agent: Hynix Semiconductor Inc.

20110158025 - Semiconductor device and method for operating the same: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring... Agent:

20110158027 - Regulator circuit and semiconductor memory device including the same: A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and... Agent: Hynix Semiconductor Inc.

20110158028 - Block decoder of semiconductor memory device: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal and a block selection signal generation circuit configured to generate a block... Agent: Hynix Semiconductor Inc.

20110158029 - Word line driving circuit and semiconductor storage device: According to one embodiment, a word line driving circuit includes a driver and a booster circuit. The driver drives a word line based on an output of an inverter. The booster circuit connects a boosting capacitor to a source side of a P-channel field effect transistor of the inverter to... Agent: Kabushiki Kaisha Toshiba

20110158030 - Method and apparatus for tuning phase of clock signal: A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency... Agent: Samsung Electronics Co., Ltd.

20110158031 - Signal calibration methods and apparatuses: In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal... Agent:

20110158032 - Clock control circuit and clock generation circuit including the same: A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined... Agent: Hynix Semiconductor Inc.

20110158033 - Semiconductor memory device: A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured... Agent:

  
06/23/2011 > patent applications in patent subcategories. invention type

20110149627 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device comprises a voltage detector for generating a detection signal when the external power supply voltage is higher than a set voltage and memory chips, each comprising a memory cell unit and a content-addressable memory (CAM) cell unit and performing internal operations in response to the detection... Agent:

20110149628 - Programming phase change memories using ovonic threshold switches: A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.... Agent:

20110149629 - Semiconductor memory apparatus and method of operating the same: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block... Agent: Hynix Semiconductor Inc.

20110149630 - High read speed electronic memory with serial array transistors: Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of... Agent: Spansion LLC

20110149631 - Rewritable memory device with multi-level, write-once memory cells: The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device... Agent:

20110149632 - Multilevel frequency addressable field driven mram: A three-dimensional nonvolatile memory array device includes a plurality of memory elements and a memory controller. The plurality of memory elements each have a stack of a plurality of bits, which in turn each include a magnetic free layer, a magnetic pinned layer, and a non-magnetic layer. The magnetic free... Agent:

20110149633 - Memory devices and methods of operating the same: Memory devices and methods of operating the same. A memory cell of a memory device may include a ferroelectric layer and a semiconductor layer bonded to each other. The ferroelectric layer may be of a p-type and the semiconductor layer may be of an n-type. The memory cell may have... Agent: Samsung Electronics Co., Ltd.

20110149636 - Ion barrier cap: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide... Agent: Unity Semiconductor Corporation

20110149637 - Method and apparatus providing high density chalcogenide-based data storage: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material... Agent: Micron Technology, Inc.

20110149639 - Non-volatile memory cell with multiple resistive sense elements sharing a common switching device: A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an... Agent: Seagate Technology LLC

20110149634 - Non-volatile memory device ion barrier: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide... Agent: Unity Semiconductor Corporation

20110149638 - Nonvolatile memory device and information recording method: According to one embodiment, a nonvolatile memory device includes a memory layer and a driver section. The memory layer has a first state having a first resistance under application of a first voltage, a second state having a second resistance higher than the first resistance under application of a second... Agent: Kabushiki Kaisha Toshiba

20110149635 - Storage device and information rerecording method: A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for... Agent: Sony Corporation

20110149640 - Magnetic storage device: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected... Agent: Kabushiki Kaisha Toshiba

20110149641 - Static magnetic field assisted resistive sense element: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to... Agent: Seagate Technology LLC

20110149642 - Static magnetic field assisted resistive sense element: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to... Agent: Seagate Technology LLC

20110149645 - Multi-level programmable pcram memory: A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to provide a memory device having three or more discrete resistance levels, and thus three or more discrete logic levels. The non-volatile memory may form part of... Agent:

20110149643 - Phase change memory apparatus having global bit line and method for driving the same: A phase change memory apparatus includes a global bit line and an internal power generation circuit. The global bit line is configured to integratedly control a plurality of bit lines. The internal power generation circuit is configured to supply an internal voltage while the global bit line is discharged and... Agent: Hynix Semiconductor Inc.

20110149644 - Voltage control circuit for phase change memory: The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change... Agent: Nxp B.v.

20110149647 - Perpendicular magnetic tunnel junctions, magnetic devices including the same and method of manufacturing a perpendicular magnetic tunnel junction: Provided are a perpendicular magnetic tunnel junction (MTJ), a magnetic device including the same, and a method of manufacturing the MTJ, the perpendicular MTJ includes a lower magnetic layer; a tunnelling layer on the lower magnetic layer; and an upper magnetic layer on the tunnelling layer. One of the upper... Agent: Korean Advanced Institute Of Science And Technology

20110149648 - Programmable device: A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is... Agent: International Business Machines Corporation

20110149646 - Transient heat assisted sttram cell for lower programming current: A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the... Agent: Micron Technology, Inc.

20110149649 - Magnetic memory devices and methods of operating the same: A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past... Agent: Samsung Electronics Co., Ltd.

20110149650 - Data transfer flows for on-chip folding: A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a... Agent:

20110149651 - Non-volatile memory and method with atomic program sequence and write abort detection: A program operation in a non-volatile memory is segmented at predefined junctures into smaller segments for execution over different times. The predefined junctures are such that they allow unambiguous identification when restarting the operation in a next segment so that the operation can continue without having to restart from the... Agent:

20110149653 - Nand flash memory: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and... Agent: Kabushiki Kaisha Toshiba

20110149652 - Semiconductor memory device and method of operating the same: A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines... Agent:

20110149654 - Nand programming technique: A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be... Agent:

20110149655 - Non-volatile memory cell array: A non-volatile microelectronic memory that has a memory cell array, which includes memory cell string pairs that share a bitline contact, that have separate source lines, and that have at least two transistors within each memory cell string that may be programming for sharing the bitline contact.... Agent:

20110149658 - Method, apparatus, and system for improved read operation in memory: Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline... Agent:

20110149657 - Methods and apparatus for write-side intercell interference mitigation in flash memories: Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell... Agent:

20110149656 - Multi-cell vertical memory nodes: Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes,... Agent:

20110149659 - Erase operations and apparatus for a memory device: Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the... Agent: Micron Technology, Inc.

20110149660 - Sensing for memory read and program verify operations in a non-volatile memory device: Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the... Agent: Micron Technology, Inc.

20110149661 - Memory array having extended write operation: In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows... Agent:

20110149662 - Memory device and method of writing data to a memory device: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write... Agent: Stmicroelectronics Pvt. Ltd.

20110149663 - Semiconductor device and semiconductor memory device: A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively... Agent: Elpida Memory, Inc.

20110149665 - Circuit for controlling redundancy in semiconductor memory apparatus: Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral... Agent: Hynix Semiconductor Inc.

20110149664 - Word line block/select circuit with repair address decision unit: A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control... Agent: Hynix Semiconductor Inc.

20110149666 - Bitline floating during non-access mode for memory arrays: Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating... Agent:

20110149668 - Memory device and method of operation thereof: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be... Agent: Stmicroelectronics Pvt. Ltd.

20110149667 - Reduced area memory array by using sense amplifier as write driver: Techniques are disclosed for reducing area needed for implementing a memory array, such as SRAM arrays. The techniques may be embodied, for example, in a memory array design that includes a sense amplifier configured to operate in a reading mode for readout of memory cells and a writing mode for... Agent:

20110149669 - Sense amplifier and data sensing method thereof: A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a... Agent: Macronix International Co., Ltd.

20110149670 - Spin valve device including graphene, method of manufacturing the same, and magnetic device including the spin valve device: Provided are a spin valve device including graphene, a method of manufacturing the spin valve device, and a magnetic device including the spin valve device. The spin valve device may include at least one of a graphene sheet or a hexagonal boron nitride (h-BN) sheet between a lower magnetic layer... Agent: Samsung Electronics Co., Ltd.

20110149671 - Operation method and leakage controller for a memory and a memory applying the same: An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the... Agent: Macronix International Co., Ltd.

20110149672 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes: a circuit required to be in a data retaining state; a data retention characteristic evaluation circuit configured to measure the data retaining state of the circuit; a leakage current evaluation circuit configured to measure the leakage current in the circuit; a voltage control signal... Agent: Panasonic Corporation

20110149673 - Three state word line driver fora dram memory device: A memory bank includes an array of memory cells, word lines for accessing the memory cells, and word line drivers coupled to the word lines. When the memory bank is being accessed, the word line drivers are coupled to receive a first supply voltage, which is applied to the non-selected... Agent: Mosys, Inc.

20110149674 - Integrated circuit memory with word line driving helper circuits: An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line... Agent:

20110149675 - Local word line driver: A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from... Agent: Macronix International Co., Ltd.

  
06/16/2011 > patent applications in patent subcategories. invention type

20110141789 - Memory module and memory system: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal,... Agent: Elpida Memory, Inc.

20110141788 - Page register outside array and sense amplifier interface: A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register... Agent:

20110141790 - Memory module having high data processing rate: A memory module having a high data processing rate and high capacity is provided. The memory module may include a memory chip, a controller controlling an operation of the memory chip, an optical detector converting an external input signal into an internal input signal to transmit the converted signal to... Agent:

20110141791 - System and method to control one time programmable memory: A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random... Agent: Sigmatel, Inc.

20110141792 - Read/write structures for a three dimensional memory: Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer is able to store bits of data in the form of magnetic domains.... Agent:

20110141793 - Semiconductor memory device: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided... Agent: Kabushiki Kaisha Toshiba

20110141794 - Semiconductor memory device and inspecting method of the same: According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for... Agent:

20110141795 - Multi-port memory based on dram core: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.... Agent: Fujitsu Semiconductor Limited

20110141797 - Creating spin-transfer torque in oscillators and memories: A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of... Agent:

20110141796 - Magnetic tunnel junction device and fabrication: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and... Agent: Qualcomm Incorporated

20110141798 - Amorphous semiconductor threshold switch volatile memory cell: A voltage memory switch may be formed of an amorphous semiconductor threshold switch and a select device. The amorphous threshold switch may be latched into one of two different current conducting levels. Then, in some embodiments, a relatively dense memory array can be achieved by maintaining an appropriate bias on... Agent:

20110141800 - Phase-change memory device: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal,... Agent:

20110141799 - Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming: A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation.... Agent:

20110141801 - Use of symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory: A crosspoint array is made up of a plurality of bitlines and wordlines and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline, and each crossbar element comprising at least a phase change material used as a rectifier in series with a... Agent: International Business Machines Corporation

20110141803 - Magnetic tunnel junction devices, electronic devices including a magnetic tunneling junction device and methods of fabricating the same: Perpendicular magnetic tunnel junction (MTJ) devices, methods of fabricating a perpendicular MTJ device, electronic devices including a perpendicular MTJ device and methods of fabricating the electronic device are provided, the perpendicular MTJ devices include a pinned layer, a tunneling layer and a free layer. At least one of the pinned... Agent: Gwangju Institute Of Science And Technology

20110141802 - Method and system for providing a high density memory cell for spin transfer torque random access memory: A method and system for providing a magnetic memory are described. The method and system include providing a plurality of magnetic storage cells, a plurality of bit lines corresponding to the magnetic storage cells, a plurality of word lines corresponding to the magnetic storage cells, and a common voltage plane... Agent: Grandis, Inc.

20110141804 - Method and system for providing dual magnetic tunneling junctions usable in spin transfer torque magnetic memories: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The pinned layers are nonmagnetic layer-free and self-pinned. In some aspects, the magnetic junction is... Agent: Grandis, Inc.

20110141808 - Methods and apparatus for programming multiple program values per signal level in flash memories: Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality... Agent: Lsi Corporation

20110141809 - Page buffer of non-volatile memory device and programming method of non-volatile memory device: Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node... Agent: Hynix Semiconductor Inc.

20110141810 - Read operation for non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent:

20110141811 - Semiconductor memory device: A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing... Agent:

20110141812 - Method and apparatus for restoring data in a non-volatile memory: A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data.... Agent: Mosys, Inc.

20110141813 - Use of emerging non-volatile memory elements with flash memory: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash... Agent:

20110141814 - Nonvolatile semiconductor memory device: According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to... Agent: Kabushiki Kaisha Toshiba

20110141815 - Methods and apparatus for read-side intercell interference mitigation in flash memories: Methods and apparatus are provided for read-side intercell interference mitigation in flash memories, A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell;... Agent:

20110141816 - Tracking cells for a memory system: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust... Agent: Sandisk Corporation

20110141806 - Flash memory device and method for manufacturing flash memory device: A method of manufacturing a flash memory device is provided. First and second gates are formed on first and second dielectrics and spaced apart from each other on a cell area of a substrate. A third gate is formed on a third dielectric that is formed on first opposing sidewalls... Agent: Dongbu Hitek Co., Ltd.

20110141805 - Method of programming an electrically programmable and erasable non-volatile memory point, and corresponding memory device: An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the... Agent: Stmicroelectronics (grenoble 2) Sas

20110141807 - Semiconductor device and control method therefor: A semiconductor device includes an insulation layer (14) provided on a semiconductor substrate (12), a p-type semiconductor region (16) provided on the insulation layer, an isolation region (18) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region (20) and an n-type drain region... Agent:

20110141818 - Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells: Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can... Agent:

20110141819 - Segmented bitscan for verification of programming: A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether... Agent:

20110141817 - Semiconductor memory device and method for controlling the same: According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and are capable of storing write data and/or read... Agent:

20110141821 - Non-volatile semiconductor storage device and method of manufacturing the same: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers... Agent: Kabushiki Kaisha Toshiba

20110141820 - Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to... Agent:

20110141823 - Semiconductor memory device and method for controlling the same: According to one embodiment, a semiconductor memory device includes a memory cell array, and first to third latch circuits. The first latch circuits hold information as to whether an associated column is defective. A pointer is set in the second latch circuits. The third latch circuits hold write data or... Agent:

20110141824 - Leakage compensated reference voltage generation system: An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor,... Agent: International Business Machines Corporation

20110141825 - Semiconductor integrated circuit system and electronic equipment: A semiconductor integrated circuit system comprises a semiconductor memory device including a memory cell array having a plurality of memory cells; a monitor circuit for monitoring characteristics of the memory cells; and a voltage output circuit connected to the semiconductor memory device to supply a power supply voltage to the... Agent: Panasonic Corporation

20110141826 - Cache array power savings through a design structure for valid bit detection: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated... Agent: International Business Machines Corporation

20110141829 - Circuits for reducing power consumption of memory components: An integrated circuit including one or more data links. A respective data link includes a precharge circuit, a voltage generator circuit, and a transmitter circuit. The precharge circuit is configured to precharge a data line to a predefined voltage level between transmission of symbols on the data line. The voltage... Agent:

20110141827 - Method and apparatus for dynamically adjusting voltage reference to optimize an i/o system: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically... Agent:

20110141828 - Semiconductor system: To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core... Agent: Elpida Memory, Inc.

20110141830 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a sense amplifier configured to sense and amplify data loaded into a bit line pair, a power line equalize signal generation unit configured to generate a power line equalize signal which is activated until the bit line sense amplifier is enabled after a bit line... Agent:

20110141831 - Read buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation

20110141833 - Low-wear writing in a solid state memory device: A method includes programming a non-volatile memory. The memory includes a plurality of cells, wherein each cell is configured to store a plurality of values, wherein each of value is represented by N digits where N is an integer greater than 1, wherein each of the plurality of cells is... Agent: Seagate Technology LLC

20110141832 - Program cycle skip: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be... Agent:

20110141822 - Source bias shift for multilevel memories: The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics... Agent:

20110141834 - Semiconductor device with ddr memory controller: In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive... Agent: Renesas Electronics Corporation

20110141835 - Circuit and method for testing multi-device systems: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system,... Agent: Mosaid Technologies Incorporated

20110141836 - Techniques for reducing impact of array disturbs in a semiconductor memory device: Techniques for reducing impact of array disturbs in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing impact of array disturbs in a semiconductor memory device by increasing the refresh rate to the semiconductor memory device based at... Agent: Innovative Silicon Isi Sa

20110141838 - Semiconductor memory device: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to... Agent: Renesas Electronics Corporation

20110141837 - Voltage regulation circuitry: Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node,... Agent: Arm Limited

20110141839 - Device and method for protecting data in non-volatile memory: Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device (200) that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit (230) to delay a drop in voltage of an input/output... Agent:

20110141840 - Nor-or decoder: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR... Agent: Novelics, LLC.

20110141841 - Synchronous semiconductor memory device having on-die termination circuit and on-die termination method: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having... Agent: Samsung Electronics Co., Ltd.

  
06/09/2011 > patent applications in patent subcategories. invention type

20110134676 - Resistive memory devices having a not-and (nand) structure: Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to... Agent: International Business Machines Corporation

20110134677 - Content addressable memory: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and... Agent: Renesas Electronics Corporation

20110134678 - Semiconductor device having hierarchical structured bit line: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing... Agent: Elpida Memory, Inc.

20110134679 - Memory module having optical beam path, apparatus including the module, and method of fabricating the module: A memory module may include at least one memory package including an optical signal input/output (I/O) unit and a first optical beam path and a printed circuit board (PCB) on which the memory package is mounted. The PCB may have a second optical beam path configured to transmit an optical... Agent:

20110134680 - Semiconductor memory device: To provide a semiconductor memory device including an oxide semiconductor that can deal with instability of a threshold characteristic, in which writing is possible by a simple method. The semiconductor memory device functions by utilizing a characteristic that a threshold shifts when a thin film transistor including an oxide semiconductor... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110134681 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory layers arranged in multi layer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at... Agent: Kabushiki Kaisha Toshiba

20110134682 - Variable write and read methods for resistive random access memory: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the... Agent: Seagate Technology LLC

20110134683 - Semiconductor device: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line;... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110134684 - Integrated circuits with split gate and common gate finfet transistors: s

20110134685 - Energy-efficient set write of phase change memory with switch: Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.... Agent:

20110134687 - Resistance variable memory device and method of writing data: A method of programming a resistance variable memory cell to a given logic state includes applying a first programming current to the memory cell, executing a verify read of the memory cell by sensing a logic state of the memory cell, and applying a second programming current to the memory... Agent: Samsung Electronics Co., Ltd.

20110134686 - Semiconductor devices including sense amplifier connected to word line: A semiconductor device includes a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, and a sense amplifier block for sensing and amplifying a signal of a word line among the plurality of word lines.... Agent: Samsung Electronics Co., Ltd.

20110134688 - Asymmetric write current compensation: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The... Agent: Seagate Technology LLC

20110134689 - Magnetic recording element, magnetic memory cell, and magnetic random access memory: A low-power consumption non-volatile memory employing an electric field write magnetic recording element is provided. A multiferroic layer 301 is provided adjacent to a magnetic recording layer 2002, and by applying an electric field to the multiferroic layer to control the dielectric state of the multiferroic, the magnetization direction of... Agent: Hitachi, Ltd.

20110134690 - Method of controlling a dram memory cell on the seoi having a second control gate buried under the insulating layer: The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a... Agent:

20110134691 - Scalable multi-function and multi-level nano-crystal non-volatile memory device: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate... Agent: Micron Technology, Inc.

20110134693 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent:

20110134694 - High voltage generation and control in source-side injection programming of non-volatile memory: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent... Agent: Sandisk Corporation

20110134695 - Semiconductor memory device: Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with... Agent: Kabushiki Kaisha Toshiba

20110134696 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent:

20110134697 - Dynamic pass voltage for sense operation in a memory device: Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the... Agent: Micron Technology, Inc.

20110134699 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent:

20110134698 - Flash memory cell on seoi having a second control gate buried under the insulating layer: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel,... Agent:

20110134700 - Nonvolatile semiconductor memory: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent... Agent: Kabushiki Kaisha Toshiba

20110134701 - Memory kink compensation: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses.... Agent: Micron Technology, Inc.

20110134703 - Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits: A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate... Agent:

20110134702 - Programming methods and memories: Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected... Agent: Micron Technology, Inc.

20110134692 - Adaptive dynamic reading of flash memories: A data storage device includes a controller and storage elements. The controller is configured to read a threshold voltage of each of a plurality of the storage elements to generate read threshold data and to assign reference voltages defining each of a plurality of voltage threshold states based on the... Agent: Sandisk Il Ltd.

20110134704 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor, a latch unit, including a first... Agent:

20110134705 - Integrated circuit package with multiple dies and a multiplexed communications interface: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex... Agent: Stmicroelectronics Srl

20110134706 - Semiconductor memory device: A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word... Agent: Renesas Technology Corporation

20110134707 - Block isolation control circuit: A block isolation control circuit includes: a control signal generation unit configured to generate a control signal which is disabled when a defect occurs in a cell block and it is necessary to replace a defective cell block with a redundant cell block, or when the cell block is not... Agent:

20110134708 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in... Agent: Micron Technology, Inc.

20110134709 - Semiconductor device including nonvolatile memory: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by... Agent: Fujitsu Semiconductor Limited

20110134710 - Level shift circuit: A feedback circuit by which an output of a memory device for storing level-shifted data can be fed back to the input side includes inverters, resistors, and transistors. The resistance value of combined resistance for pulling up or down first and second switching devices is varied in accordance with the... Agent: Fuji Electric Systems Co., Ltd.

20110134711 - Memory control circuit and memory control method: A memory control circuit includes a data sample circuit, a first delay control circuit, a second delay control circuit and a data circuit. The data sample circuit is used for generating a first data strobe signal and a second data strobe signal. The first delay control circuit is coupled to... Agent:

20110134712 - Apparatus and method for trimming static delay of a synchronizing circuit: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an... Agent:

20110134713 - Methods circuits devices and systems for operating an array of non-volatile memory cells: Disclosed are methods, circuits, devices and systems for operating one or more non-volatile memory (NVM) cells within an array of NVM cells. According to embodiments, there may be provided a nonvolatile memory (NVM) device comprising an array of NVM data cells including one or more border/periphery data cells and one... Agent:

20110134714 - Semiconductor memory device changing refresh interval depending on temperature: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to... Agent: Fujitsu Semiconductor Limited

20110134715 - Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory: A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked... Agent: Unity Semiconductor Corporation

  
06/02/2011 > patent applications in patent subcategories. invention type

20110128764 - Semiconductor memory device: A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the second amplifier circuit, a first equalizer circuit being coupled to the first and second bit lines, and a second... Agent: Elpida Memory, Inc.

20110128765 - Identifying and accessing individual memory devices in a memory channel: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity... Agent:

20110128767 - Memory with intervening transistor: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated... Agent: Infineon Technologies Ag

20110128766 - Programmable resistance memory: A nonvolatile integrated circuit memory includes mode control circuitry that allows it to be configured as any of a plurality of memory types.... Agent:

20110128768 - Memory interface circuit: According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential... Agent: Kabushiki Kaisha Toshiba

20110128769 - Data holding device: A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV3 and INV4 of FIG. 1); a nonvolatile storage part (CL1a, CL1b, CL2a, CL2b, Q1a, Q1b, Q2a and Q2b) that utilizes the hysteresis characteristic of a... Agent: Rohm Co., Ltd.

20110128772 - Nonvolatile memory cells and nonvolatile memory devices including the same: A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series.... Agent: Samsung Electronics Co., Ltd.

20110128776 - Nonvolatile memory device and method of writing data to nonvolatile memory device: A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to... Agent:

20110128774 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a... Agent: Kabushiki Kaisha Toshiba

20110128775 - Nonvolatile semiconductor storage device and data writing method therefor: A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in... Agent: Kabushiki Kaisha Toshiba

20110128773 - Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device: To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to... Agent:

20110128771 - Resistance based memory circuit with digital sensing: A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance... Agent: Qualcomm Incorporated

20110128770 - Stored multi-bit data characterized by multiple-dimensional memory states: Subject matter disclosed herein relates to enhancing data storage density of a memory device.... Agent:

20110128777 - Semiconductor device: The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110128778 - Predictive thermal preconditioning and timing control for non-volatile memory cells: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning... Agent: Seagate Technology LLC

20110128779 - Memory including a selector switch on a variable resistance memory cell: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.... Agent:

20110128780 - Semiconductor device: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and... Agent: Renesas Electronics Corporation

20110128781 - Semiconductor memory circuit: A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the... Agent:

20110128782 - Reducing effects of erase disturb in a memory device: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string.... Agent: Micron Technology, Inc.

20110128784 - Non-volatile memory device: An electronic memory device is presented. The device comprises at least one basic unit (FIG. 2), which is configured as a memory cell for storing at least one bit of information. The basic unit comprises a vacuum cavity (FIG. 2, 2) for free charge carriers propagation therethrough, a region of... Agent: Nova-trans Group Sa

20110128785 - Apparatus and method for protecting data in flash memory: An apparatus for securely protecting data in a flash memory upon power off is disclosed. In the apparatus, a power detector monitors a voltage output from a power supply unit, and outputs a power fail signal when the voltage drops by a predetermined reference voltage or more. A Programmable Logic... Agent: Samsung Electronics Co. Ltd.

20110128786 - Memory device: A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the... Agent: Macronix International Co., Ltd.

20110128787 - Ripple programming of memory cells in a nonvolatile memory: An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bit lines. A memory cell is programmed by applying a high programming voltage to... Agent: Texas Instruments Incorporated

20110128788 - Nand flash memory: A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling... Agent: Kabushiki Kaisha Toshiba

20110128789 - Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is... Agent: Kabushiki Kaisha Toshiba

20110128790 - Analog sensing of memory cells in a solid-state memory device: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the... Agent: Micron Technology, Inc.

20110128783 - Method of reading nonvolatile memory device and method of operating nonvolatile memory device: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are... Agent:

20110128791 - Method and apparatus of performing an erase operation on a memory integrated circuit: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also... Agent: Macronix International Co., Ltd.

20110128792 - Semiconductor storage device and boosting circuit: A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of... Agent: Kabushiki Kaisha Toshiba

20110128793 - Preamble detection and postamble closure for a memory interface controller: A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of... Agent: Juniper Networks, Inc.

20110128794 - Apparatus and method for controlling operation timing in semiconductor memory device: An apparatus for controlling an operation timing in a semiconductor memory device, comprising: a shift information generator configured to generate shift information based on data path delay information and latency information; and a shift register configured to shift a command based on the shift information and produce a shifted command... Agent:

20110128796 - Disturb-free static random access memory cell: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a... Agent:

20110128795 - Semiconductor memory device having sense amplifier: A sense amplifier prevents a reduction in sensing margin occurring when data forms an island pattern. The sense amplifier includes a first inverter having an input terminal connected to a bit line and an output terminal connected to a bar bit line, and a second inverter having an input terminal... Agent:

20110128797 - Sense amplifying circuit, and semiconductor memory device having the same: A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge... Agent:

20110128798 - Power source circuit and semiconductor memory circuit using the same: A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count... Agent: Hynix Semiconductor Inc.

20110128799 - Level shifting circuit and nonvolatile semiconductor memory apparatus using the same: A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a... Agent: Hynix Semiconductor Inc.

20110128800 - Semiconductor memory apparatus: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured... Agent: Hynix Semiconductor Inc.

20110128801 - Semiconductor device and operating method thereof: In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110128802 - Semiconductor memory device: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the... Agent:

20110128803 - Core voltage discharger and semiconductor memory device with the same: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.... Agent:

20110128806 - Semiconductor integrated circuit test method and semiconductor integrated circuit: In a semiconductor integrated circuit having multiple memory macros, a memory macro test is carried out with high accuracy within a short period of time. A semiconductor integrated circuit test method according to one aspect of the present invention is applicable to inspection of a semiconductor integrated circuit having multiple... Agent: Renesas Electronics Corporation

20110128805 - Test circuit, nonvolatile semiconductor memory appratus using the same, and test method: A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching... Agent: Hynix Semiconductor Inc.

20110128804 - Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus: A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled;... Agent: Hynix Semiconductor Inc.

20110128807 - Memory device and sense circuitry therefor: A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled... Agent: Freescale Semiconductor, Inc

20110128808 - Current sense amplifier with feedback loop: A sensing circuit (100) for sensing the content of a memory cell (101), wherein the sensing circuit comprises a sense node (103) connectable to the memory cell (101) so that a signal indicative of the content of the memory cell (101) is providable to the sense node (103). The sensing... Agent: Nxp B.v.

20110128809 - Method and apparatus of addressing a memory integrated circuit: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set... Agent: Macronix International Co., Ltd.

20110128810 - Memory device and memory control for controlling the same: A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes... Agent: Fujitsu Semiconductor Limited

20110128811 - Internal command generation circuit: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst... Agent: Hynix Semiconductor Inc.

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