|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
05/2011 | Recent | 14: Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval May archived by USPTO category 05/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/26/2011 > patent applications in patent subcategories. archived by USPTO category
20110122670 - Semiconductor device: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110122671 - Systems and methods for controlling integrated circuit operation with below ground pin voltage: Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit... Agent:
20110122672 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel... Agent: Renesas Electronics Corporation
20110122673 - Semiconductor device including memory cell: A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110122674 - Reverse connection mtj cell for stt mram: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110122678 - Anti-parallel diode structure and method of fabrication: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a... Agent: Seagate Technology LLC
20110122675 - Programmable resistance memory: A nonvolatile memory includes write circuitry that writes to a selected memory element and, in parallel, to a data latch. The memory is configured to compare the current memory address to the previous memory address and to enable a read operation from the data latch rather than a selected memory... Agent:
20110122679 - Resistive sense memory calibration for self-reference read method: Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory... Agent: Seagate Technology LLC
20110122676 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the... Agent: Kabushiki Kaisha Toshiba
20110122677 - Semiconductor memory device: First main bit lines correspond to at least one first memory cell. Second main bit lines correspond to at least one second memory cell. At least one sense amplifier outputs read data according to a difference between a voltage of any one of the first main bit lines and a... Agent: Panasonic Corporation
20110122680 - Variable resistance nonvolatile memory device: A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a... Agent:
20110122681 - Semiconductor memory device: n
20110122682 - High density low power nanowire phase change material memory device: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the... Agent: International Business Machines Corporation
20110122685 - Multi-level phase-change memory device and method of operating same: A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected... Agent: Samsung Electronics Co., Ltd.
20110122683 - Resetting phase change memory bits: After determining that a reset pulse has reached its programmed threshold voltage level, a lower voltage verify can be conducted. This can be followed by another program step to increase the programmed threshold voltage. By avoiding the need for subsequent verification after the cell has reached its desired threshold level,... Agent:
20110122684 - Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of... Agent: Industrial Technology Research Institute
20110122686 - Non-volatile electromechanical configuration bit array: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.... Agent: Agate Logic, Inc.
20110122689 - Reducing effects of program disturb in a memory device: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage.... Agent: Micron Technology, Inc.
20110122687 - Techniques for reducing disturbance in a semiconductor device: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory... Agent: Innovative Silicon Isi Sa
20110122693 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent:
20110122690 - Method for programming multi-level cell and memory apparatus: m
20110122691 - Power management of memory systems: A memory system that includes a memory array and a memory controller manages power consumption by maintaining a variable credit value that reflects the amount of power available to the memory system. The variable credit value may be increased periodically up to a limit. When a power-consuming operation is performed,... Agent: Sandisk Corporation
20110122692 - Programming non-volatile memory with a reduced number of verify operations: A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached,... Agent:
20110122694 - Limitation of the access to a resource of an electronic circuit: A method and a circuit for controlling the access to at least one resource of an electronic circuit, in which a test of the value of a counter over at least one bit conditions the access to the resource, the counter being automatically reset after a time period independent from... Agent: Proton World International N.v.
20110122695 - Programming memory with bit line floating to reduce channel-to-floating gate coupling: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of... Agent:
20110122696 - Non-volatile semiconductor memory device: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states... Agent: Renesas Electronics Corporation
20110122697 - Method of programming a nonvolatile memory device: A method of programming a nonvolatile memory device is disclosed. The method includes providing a plurality of memory cells coupled to a wordline, the plurality of memory cells grouped into a plurality of groups, each group including at least two memory cells, such that for each cell of the plurality... Agent:
20110122699 - Controlling a memory device responsive to degradation: Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize... Agent: Micron Technology, Inc.
20110122700 - Relaxed metal pitch memory architectures: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied... Agent:
20110122701 - Semiconductor memory having electrically erasable and programmable semiconductor memory cells: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to... Agent:
20110122698 - Semiconductor memory device: A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and... Agent: Kabushiki Kaisha Toshiba
20110122704 - Method of programming nonvolatile memory device: The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing an erase operation, counting an erase pulse application number once the erase operation is completed, comparing the... Agent: Hynix Semiconductor Inc.
20110122705 - Method of programming nonvolatile memory device: The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing an erase operation, counting an erase pulse application number once the erase operation is completed, comparing the... Agent: Hynix Semiconductor Inc.
20110122703 - Programming memory with direct bit line driving to reduce channel-to-floating gate coupling: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines. Dedicated power supplies can be used to provide the... Agent:
20110122702 - Programming memory with sensing-based bit line compensation to reduce channel-to-floating gate coupling: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by... Agent:
20110122688 - Reading array cell with matched reference cell: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to... Agent:
20110122706 - Operating method in a non-volatile memory device: A method of verifying a non-volatile memory device to increase the read margin even though a negative verifying voltage is not applied is disclosed. The method of verifying a non-volatile memory device includes coupling a cell string to a bit line precharged to a high level through a sensing node,... Agent: Hynix Semiconductor Inc.
20110122707 - Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is... Agent:
20110122708 - Method and apparatus for performing semiconductor memory operations: A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging... Agent: Spansion LLC
20110122710 - Method and apparatus for generating a sequence of clock signals: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input... Agent: Round Rock Research, LLC
20110122709 - Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit: A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory... Agent: Samsung Electronics Co., Ltd.
20110122711 - Bitline precharge voltage generator, semiconductor memory device comprising same, and method of trimming bitline precharge voltage: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the... Agent: Samsung Electronics Co., Ltd.
20110122712 - Controlling voltage levels applied to access devices when accessing storage cells in a memory: A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at... Agent: Arm Limited
20110122713 - Read strobe feedback in a memory system: A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed... Agent: Micron Technology, Inc.
20110122714 - Control method for memory cell: A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory... Agent: Industrial Technology Research Institute
20110122716 - Dynamic random access memory device and method of determining refresh cycle thereof: Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal... Agent: Samsung Electronics Co., Ltd.
20110122715 - Redundant memory array for replacing memory sections of main memory: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main... Agent:
20110122717 - Replacing defective columns of memory cells in response to external addresses: Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory... Agent: Micron Technology, Inc.
20110122718 - Low cost testing and sorting for integrated circuits: Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is... Agent:
20110122719 - Pre-charge voltage generation and power saving modes: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set... Agent:
20110122720 - Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and... Agent: Micron Technology, Inc.
20110122721 - Y-decoder and decoding method thereof: A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a... Agent: Macronix International Co., Ltd.05/19/2011 > patent applications in patent subcategories. archived by USPTO category
20110116298 - Memory emulation using resistivity-sensitive memory: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element,... Agent: Unity Semiconductor Corporation
20110116297 - Multi-layered memory devices: A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes... Agent:
20110116296 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory component in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one... Agent: Sony Corporation
20110116299 - Semiconductor device: In the semiconductor device, a dummy fuse is provided adjacent to a fuse, each wiring width of the fuse and the dummy fuse is set to the minimum line width, and the interval between the fuse and the dummy fuse is set to the minimum interval. Consequently, the exposure condition... Agent: Renesas Electronics Corporation
20110116302 - Asymmetric write current compensation using gate overdrive for resistive sense memory cells: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching... Agent: Seagate Technology LLC
20110116300 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell array including plural mutually crossing first and second lines and memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistance element and a rectifier element connected in series; and... Agent: Kabushiki Kaisha Toshiba
20110116301 - State machine sensing of memory cells: The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell... Agent: Micron Technology, Inc.
20110116306 - Magnetic random access memory and initializing method for the same: A domain wall motion type MRAM has: a magnetic recording layer 10 being a ferromagnetic layer having perpendicular magnetic anisotropy; a pair of current supply terminals 14a and 14b connected to the magnetic recording layer 10 for supplying a current to the magnetic recording layer 10; and an anti-ferromagnetic layer... Agent: Nec Corporation
20110116303 - Magnetic tunnel junction and memristor apparatus: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor... Agent: Seagate Technology LLC
20110116305 - Magnetoresistive element: A magnetoresistive element includes a first magnetic layer which includes a first surface and a second surface and has a first standard electrode potential, a second magnetic layer, a barrier layer which is provided between the second magnetic layer and the first surface of the first magnetic layer, and a... Agent:
20110116304 - Spin current generator for stt-mram or other spintronics applications: Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin... Agent: Micron Technology, Inc.
20110116308 - Multiple phase change materials in an integrated circuit for system on a chip application: An integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first... Agent: Macronix International Co., Ltd.
20110116307 - Phase change memory device suitable for high temperature operation: A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The... Agent: International Business Machines Corporation
20110116309 - Refresh circuitry for phase change memory: A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the... Agent: Macronix International Co., Ltd.
20110116310 - Semiconductor device and driving method thereof: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110116311 - Reduction of punch-through disturb during programming of a memory device: In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage,... Agent: Micron Technology, Inc.
20110116314 - Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data: A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through... Agent:
20110116312 - Non volatile cell and architecture with single bit random access read, program and erase: One embodiment is a non-volatile memory cell with random access read, program, and erase. The memory cell includes a cell transistor that includes a source region, a drain region, a first insulating spacer, and a second insulating spacer. The memory cell also includes a source-side transistor, a drain-side transistor, a... Agent: International Business Machines Corporation
20110116315 - Nonvolatile semiconductor memory device: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has... Agent: Kabushiki Kaisha Toshiba
20110116313 - Read method for mlc: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Micron Technology, Inc.
20110116316 - Nonvolatile random access memory: A nonvolatile random access memory that can be mounted on a substrate during a standard CMOS process. A memory cell comprises: a first MIS transistor including a first semiconductor layer of a first conductivity type in an electrically floating state, first drain and source regions of a second conductivity type... Agent:
20110116317 - Program and erase methods with substrate transient hot carrier injections in a non-volatile memory: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of... Agent: Macronix International Co., Ltd.
20110116318 - Memory array of floating gate-based non-volatile memory cells: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A... Agent: Intersil Americas Inc.
20110116319 - Memory array of floating gate-based non-volatile memory cells: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A... Agent: Intersil Americas Inc.
20110116320 - Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory: In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared... Agent:
20110116321 - Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power... Agent: Renesas Electronics Corporation
20110116322 - Charge recycling memory system and a charge recycling method thereof: A memory system, including a nonvolatile memory device, a charge recycler configured to discharge charges from the nonvolatile memory device and recycle the discharged charges, and a controller configured to control the nonvolatile memory device and the charge recycler, wherein the controller controls the charge recycler to recycle the discharged... Agent:
20110116323 - Semiconductor device, method of controlling the same, and method of manufacturing the same: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO... Agent:
20110116324 - Memory array of floating gate-based non-volatile memory cells: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A... Agent: Intersil Americas Inc.
20110116325 - Computer apparatus and memory error signal detecting system: A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level.... Agent: Inventec Corporation
20110116326 - Refresh signal generating circuit: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal... Agent: Hynix Semiconductor Inc.
20110116327 - Memory devices having adjustable refresh cycles responsive to temperature changes: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh... Agent:
20110116328 - Memory device and method thereof: An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also... Agent: Freescale Semiconductor, Inc.
20110116329 - Semiconductor storage device: A memory cell (100) includes a read circuit (30) whose output wiring is a read bit line (RBIT) and which has a switching transistor (31), a reset transistor (32), and an output wiring driving transistor (33). The switching transistor (31) connects a data holding node (MD) of a storage circuit... Agent:
20110116330 - Semiconductor device having additive latency: A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting... Agent: Samsung Electronics Co., Ltd.
20110116331 - Method for initializing memory device: A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output serial data of the memory device. During a clock cycle of the at least N+1... Agent: Himax Technologies Limited
20110116332 - Memory device with test mechanism: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of... Agent: Nscore Inc.
20110116333 - Memory test apparatus and testing method: A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an... Agent: Advantest Corporation
20110116334 - Semiconductor memory device: A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging... Agent:
20110116335 - Semiconductor memory device and system including the same: A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in... Agent:
20110116336 - Multi-layered memory devices: A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes... Agent:
20110116337 - Synchronising between clock domains: An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be... Agent:05/12/2011 > patent applications in patent subcategories. archived by USPTO category
20110110139 - Multi-state memory and multi-functional devices comprising magnetoplastic or magnetoelastic materials: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is... Agent: Boise State University
20110110142 - Memory device and method of reading memory device: A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of... Agent: Sony Corporation
20110110143 - Method of programming nonvolatile memory element: Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR... Agent:
20110110140 - Reference current generator for resistance type memory and method thereof: A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of... Agent: National Tsing Hua University
20110110141 - Resistive memory: A memory device includes an array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer coupled to the first signal electrode and the second signal electrode; a plurality of word... Agent:
20110110144 - Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device: A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of... Agent: Panasonic Corporation
20110110145 - Semiconductor device: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110110146 - Semiconductor memory which enables reliable data writing with low supply voltage by improving the conductance via access transistors during write operation: A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between... Agent: Fujitsu Semiconductor Limited
20110110147 - Compound cell spin-torque magnetic random access memory: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance... Agent: Seagate Technology LLC
20110110148 - Memory arrays and associated methods of manufacturing: Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact... Agent: Micron Technology, Inc.
20110110150 - Semiconductor device: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and... Agent: Hitachi, Ltd.
20110110149 - Structure and method for biasing phase change memory array for reliable writing: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory... Agent:
20110110151 - Magnetic memory with a thermally assisted spin transfer torque writing procedure using a low writing current: A magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure, comprising a magnetic tunnel junction formed from a ferromagnetic storage layer having a first magnetization adjustable at a high temperature threshold, a ferromagnetic reference layer having a fixed second magnetization, and an insulating layer, said... Agent: Crocus Technology Sa
20110110153 - Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory: In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a... Agent:
20110110154 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device comprises applying a gradually increasing program voltage to a memory cell, determining the number of verify voltages to be applied to the memory cell during a program loop based on the change of a threshold voltage from an initial state of the... Agent: Samsung Electronics Co., Ltd.
20110110155 - Stacked semiconductor devices including a master device: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).... Agent: Mosaid Technologies Incorporated
20110110157 - Random access memory with cmos-compatible nonvolatile storage element and parallel storage capacitor: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a... Agent: S. Aqua Semiconductor, LLC
20110110156 - Semiconductor device and method of manufacturing the same: There is provided a technology which can allow a semiconductor chip formed with a nonvolatile memory to be sufficiently reduced in size. There is also provided a technology which can ensure the reliability of the nonvolatile memory. In a memory cell of the present invention, a boost gate electrode is... Agent: Renesas Electronics Corporation
20110110158 - Mass storage device with solid-state memory components capable of increased endurance: A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient... Agent: Ocz Technology Group, Inc.
20110110159 - Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected... Agent:
20110110160 - Area-efficient electrically erasable programmable memory cell: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In... Agent: Texas Instruments Incorporated
20110110161 - Method of programming a flash memory device: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is... Agent:
20110110152 - Non-volatile multilevel memory cells with data read of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold... Agent: Micron Technology, Inc.
20110110162 - Structures and methods for reading out non-volatile memories: Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventional sensing scheme.... Agent:
20110110163 - Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same: A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The... Agent: Micron Technology, Inc.
20110110164 - Trim circuit and semiconductor memory device comprising same: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the... Agent: Samsung Electronics Co., Ltd.
20110110165 - Clock mode determination in a memory system: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from... Agent: Mosaid Technologies Incorporated
20110110167 - Integrated circuit: An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a... Agent:
20110110166 - Semiconductor device: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as... Agent: Renesas Electronics Corporation
20110110168 - Semiconductor memory device, semiconductor memory module and semiconductor memory system including the semiconductor memory device: A semiconductor memory device, a semiconductor memory module, and a semiconductor memory system including the same, the semiconductor memory device including a command/address input buffer that receives a command/address signal and a command/address reference voltage signal, wherein the command/address input buffer is configured to amplify a difference between the command/address... Agent: Samsung Electronics Co., Ltd.
20110110170 - Non-volatile memory systems and methods including page read and/or configuration features: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment... Agent:
20110110169 - Sense amplifier with reduced area occupation for semiconductor memories: A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of... Agent: Stmicroelectronics, S.r.i.
20110110171 - Powerless external event detection device: The external event detection device comprises an electronic unit (22) and an external event sensor (16), the electronic unit having at least a non-volatile memory cell (24, T1) in which data relative to at least one external event detected by the external event sensor can be stored. According to the... Agent: Em Microelectronic-marin Sa
20110110172 - Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such... Agent: Samsung Electronics Co., Ltd.
20110110173 - Signal generating circuit and related storage apparatus: A signal generating circuit is employed for generating a control in order to control operations of one of a controller and at least a storage unit of a related storage apparatus controlled by the controller. The signal generating circuit includes a voltage inputting unit and a voltage detection unit. The... Agent:
20110110174 - System and method of operating a memory device: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and... Agent: Qualcomm Incorporated
20110110175 - Memory refresh system and operating method thereof: A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by comparing the voltage with a reference voltage. Each memory... Agent: National Tsing Hua University
20110110176 - Address control circuit and semiconductor memory device: An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from... Agent: Hynix Semiconductor Inc.05/05/2011 > patent applications in patent subcategories. archived by USPTO category
20110103120 - Binray content addressable memory: The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration... Agent: University-industry Cooperation Group Of Kyunghee University
20110103121 - Stacked semiconductor device and automatic chip recognition selection circuit: A semiconductor device includes a plurality of stacked chips which are allocated with different self-chip addresses. Each of the plurality of stacked chips includes a frequency change circuit, a self-address storing circuit and a determination circuit. The frequency change circuit changes a first frequency of a signal into a second... Agent: Elpida Memory, Inc.
20110103122 - System and method for optimizing interconnections of components in a multichip memory module: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs,... Agent:
20110103123 - Semiconductor device: Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair;... Agent: Elpida Memory, Inc.
20110103124 - Semiconductor memory device: A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and... Agent: Renesas Electronics Corporation
20110103125 - Memory cells having a folded digit line architecture: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array,... Agent: Micron Technology, Inc.
20110103126 - Semiconductor memory device: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities... Agent: Panasonic Corporation
20110103127 - And-type one time programmable memory cell: An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes... Agent: Sidence Corp.
20110103133 - Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array: A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically... Agent:
20110103135 - Non-volatile memory device and method for writing data thereto: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to... Agent: Kabushiki Kaisha Toshiba
20110103131 - Nonvolatile memory element and nonvolatile memory device: Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes... Agent:
20110103132 - Nonvolatile memory element and semiconductor memory device including nonvolatile memory element: A nonvolatile memory element comprises a current controlling element (112) having a non-linear current-voltage characteristic, a resistance variable element (105) which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance... Agent:
20110103128 - Nonvolatile semiconductor memory device: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity;... Agent: Kabushiki Kaisha Toshiba
20110103130 - Resistance change memory device: A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to... Agent: Kabushiki Kaisha Toshiba
20110103134 - Resistance random access memory having common source line: A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the... Agent: Samsung Electronics Co., Ltd.
20110103129 - Variable-resistance material memories, processes of forming same, and methods of using same: A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a... Agent:
20110103136 - Semiconductor memory device: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and... Agent: Hitachi, Ltd.
20110103137 - Source controlled sram: Disclosed is a cmos sram cell including two cross-coupled inverters, each having a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of... Agent: Silicon Basis Ltd
20110103138 - Single-charge tunneling device: A single-electron transistor (1) has an elongate conductive channel (2) and a side gate (3) formed in a 5 nm-thick layer (4) of Ga0.98Mn0.02As. The single-electron transistor (1) is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory.... Agent:
20110103140 - Data read circuit for phase change memory device and apparatuses including the same: The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line... Agent:
20110103139 - Double-pulse write for phase change memory: The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower... Agent:
20110103141 - Reading a phase change memory: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some... Agent:
20110103142 - Semiconductor device: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current.... Agent: Renesas Electronics Corporation
20110103143 - Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains... Agent: Avalanche Technology Inc.
20110103145 - M+n bit programming and m+l bit read for m bit memory cells: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the... Agent: Micron Technology, Inc.
20110103144 - Structures and methods of trimming threshold voltage of a flash eeprom memory: A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed... Agent:
20110103146 - Memory device of the electrically erasable and programmable type, having two cells per bit: The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of... Agent: Stmicroelectronics (rousset) Sas
20110103147 - Nand flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive... Agent: Samsung Electronics Co., Ltd.
20110103149 - Nonvolatile semiconductor memory device and method for driving same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality... Agent: Kabushiki Kaisha Toshiba
20110103148 - Normally off gallium nitride field effect transistors (fet): A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source... Agent: Alpha & Omega Semiconductor, Inc.
20110103151 - Methods of programming semiconductor memory devices: To program a semiconductor memory device, a plurality of target threshold voltage groups are set by dividing target threshold voltages representing states of memory cells. The target threshold voltage groups are substantially simultaneously programmed by applying a plurality of program voltages to a word line. Program end times for the... Agent: Samsung Electronics Co., Ltd.
20110103150 - Non-volatile memory with predictive programming: A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse... Agent: Infineon Technologies Ag
20110103152 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in... Agent: Kabushiki Kaisha Toshiba
20110103154 - Local self-boosting method of flash memory device and program method using the same: Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at... Agent:
20110103153 - Nonvolatile semiconductor memory device and method for driving same: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode... Agent: Kabushiki Kaisha Toshiba
20110103155 - Operation method of memory device: One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate... Agent: Acer Incorporated
20110103159 - Degradation equalization for a memory: In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one... Agent:
20110103156 - Data input/output circuit and semiconductor memory apparatus having the same: A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank.... Agent: Hynix Semiconductor Inc.
20110103157 - Time reduction of address setup/hold time for semiconductor memory: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input.... Agent:
20110103158 - Low voltage sensing scheme having reduced active power down standby current: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is... Agent:
20110103160 - Semiconductor memory apparatus: A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and... Agent: Hynix Semiconductor Inc.
20110103161 - Method of reducing the occurrence of burn-in due to negative bias temperature instability: A method for alleviating burn-in effect and enabling performing a start-up process in respect of a device comprising a plurality of challengeable memory elements, wherein the memory elements are able to, upon start-up, generate a response pattern of start-up values useful for identification as the response pattern depends on physical... Agent:
20110103163 - Multi-bit test control circuit: A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse... Agent:
20110103162 - Semiconductor memory apparatus: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and... Agent: Hynix Semiconductor Inc.
20110103165 - Self-refresh test circuit of semiconductor memory apparatus: A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal... Agent: Hynix Semiconductor Inc.
20110103164 - Semiconductor memory device and method for performing data compression test of the same: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of... Agent:
20110103166 - Layout structure of bit line sense amplifiers for a semiconductor memory device: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of... Agent: Samsung Electronics Co., Ltd.
20110103168 - Bit line sense amplifier of semiconductor memory device having open bit line structure: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a... Agent: Samsung Electronics Co., Ltd.
20110103167 - Sense amplifier and semiconductor memory apparatus including the same: A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and... Agent: Hynix Semiconductor Inc.
20110103169 - Dynamic random access memory device and method for self-refreshing memory cells: A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal.... Agent: Mosaid Technologies Incorporated
20110103170 - Novel fuse programming schemes for robust yield: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.... Agent: Intel Corporation
20110103171 - Semiconductor memory apparatus: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to corresponding memory cells in the first and... Agent: Hynix Semiconductor Inc.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140925:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.01646 seconds