|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
04/2011 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval April category listing, related patent applications 04/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/28/2011 > patent applications in patent subcategories.
20110096582 - Content addressable memory with concurrent two-dimensional search capability in both row and column directions: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of... Agent: International Business Machines Corporation
20110096583 - Semiconductor modules and signal line layout methods thereof: A memory module and a layout method of the memory module. The memory module includes memory devices connected to corresponding tabs through corresponding damping resistors formed on a printed circuit board and includes a first signal line group in a first region between the memory devices and the damping resistors... Agent: Samsung Electronics Co., Ltd.
20110096584 - Semiconductor device having open bit line architecture: When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third... Agent: Elpida Memory, Inc.
20110096585 - Semiconductor device having hierarchical data line structure and control method thereof: To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and... Agent: Elpida Memory, Inc.
20110096586 - Semiconductor memory device having layout area reduced: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a... Agent: Renesas Electronics Corporation
20110096587 - Dynamic sense current supply circuit and associated method for reading and characterizing a resistive memory array: A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a... Agent: Nantero, Inc.
20110096589 - Nanowire-based memristor devices: Embodiments of the present invention are directed to memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device includes a first electrode, a second electrode, and a nanowire disposed between the first electrode and the second electrode. The nanowire is configured with an inner region surrounded by... Agent:
20110096588 - Non-volatile memory array architecture incorporating 1t-1r near 4f2 memory cell: A nonvolatile memory array architecture includes a resistive element between each common source/drain (intermediate) node and data line (or bit line), in an otherwise virtual ground-like memory array having serially-connected transistors coupled to the same word line. However, every N+1 transistors the corresponding resistive element is omitted (or generally kept... Agent:
20110096590 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a cell array having plural memory cells arranged in matrix, each memory cell including a variable resistor having a resistance reversibly variable to store data corresponding to the resistance of the variable resistor; a selection circuit operative to select a memory cell from the... Agent: Kabushiki Kaisha Toshiba
20110096591 - Information storage element and method for driving the same: Disclosed herein is an information storage element including: a word electrode includes a first magnetic material that is continuously formed and is electrically conductive; a non-magnetic film formed in contact with the first magnetic material of the word electrode; a second magnetic material connected to the first magnetic material via... Agent: Sony Corporation
20110096593 - Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains... Agent: Avalanche Technology Inc.
20110096592 - Thin film magnetic memory device writing data with bidirectional current: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets... Agent: Renesas Electronics Corporation
20110096594 - Memory reading method for resistance drift mitigation: Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes... Agent: International Business Machines Corporation
20110096595 - Semiconductor memory device and operation method thereof: Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film (2) sandwiched between metal... Agent:
20110096596 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of the plurality of memory cells. The power supply... Agent: Renesas Electronics Corporation
20110096597 - Programming a flash memory device: An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the... Agent: Micron Technology, Inc.
20110096599 - Multi level inhibit scheme: Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the... Agent: Micron Technology, Inc.
20110096598 - Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit... Agent: Kabushiki Kaisha Toshiba
20110096600 - Semiconductor memory device reducing resistance fluctuation of data transfer line: According to one embodiment, a semiconductor memory device includes first and second memory cell blocks and an interconnect rerouting unit provided therebetween. The first memory cell block includes first interconnects and second interconnects provided in each space between the first interconnects. The second memory cell block includes a plurality of... Agent: Kabushiki Kaisha Toshiba
20110096601 - Non-volatile memory and method with accelerated post-write read to manage errors: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An... Agent:
20110096602 - Nonvolatile memory devices operable using negative bias voltages and related methods of operation: A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first... Agent: Samsung Electronics Co., Ltd.
20110096603 - Reverse order page writing in flash memories: To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the... Agent: Sandisk Il Ltd.
20110096605 - Semiconductor memory device and method for controlling the same: A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line... Agent: Kabushiki Kaisha Toshiba
20110096604 - Semiconductor memory device including alternately arranged contact members: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer... Agent: Toshiba Corporation
20110096607 - Programming a memory device to increase data reliability: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group... Agent: Micron Technology, Inc.
20110096606 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent:
20110096608 - Mitigation of runaway programming of a memory device: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by... Agent: Micron Technology, Inc.
20110096609 - Novel punch-through free program scheme for nt-string flash design: A nonvolatile memory array has nonvolatile memory cells arranged in rows and columns where each column has a bit line and source line associated with and in parallel with the nonvolatile memory cells. In programming the nonvolatile memory cell, approximately equal program voltage levels are applied to a drain and... Agent: Aplus Flash Technology, Inc.
20110096610 - Method for enabling a sonos transistor to be used as both a switch and a memory: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to... Agent: Acer Incorporated
20110096611 - Semiconductor device and semiconductor system having the same: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank... Agent:
20110096612 - Method, system, and computer readable medium for reading and programming flash memory cells: A system, method and computer readable medium for programming and reading flash memory cells. Respective first and second read operations may be performed while supplying respective first and second bias voltage to multiple flash memory cells, to provide respective first and second read results, where the first bias voltage may... Agent:
20110096613 - Semiconductor device: A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to... Agent: Elpida Memory, Inc.
20110096614 - Single-strobe operation of memory devices: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted... Agent: Mosaid Technologies Incorporated
20110096615 - Memory devices having redundant arrays for repair: Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data... Agent: Micron Technology, Inc.
20110096616 - Sense amplifier circuit to enable speeding-up of readout of information from memory cells: A sense amplifier circuit, which is connected to a bit line and to an inverted bit line to which a voltage, inverted alternatively from a high level or a low level of a voltage applied to the bit line, is applied, includes a first resistance section reducing a voltage output... Agent: Elpida Memory, Inc.04/21/2011 > patent applications in patent subcategories.
20110090728 - Memory core and semiconductor memory device having the same: A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line... Agent: Samsung Electronics Co., Ltd.
20110090727 - Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices: A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module... Agent:
20110090729 - Semiconductor storage device and rom generator: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection... Agent: Kabushiki Kaisha Toshiba
20110090730 - Magnetic memory structure and operation method: A magnetic memory structure includes a memory track which has consecutive magnetic domains. Each of the magnetic domains has memory capacity of one bit. A first domain-wall injecting layer intersects and connects a terminal of the memory track and constantly stores a first binary data. A second domain-wall injecting layer... Agent: Industrial Technology Research Institute
20110090731 - Green transistor for nano-si ferro-electric ram and method of operating the same: The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a... Agent: Semiconductor Manufacturing International (shanghai) Corporation
20110090732 - Magnetic tunnel junction cell adapted to store multiple digital values: A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.... Agent: Qualcomm Incorporated
20110090733 - Memory with separate read and write paths: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is... Agent: Seagate Technology LLC
20110090735 - Expanded programming window for non-volatile multilevel memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include... Agent: Micron Technology, Inc.
20110090734 - Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each... Agent:
20110090736 - Semiconductor memory device: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense... Agent:
20110090737 - 3d non-volatile memory device and method for operating and fabricating the same: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source... Agent:
20110090738 - Nand flash memory device having dummy memory cells and methods of operating same: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality... Agent: Samsung Electronics Co., Ltd.
20110090739 - Independent well bias management in a memory device: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory... Agent: Micron Technology, Inc.
20110090741 - Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory... Agent: Sandisk Corporation
20110090740 - Nonvolatile memory device and related method of operation: A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two... Agent: Samsung Electronics Co., Ltd.
20110090742 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent:
20110090743 - Sub volt flash memory system: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other... Agent:
20110090744 - Channel precharge and program methods of a nonvolatile memory device: A channel pre-charge method of a nonvolatile memory device including a cell string includes pre-charging a channel of the cell string according to a first word line bias condition and pre-charging the channel of the cell string according to a second word line bias condition, different than the first word... Agent:
20110090746 - Device and method generating internal voltage in semiconductor memory device: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command... Agent: Samsung Electronics Co., Ltd.
20110090745 - Sense amplifier with fast bitline precharge means: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the... Agent: Stmicroelectronics (rousset) Sas
20110090748 - Device for supplying a high erase program voltage to an integrated circuit: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal... Agent: Stmicroelectronics (rousset) Sas
20110090747 - Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of... Agent: Stmicroelectronics (rousset) Sas
20110090749 - Circuit for providing chip-select signals to a plurality of ranks of a ddr memory module: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first... Agent: Netlist, Inc.
20110090750 - Sram delay circuit that tracks bitcell characteristics: An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and... Agent: International Business Machines Corporation
20110090751 - Systems and methods for efficiently repairing dynamic random-access memory having marginally failing cells: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column... Agent: Avago Technologies EnterpriseIP(singapore) Pte. Ltd.
20110090752 - Semiconductor memory device: There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line... Agent: Oki Semiconductor Co., Ltd.
20110090754 - Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory: An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels... Agent:
20110090753 - Power management: An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110090755 - Memory device having multiple power modes: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is... Agent:04/14/2011 > patent applications in patent subcategories.
20110085364 - Semiconductor signal processing apparatus: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit.... Agent: Renesas Electronics Corporation
20110085366 - Device: A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag... Agent: Elpida Memory, Inc.
20110085365 - Semiconductor device: A semiconductor device includes a substrate including a cell area and a sense amplifier area, a first bit line connected to a bit line contact of the cell area and a first contact of the sense amplifier area, and a second bit line located on the first bit line to... Agent: Hynix Semiconductor Inc.
20110085368 - Non-volatile memory device and method of manufacturing the same: The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines... Agent: Samsung Electronics Co., Ltd.
20110085367 - Switched memory devices: A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of... Agent: Seagate Technology LLC
20110085369 - Method to improve ferroelectric memory performance and reliability: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip.... Agent: Texas Instruments Incorporated
20110085370 - Soft forming reversible resistivity-switching element for bipolar switching: A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance... Agent:
20110085371 - Apparatus of low power dual word line six-transistor srams: A six-transistor SRAM cell with dual word line and dual bit line is provided. Each word line is used to separately control an access transistor of the SRAM cell. A six-transistor SRAM cell with dual word line and a single bit line is also provided. The dual word line SRAM... Agent:
20110085372 - Non-volatile sram cell that incorporates phase-change memory into a cmos process: A SRAM cell having two cross-coupled inverters formed by CMOS technology and first and second chalcogenic elements integrated with the SRAM cell to add nonvolatile properties to the storage cell. The PCM resistors are programmed to the SET state and the RESET state, and upon power-up the SRAM cell takes... Agent:
20110085374 - Semiconductor device: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible... Agent: Renesas Electronics Corporation
20110085373 - Spin-transfer torque memory self-reference read method: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the... Agent: Seagate Technology LLC
20110085375 - Methods for determining resistance of phase change memory elements: Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of... Agent: Micron Technology, Inc.
20110085376 - Shunted phase change memory: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions... Agent:
20110085377 - Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers... Agent: Kabushiki Kaisha Toshiba
20110085378 - Memory and operation method therefor: In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on... Agent: Macronix International Co., Ltd.
20110085380 - Method of programming a memory: A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data... Agent: Macronix International Co., Ltd.
20110085379 - Nonvolatile memory device and system and related method of operation: A nonvolatile memory device detects a first memory cell to be successfully programmed in a program operation for multiple memory cells connected to a wordline, and then detects a number of program loops required to successfully program the remaining memory cells connected to the wordline. An initial program voltage of... Agent: Samsung Electronics Co., Ltd.
20110085381 - Charge carrier device: A device comprises an impurity ion disposed in an insulating region, a semiconductor region adjacent to the insulating region, an electrometer arranged to detect charge carriers in the semiconductor region and at least one control gate configured to apply an electric field to the insulating region and semiconductor region. The... Agent: Hitachi, Ltd.
20110085382 - Universal dual charge-retaining transistor flash nor cell, a dual charge-retaining transistor flash nor cell array, and method for operating same: A NOR flash memory cell is formed of dual serially connected charge retaining transistors. A drain/source of a first of the dual charge retaining transistors connected to a local bit line and a source/drain of a second of the dual charge retaining transistors connected to a local source line. The... Agent: Aplus Flash Technology, Inc.
20110085383 - Current sink system for source side sensing: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the... Agent: Macronix International Co., Ltd.
20110085384 - Current sink system for source-side sensing: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the... Agent: Macronix International Co., Ltd.
20110085385 - Nonvolatile memory devices having dummy cell and bias methods thereof: Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy... Agent: Samsung Electronics Co., Ltd.
20110085386 - Methods of programming and reading single-level trapped-charge memory cells using second-bit threshold detection: Methods are disclosed to compensate for a second-bit effect during programming and reading of charge-trapping memory cells having left and right data regions. When only one of the left and right data regions is to be programmed, a two-step programming procedure is performed on the data region to be programmed.... Agent:
20110085387 - Semiconductor memory apparatus with clock and data strobe phase detection: A semiconductor memory apparatus includes an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal, and a data input sense amplifier configured to transmit data bits to a... Agent: Hynix Semiconductor, Inc.
20110085388 - System in package integrated circuit with self-generating reference voltage: This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals... Agent:
20110085389 - Method and system to lower the minimum operating voltage of a memory array: A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write... Agent:
20110085390 - Word-line level shift circuit: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a... Agent: International Business Machines Corporation
20110085391 - Memory with improved read stability: A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least... Agent: Arm Limited
20110085392 - Method for writing data to memory array: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used... Agent: Nanya Technology Corp.
20110085393 - Semiconductor memory apparatus and data input/output method thereof: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to... Agent: Hynix Semiconductor Inc.
20110085394 - Latency circuit and semiconductor device comprising same: A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a... Agent: Samsung Electronics Co., Ltd.
20110085395 - Output enable signal generating circuit and method of semiconductor memory apparatus: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output... Agent: Hynix Semiconductor, Inc.
20110085396 - Repair fuse device: A repair fuse device is provided. The repair fuse device remarkably reduces the number of the enable fuse cuttings by making initial states of all repair fuse sets to a repair state, cutting an address fuse corresponding to a defective cell, and cutting an enable fuse corresponding to a defective... Agent: Hynix Semiconductor Inc.
20110085397 - Semiconductor device and information processing system including the same: A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit... Agent: Elpida Memory, Inc.
20110085398 - Multiple cycle memory write completion: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one... Agent: Mosys, Inc.
20110085399 - Method for extending word-line pulses: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20110085400 - Semiconductor device: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this... Agent: Renesas Electronics Corporation
20110085401 - Semiconductor memory device: A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled... Agent:
20110085402 - Bank re-assignment in chip to reduce ir drop: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the centre of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes:... Agent:
20110085403 - Semiconductor memory device and information processing system including the same: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip... Agent: Elpida Memory, Inc.
20110085404 - Semiconductor memory device and information processing system including the same: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip... Agent: Elpida Memory, Inc.
20110085405 - Semiconductor memory device having advanced tag block: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address... Agent:
20110085406 - Circuit providing load isolation and memory domain translation for memory module: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first... Agent: Netlist, Inc.04/07/2011 > patent applications in patent subcategories.
20110080763 - Method for contemporaneous margin verification and memory access for memory cells in cross-point memory arrays: Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of... Agent: Unity Semiconductor Corporation
20110080764 - One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected... Agent: Renesas Electronics Corporation
20110080765 - Programmable antifuse transistor and method for programming thereof: Programmable antifuse transistor, in particular n-channel MOS transistor, and a method for programming at least one such antifuse transistor, includes at least one gate with a gate terminal, source with a source terminal, drain with a drain terminal, and substrate with a substrate terminal, configured so that active circuits/circuit elements... Agent: Silicon Line Gmbh
20110080770 - Method of programming variable resistance element and nonvolatile storage device: Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state a write state, applying an erasing voltage pulse having a second polarity different... Agent:
20110080766 - Resistive memory device and manufacturing method thereof and operating method thereof: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted... Agent: Macronix International Co., Ltd.
20110080767 - Resistive memory device and manufacturing method thereof and operating method thereof: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon... Agent: Unity Semiconductor Corporation
20110080769 - Spatial correlation of reference cells in resistive memory array: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory... Agent: Seagate Technology LLC
20110080768 - Write current compensation using word line boosting circuitry: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device,... Agent: Seagate Technology LLC
20110080771 - Dram positive wordline voltage compensation device for array device threshold voltage and voltage compensating method thereof: The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array... Agent: Nanya Technology Corp.
20110080772 - Body controlled double channel transistor and circuits comprising the same: By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the... Agent: Globalfoundries Inc.
20110080773 - Circuit for generating adjustable timing signals for sensing a self-referenced mram cell: Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device for selecting one of the MRAM cells, and a sense circuit for sourcing a sense current to measure the first and second resistance... Agent: Crocus Technology Sa
20110080777 - Adaptive wordline programming bias of a phase change memory: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused... Agent:
20110080780 - Method for programming a multilevel phase change memory device: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at... Agent: Macronix International Co., Ltd.
20110080775 - Nonvolatile memory device, storage system having the same, and method of driving the nonvolatile memory device: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or... Agent:
20110080778 - Phase change memory device: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set... Agent: Kabushiki Kaisha Toshiba
20110080781 - Phase change memory device and control method: The present invention relates to a phase change memory device comprising a plurality of phase change memory cells, each cell comprising a phase change material (50) conductively coupled between a first electrode (44) and a second electrode (42) for applying a reset current pulse having a predefined polarity to the... Agent: Interuniversitair Microelektronica Centrum Vzw
20110080774 - Semiconductor device: Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included... Agent: Semiconductor Energy Laboratory Co., Ltd
20110080779 - Semiconductor device including resistance storage element: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write... Agent: Renesas Electronics Corporation
20110080776 - Semiconductor memory device having diode cell structure: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence,... Agent: Elpida Memory Inc.
20110080782 - Write current compensation using word line boosting circuitry: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device,... Agent: Seagate Technology LLC
20110080783 - Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic... Agent: Micron Technology, Inc.
20110080786 - Dynamically configurable mlc state assignment: Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values... Agent: Micron Technology, Inc.
20110080784 - Non-volatile memory and operation method thereof: An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than... Agent: Macronix International Co., Ltd.
20110080785 - Semiconductor memory device, and multi-chip package and method of operating the same: Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data... Agent: Hynix Semiconductor Inc.
20110080788 - Driving method of semiconductor device: A semiconductor memory circuit including a memory cell region and a test region and a control circuit are included in a semiconductor device of the present invention. In the control circuit, a first operation is performed for writing data to a memory cell, and writing a first storage state to... Agent: Semiconductor Energy Laboratory Co., Ltd.
20110080787 - Non-volatile memory apparatus and methods: Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus... Agent: Micron Technology, Inc.
20110080789 - Automatic selective slow program convergence: Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a... Agent: Micron Technology, Inc.
20110080790 - Array of non-volatile memory cells including embedded local and global reference cells and system: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source,... Agent:
20110080791 - Nonvolatile memory device and related method of operation: A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops.... Agent: Samsung Electronics Co., Ltd.
20110080792 - Parallel bitline nonvolatile memory employing channel-based processing technology: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the... Agent: Spansion LLC
20110080793 - Sensing amplifier applied to at least a memory cell, memory device, and enhancement method for boosting the sensing amplifier thereof: A sensing amplifier consists of a sensing circuit, a boosting circuit, at least one bit-line isolating circuit, and at least a P-sensing enhancement circuit. The sensing circuit is disposed between a sensing line and a complementary sensing line. The boosting circuit boosts the sensing line and the complementary sensing line... Agent:
20110080794 - Semiconductor memory device and method of operating the same: A semiconductor memory device allows a read command to be inputted thereto after a passage of a relatively short time period from a point in time where a write command has been inputted thereto. A method of operating the semiconductor memory device includes inputting a write command, inputting a read... Agent:
20110080795 - Semiconductor memory device and data read method thereof: A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the... Agent:
20110080796 - Integrated circuit: An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect the second bit line to/from the sense amplifier independently... Agent: Qimonda Ag
20110080797 - Semiconductor device having sense amplifiers: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power... Agent: Elpida Memory, Inc.
20110080798 - Digital retention voltage generation: A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.33668 seconds