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Static information storage and retrieval March listing by industry category 03/11

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
03/31/2011 > patent applications in patent subcategories. listing by industry category

20110075466 - Methods and apparatus for using a configuration array similar to an associated data array: Methods, apparatus, and systems in accordance with this invention include memories that include a data array and a configuration array adapted to store configuration information for configuring the data array. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of... Agent:

20110075467 - Ferroelectric memory devices and operating methods thereof: A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased... Agent: Samsung Electronics Co., Ltd.

20110075469 - Resistance variable nonvolatile memory device: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and... Agent:

20110075468 - Reverse set with current limit for non-volatile storage: A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.... Agent:

20110075470 - Embedded sram structure and chip: An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20110075471 - Enhancing read and write sense margins in a resistive sense element: An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction... Agent: Seagate Technology LLC

20110075472 - Magnetoresistive device having specular sidewall layers: A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall.... Agent: Seagate Technology LLC

20110075473 - Circuit and method for generating reference voltage, phase change random access memory apparatus and read method using the same: A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference... Agent: Hynix Semiconductor Inc.

20110075474 - Phase change random access memory apparatus and write control method for the same: The disclosed phase change random access memory apparatus is configured to program a predetermined phase change memory cell in the phase change memory apparatus in response to a plurality of write instructions applied at independent points of time.... Agent: Hynix Semidonductor Inc.

20110075475 - Set algorithm for phase change memory cell: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias... Agent: Macronix International Co., Ltd.

20110075476 - Spintronic device and information transmitting method: At least one metal electrode made of any of Pt, Au, Pd, Ag, Bi, alloys of these, or elements having an f-orbital are provided on top of a magnetic dielectric layer and, so that spin-wave spin current—pure spin current exchange is carried out at the interface between the above described... Agent: Keio University

20110075477 - Reducing the impact of interference during programming: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior... Agent:

20110075479 - Multi-level cell copyback program method in a non-volatile memory device: A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first... Agent: Hynix Semiconductor Inc.

20110075480 - Non-volatile memory with improved sensing by reducing source line current: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects... Agent:

20110075478 - Nonvolatile memory device and system, and method of programming a nonvolatile memory device: A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive... Agent: Samsung Electronics Co., Ltd.

20110075481 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other... Agent: Kabushiki Kaisha Toshiba

20110075482 - Maintaining integrity of preloaded content in non-volatile memory during surface mounting: A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the... Agent:

20110075483 - Non-volatile semiconductor storage device and method of controlling the same: According to one embodiment, a non-volatile semiconductor storage device includes a control circuit. When performing a read operation, the control circuit is configured to: apply a first voltage to a selected word line that is connected to a selected memory cell, the first voltage being a voltage between a plurality... Agent: Kabushiki Kaisha Toshiba

20110075485 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to one aspect of the present invention includes a plurality of sense amplifier circuit that are configured to carry out a plurality of read cycles on a plurality of bit lines connected to those memory cells that are selected by a selected one of... Agent: Kabushiki Kaisha Toshiba

20110075484 - Nonvolatile memory device and nonvolatile memory system employing same: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor... Agent: Samsung Electronics Co., Ltd.

20110075487 - Booster circuit and semiconductor memory: A booster circuit includes a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node; a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node; a first switch coupling... Agent: Fujitsu Semiconductor Limited

20110075486 - Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low... Agent: Macronix International Co., Ltd.

20110075488 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second... Agent: Kabushiki Kaisha Toshiba

20110075489 - Non-volatile semiconductor memory device: Two or more writing prohibition voltages are applied to bit lines connected to memory cell transistors corresponding to the writing voltage of word lines in a writing operation to write data in the memory cell transistors, while increasing the writing voltage of the word line in a stepwise. Two or... Agent: Kabushiki Kaisha Toshiba

20110075490 - Data stripes and addressing for flash memory devices: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory... Agent: Seagate Technology LLC

20110075491 - Semiconductor memory apparatus and method of driving bit-line sense amplifier: Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power... Agent: Hynix Semiconductor Inc.

20110075492 - Memory device bit line sensing system and method that compensates for bit line resistance variations: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and... Agent: Micron Technology, Inc.

20110075493 - Nonvolatile memory devices and methods of controlling the wordline voltage of the same: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages... Agent: Samsung Electronics Co., Ltd.

20110075494 - Data transfer circuit: A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to... Agent: Kabushiki Kaisha Toshiba

20110075495 - Semiconductor memory apparatus and driving method usingthe same: Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate... Agent: Hynix Semiconductor Inc.

20110075496 - Memory controller comprising adjustable transmitter impedance: Memory controllers, memory devices and methods are provided in which test data is transmitted and signal parameters are varied. The transmitted test data is read, and based on a comparison between transmitted test data and read test data a transmitter impedance is adjusted.... Agent: Infineon Technologies Ag

20110075497 - Memory system and method using stacked memory device dice, and system using the memory system: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of... Agent: Micron Technology, Inc.

20110075498 - Semiconductor memory apparatus and test method using the same: A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense... Agent: Hynix Semiconductor Inc.

20110075499 - Semiconductor memory device comprising sensing circuits with adjacent column selectors: A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to... Agent: Samsung Electronics Co., Ltd.

20110075500 - Semiconductor memory device and a method of controlling a semiconductor memory device: A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated... Agent: Renesas Electronics Corporation

20110075501 - Multi-channel semiconductor integrated circuit devices for controlling direct current generators and memory systems including the same: Multi-channel semiconductor integrated circuit devices are provided including a plurality of memory devices that are independently accessible, each of the plurality of memory devices including at least one power generation unit and a control unit for controlling an operation of the at least one power generation unit, a detection unit... Agent:

20110075502 - Bank active signal generation circuit: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode.... Agent: Hynix Semiconductor Inc.

20110075503 - Main decoding circuit and semiconductor memory apparatus including the same: A main decoding circuit includes a shared column selection signal generating unit and a switching unit. The shared column selection signal generating unit receives a column decoding signal to generate a shared column selection signal. The switching unit selectively provides the shared column selection signal to one of a column... Agent: Hynix Semiconductor Inc.

20110075504 - Dual beta ratio sram: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes... Agent: International Business Machines Corporation

20110075505 - Semiconductor memory device and layout structure of sub-word line control signal generator: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At... Agent: Samsung Electronics Co., Ltd.

  
03/24/2011 > patent applications in patent subcategories. listing by industry category

20110069521 - Adjustable write bins for multi-level analog memories: An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory... Agent: International Business Machines Corporation

20110069522 - Variable resistance memory with lattice array using enclosing transistors: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are... Agent:

20110069526 - High performance solid-state drives and methods therefor: A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes... Agent: Ocz Technology Group, Inc.

20110069525 - Nonvolatile memory device and method for manufacturing same: According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell is connected to a first interconnection and a second interconnection and includes a plurality of layers. The plurality of layers includes a memory layer and a carbon nanotube-containing layer which is in contact with the... Agent: Kabushiki Kaisha Toshiba

20110069524 - Semiconductor memory device: A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first... Agent:

20110069523 - Semiconductor memory device and multilayered chip semiconductor device: Disclosed here is a semiconductor memory device including: a semiconductor substrate; a plurality of pads formed on the semiconductor substrate and configured to permit data input and output; and a memory core block and an I/O block integrated on the semiconductor substrate. The data items are input and output to... Agent: Sony Corporation

20110069527 - Rom cell and array structure: A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20110069528 - Electronic device with a programmable resistive element and a method for blocking a device: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a... Agent: Infineon Technologies Ag

20110069529 - Methods of reading and using memory cells: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration... Agent:

20110069530 - Nonvolatile memory device and method of manufacturing the same: According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a... Agent:

20110069532 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of... Agent: Kabushiki Kaisha Toshiba

20110069531 - Nonvolatile semiconductor storage device and method of manufacturing the same: According to one embodiment, a method of manufacturing a nonvolatile semiconductor storage device includes a memory-cell forming step, a first wire forming step, and a second wire forming step. The memory-cell forming step is forming dummy memory cells arranged at a predetermined space apart from an end memory cell located... Agent:

20110069533 - Resistance change memory and control method thereof: According to one embodiment, a resistance change memory includes a memory cell array in which a plurality of blocks are provided, resistance change storage elements which are provided in blocks and which store data in accordance with a change in resistance state, first and second wirings in the blocks, each... Agent:

20110069535 - Magnetic random access memory with dual spin torque reference layers: A magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic cell includes first and second fixed magnetic layers and a free magnetic layer positioned between the fixed magnetic layers. The magnetic cell also includes terminals configured for providing a spin-polarized current through the magnetic... Agent: Seagate Technology LLC

20110069537 - Magnetic storage element responsive to spin polarized current: The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the... Agent: Seagate Technology LLC

20110069536 - Reconfigurable magnetic logic device using spin torque: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has... Agent: Seagate Technology LLC

20110069534 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each... Agent: Kabushiki Kaisha Toshiba

20110069540 - Method of a phase-change memory programming: A method of programming a phase-change memory (PCM) device to the high resistance reset state by means of pressure-induced amorphization. A train of few short bipolar current pulses is applied to the PCM device in order to stress phase-change alloy (PCA) under high pressure, and current in each pulse is... Agent:

20110069538 - Multi-level cell programming of pcm by varying the reset amplitude: A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes... Agent: Infineon Technologies North America Corp.

20110069539 - Programming multi-level phase change memory cells: A method and a feedback controller for programming at least one multi-level phase-change memory cell with a programming signal. The method and feedback controller include a sequence of write pulses applied to the multi-level phase change memory cell, wherein the feedback controller adjusts in real time at least one parameter... Agent: International Business Machines Corporation

20110069541 - Ferromagnetic thin wire element: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the... Agent: The University Of Electro-communications

20110069543 - Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the... Agent:

20110069542 - Nonvolatile semiconductor memory device including nand-type flash memory and the like: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and... Agent:

20110069548 - Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array: Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping... Agent: Micron Technology, Inc.

20110069544 - Method and apparatus for programming a multi-level memory: A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program... Agent:

20110069545 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller... Agent: Kabushiki Kaisha Toshiba

20110069546 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory... Agent: Kabushiki Kaisha Toshiba

20110069547 - Sensing against a reference cell: Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range... Agent: Micron Technology, Inc.

20110069549 - Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit... Agent:

20110069550 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not... Agent:

20110069551 - Non-volatile semiconductor memory with page erase: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A... Agent: Mosaid Technologies Incorporated

20110069552 - Nonvolatile semiconductor memory device and method of data read therein: A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from... Agent: Kabushiki Kaisha Toshiba

20110069553 - Semiconductor storage device comprising dot-type charge accumulation portion and control gate, and method of manufacturing the same: A semiconductor memory device includes a first insulation film, Charge accumulation portions, a second insulation film, and a control gate. The first insulation film is located on an active area (AA). The charge accumulation portions comprise minute crystals arranged on the first insulation film. A density of the charge accumulation... Agent:

20110069555 - Non-volatile memory device and method of operating the same: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate... Agent: Industry-university Cooperation Foundation, Hanyang-university

20110069554 - Sense-amplifier circuit for non-volatile memories that operates at low supply voltages: A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior... Agent: Stmicroelectronics S.r.l.

20110069556 - Nand flash memory: A NAND flash memory has a memory cell transistor, the memory cell transistor including a charge storage layer formed over a well of a semiconductor substrate surface via a first insulation film and insulated from surroundings, and a control gate provided over the charge storage layer via a second insulation... Agent: Kabushiki Kaisha Toshiba

20110069557 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a... Agent: Kabushiki Kaisha Toshiba

20110069558 - Local word line driver of a memory: A memory includes a local word line driver for a memory array having a first word line and a second word line. The local word line driver includes a first selection transistor, a second selection transistor, and a middle transistor disposed between the first and second selection transistors. The first... Agent:

20110069559 - Methods of forming and operating back-side trap non-volatile memory cells: Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a trapping material, forming two or more sub-layers of dielectric material on the trapping material, wherein a conduction band offset of each sub-layer of dielectric material is less... Agent: Micron Technology, Inc.

20110069564 - Semiconductor device and method of controlling the same: A semiconductor device may include, but is not limited to: a first insulating film; first and second impurity layers on the first insulating film; a semiconductor layer on the first insulating film; a second insulating film covering the semiconductor layer; a first electrode on the second insulating film over the... Agent: Elpida Memory, Inc.

20110069560 - Data capture system and method, and memory controllers and devices: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first... Agent: Micron Technology, Inc.

20110069561 - System and method for controlling timing of output signals: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of... Agent: Micron Technology, Inc.

20110069562 - Low consumption voltage regulator for a high voltage charge pump, voltage regulation method, and memory device provided with the voltage regulator: A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the... Agent: Stmicroelectronics S.r.l.

20110069563 - Voltage shifter for high voltage operations: A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives... Agent: Stmicroelectronics S.r.l.

20110069565 - Memory cell employing reduced voltage: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory... Agent: Texas Instruments Incorporated

20110069566 - Memory cell write: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and... Agent:

20110069567 - Memory device having data paths with multiple speeds: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.... Agent: Round Rock Research, LLC

20110069568 - Semiconductor memory device having local sense amplifier with on/off control: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration... Agent:

20110069569 - Semiconductor memory device comprising transistor having vertical channel structure: A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including... Agent: Samsung Electronics Co., Ltd.

20110069570 - Memory circuits and method for accessing data of the memory circuits: A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110069571 - Word line decoder circuit apparatus and method: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and... Agent: Macronix International Co., Ltd.

20110069572 - Row address code selection based on locations of substandard memory cells: A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to... Agent: Samsung Electronics Co., Ltd.

20110069573 - Semiconductor memory device: A semiconductor device includes a plurality of bank sets and an address controller. Each bank set includes a plurality of banks Each bank includes a plurality of memory mats and sense amplifier arrays corresponding to row addresses. The plurality of bank sets is arranged in both sides of arrays of... Agent: Elpida Memory, Inc.

20110069574 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, a word line driver, and a bit line booster. The memory cell array has multiple word lines WL, multiple bit line pairs BL, and multiple memory cells MC provided at the respective intersections of the word lines WL and the bit... Agent: Kabushiki Kaisha Toshiba

20110069575 - Electronic device and method for preventing data loss in memory storage device and electronic device assembly: An electronic device includes a memory storage device, a storing unit, and a voltage increasing unit. The storing unit is used for receiving the supply voltage to store energy and releasing energy to generate an standby voltage when the power supply stops providing the supply voltage. The voltage increasing unit... Agent: Hon Hai Precision Industry Co., Ltd.

  
03/17/2011 > patent applications in patent subcategories. listing by industry category

20110063884 - Structure and method for backing up and restitution of data: A structure and a method for backing up and restitution of data allowing management of a memory space. The backup and restitution structure includes a matrix of connectors distributed in line and in column, on said matrix. Each connector of one line is connected to its two adjacent connectors. Each... Agent:

20110063885 - Information storage devices including vertical nano wires: A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least... Agent: Samsung Electronics Co., Ltd.

20110063886 - Semiconductor memory device and driving method of the same: A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first... Agent: Kabushiki Kaisha Toshiba

20110063888 - Green transistor for resistive random access memory and method of operating the same: A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20110063887 - Nonvolatile semiconductor memory device capable of testing diodes and manufacturing method thereof: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells.... Agent:

20110063890 - Semiconductor memory device: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential... Agent: Elpida Memory, Inc.

20110063889 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second... Agent:

20110063891 - Semiconductor device, semiconductor memory device and data processing system comprising semiconductor system: A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based... Agent: Elpida Memory, Inc.

20110063892 - Sense amplifier circuit and semiconductor device: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate... Agent: Elpida Memory, Inc.

20110063894 - Sram cells, memory circuits, systems, and fabrication methods thereof: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110063893 - Systems and methods for reducing memory array leakage in high capacity memories by selective biasing: A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In... Agent:

20110063895 - Semiconductor integrated circuit device and system: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent... Agent: Renesas Electronics Corporation

20110063896 - Semiconductor memory device: A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second... Agent: Renesas Electronics Corporation

20110063897 - Differential read and write architecture: A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the... Agent: Grandis, Inc.

20110063900 - Magnetic memory: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to... Agent: Kabushiki Kaisha Toshiba

20110063899 - Magnetic memory element, method of driving same, and nonvolatile storage device: In order to obtain a memory cell of size 4 F2 to realize cross-point type memory, a magnetic memory element is used having a spin valve structure including a free layer 5, nonmagnetic layer 4, and layer 3. The layer or the free layer includes an N-type ferrimagnetic material, and... Agent: Fuji Electric Holdings Co., Ltd

20110063898 - Method and system for providing a hierarchical data path for spin transfer torque random access memory: A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes... Agent: Grandis, Inc.

20110063901 - Static source plane in stram: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell... Agent: Seagate Technology LLC

20110063902 - 2t2r-1t1r mix mode phase change memory array: A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between... Agent: Macronix International Co., Ltd.

20110063903 - Nonvolatile memory devices, systems having the same, and write current control methods thereof: Provided is a nonvolatile memory device, a memory system having the same, and a write current control method thereof. The memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a plurality of write modes. The memory controller includes a sensor configured to sense... Agent: Samsung Electronics Co., Ltd.

20110063904 - Phase change memory device, memory system, and programming method: A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by... Agent: Samsung Electronics Co., Ltd.

20110063907 - Fractional bits in memory cells: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to... Agent: Micron Technology, Inc.

20110063906 - Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell: A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.... Agent: Micron Technology, Inc.

20110063905 - Multi-valued rom using carbon-nanotube and nanowire fet: A multivalued memory device which includes a first multivalued memory transistor and a second multivalued memory transistor, wherein each transistor has a channel made from at least one carbon nanotube or nanowire, wherein data is stored by varying the number of carbon nanotubes or nanowires used in the channel, wherein... Agent: Toshiba America Research, Inc.

20110063908 - Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory: Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110063909 - Nonvolatile semiconductor memory and method of testing the same: A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory cells. A block control unit operates according to input signals from outside and controls operation of the... Agent: Kabushiki Kaisha Toshiba

20110063912 - Methods and structures for reading out non-volatile memory using nvm cells as a load element: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with... Agent:

20110063911 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality... Agent:

20110063910 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent:

20110063913 - Three dimensional stacked nonvolatile semiconductor memory: In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential... Agent:

20110063914 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor... Agent: Kabushiki Kaisha Toshiba

20110063915 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage... Agent: Kabushiki Kaisha Toshiba

20110063916 - Non-volatile semiconductor storage device: At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory... Agent: Kabushiki Kaisha Toshiba

20110063917 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes... Agent: Kabushiki Kaisha Toshiba

20110063918 - Identifying at-risk data in non-volatile storage: The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.... Agent:

20110063919 - Memory kink checking: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line.... Agent: Micron Technology, Inc.

20110063920 - Sensing for all bit line architecture in a memory device: Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells... Agent: Micron Technology, Inc.

20110063921 - Circuit arrangement with a column latch and method for operating a column latch: In one embodiment, a circuit arrangement with a column latch has a first terminal (A1) for connection to a bit line (BL) of a nonvolatile memory, a second terminal (A2) connected via a first switchable path (P1) to a reference-potential terminal (VSS) and via a second switchable path (P2) to... Agent: Austriamicrosystems Ag

20110063922 - Nonvolatile semiconductor memory device: Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory... Agent: Kabushiki Kaisha Toshiba

20110063923 - Trench memory structure operation: Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over... Agent: Micron Technology, Inc.

20110063924 - Method of flash memory design with differential cell for better endurance: A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20110063926 - Write through speed up for memory circuit: A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line,... Agent: Lsi Corporation

20110063925 - Semiconductor device and semiconductor package including the same: To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer,... Agent: Elpida Memory, Inc.

20110063927 - Semiconductor device using plural internal operation voltages and data processing system using the same: A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address... Agent: Elpida Memory, Inc.

20110063928 - Semiconductor memory device: A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with... Agent: Panasonic Corporation

20110063929 - Delay line that tracks setup time of a latching element over pvt: A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed... Agent: Qualcomm Incorporated

20110063930 - Subtraction circuits and digital-to-analog converters for semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs... Agent: Micron Technology, Inc.

20110063931 - Interfaces, circuits, and methods for communicating with a double data rate memory device: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer.... Agent: Avago Technologies EnterpriseIP(singapore) Pte. Ltd.

20110063932 - Boosting voltage levels applied to an access control line when accessing storage cells in a memory: A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a... Agent:

20110063933 - Semiconductor device, relief-address-information writing device, and relief-address-information writing method: To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this... Agent: Elpida Memory, Inc.

20110063934 - Memory circuit with multi-sized sense amplifier redundancy: A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of... Agent: Katholieke Universiteit Leuven

20110063935 - Semiconductor device and data processing system comprising semiconductor device: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components,... Agent: Elpida Memory, Inc.

20110063936 - Semiconductor device including plural electrode pads: A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad... Agent: Elpida Memory, Inc.

20110063937 - System and method to compensate for process and environmental variations in semiconductor devices: An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving... Agent:

  
03/10/2011 > patent applications in patent subcategories. listing by industry category

20110058401 - Semiconductor memory device having pad electrodes arranged in plural rows: To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between... Agent: Elpida Memory, Inc.

20110058402 - Semiconductor device having nonvolatile memory elements: A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements... Agent: Elpida Memory, Inc.

20110058403 - Ferro-electric random access memory apparatus: A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end... Agent: Kabushiki Kaisha Toshiba

20110058405 - Memory cell with proportional current self-reference sensing: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second... Agent: Seagate Technology LLC

20110058406 - Resistive memory: The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch... Agent: Micron Technology, Inc.

20110058404 - Variable resistive memory punchthrough access method: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor... Agent: Seagate Technology LLC

20110058407 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of... Agent: Kabushiki Kaisha Toshiba

20110058408 - Memory cell arrangements; memory cell reader; method for determining a memory cell storage state: A memory cell arrangement is provided including a magnetoresistive memory cell; and a frequency determiner configured to determine a spin precession frequency provided by the magnetoresistive memory cell; and a storage state determiner configured to determine the magnetoresistive memory cell storage state of the magnetoresistive memory cell based on the... Agent: Agency For Science, Technology And Research

20110058409 - Mram diode array and access method: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel... Agent: Seagate Technology LLC

20110058411 - Phase change memory system having write driver: A phase change memory system capable of gradually reducing current at the time of writing set data by using a small number of control circuits while occupying a small dimension is disclosed. The phase change memory system includes a memory cell array including a plurality of memory cells, each including... Agent: Hynix Semiconductor Inc.

20110058410 - Semiconductor memory device: A random-access non-volatile semiconductor memory device, which does not use individual gate terminals of transistors of memory cells in order to select individual memory cells for read/write operations performed on the device. The gate terminals of the memory cells are all biased to the same voltage during a read or... Agent: Hitachi, Ltd.

20110058412 - Magnetic stack having assist layer: A magnetic tunnel junction having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation, the ferromagnetic free layer switchable by spin torque. The magnetic tunnel junction includes a ferromagnetic assist layer proximate the free layer, the assist layer... Agent: Seagate Technology LLC

20110058413 - Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then... Agent: Micron Technology, Inc.

20110058414 - Memory with multiple reference cells: A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a... Agent: Macronix International Co., Ltd.

20110058416 - Semiconductor memory device capable of suppressing peak current: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller,... Agent:

20110058417 - Sensing memory cells: Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to... Agent: Micron Technology, Inc.

20110058415 - Systems and methods for increasing bit density in a memory cell: Various embodiments of the present invention provide systems, methods and circuits for memory utilization. As one example, a memory system is disclosed that includes a memory bank and a memory access controller circuit. The memory bank includes a number of default memory cells and a number of redundant memory cells.... Agent: Lsi Corporation

20110058418 - 3d nonvolatile memory device and method for fabricating the same: A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a... Agent:

20110058419 - Multi-chip assembly with optically coupled die: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die... Agent:

20110058420 - Storage apparatus, substrate, liquid container, system, and control method of the storage apparatus: A storage apparatus including a nonvolatile storage section and a control section controlling the nonvolatile storage section, wherein the control section has a detection circuit detecting floating state in at least one of power supply terminal connected to host side power supply terminal to which a power supply voltage is... Agent: Seiko Epson Corporation

20110058422 - Systems and methods for circular buffering control in a memory device: circuits for memories and utilization thereof. As one example, memory devices are disclosed that include a plurality of non-volatile memory blocks, and a memory write circuit. The memory write circuit is operable to write subsets of the plurality of non-volatile memory blocks at locations identified by a pointer, and to... Agent: Lsi Corporation

20110058421 - Systems and methods for peak power and/or emi reduction: Various embodiments of the present invention provide systems, methods and circuits for power management and/or EMI reduction. As one example, a method for memory system access is disclosed that includes providing a first bank of memory; providing a second bank of memory; receiving a memory access request that includes assertion... Agent: Lsi Corporation

20110058423 - Semiconductor memory device and method of programming the same: In an embodiment, a semiconductor memory device including a cell array with NAND strings arranged therein, wherein the device has such a program mode that bit lines and cell's channels of the NAND strings coupled thereto are initially charged in accordance with program data, and then program voltage is applied... Agent: Kabushiki Kaisha Toshiba

20110058424 - Data line management in a memory device: Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program... Agent: Micro Technology, Inc.

20110058425 - Integrated flash memory systems and methods for load compensation: Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage.... Agent: Silicon Storage Technology, Inc.

20110058426 - Nonvolatile semiconductor memory device: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one... Agent: Renesas Electronics Corporation

20110058427 - Flash memory device configured to reduce common source line noise, methods of operating same, and memory system incorporating same: A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL... Agent: Samsung Electronics Co., Ltd.

20110058428 - Semiconductor storage device: According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected... Agent: Kabushiki Kaisha Toshiba

20110058429 - Low power shift register and semiconductor memory device including the same: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift dock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock... Agent:

20110058430 - Voltage regulation method and memory applying thereof: A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written... Agent: Macronix International Co., Ltd.

20110058431 - Method and apparatus for compression of configuration bitstream of field programmable logic: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array... Agent:

20110058432 - Semiconductor integrated circuit: A semiconductor integrated circuit is provided that includes a first pad, a data storage and input/output block configured to store and output data by using a data strobe signal and a clock signal inputted through the first pad, and a timing compensation unit configured to delay the clock signal to... Agent: Hynix Semiconductor Inc.

20110058433 - Latency control circuit, semiconductor memory device including the same, and method for controlling latency: A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for... Agent:

20110058434 - Semiconductor integrated circuit: A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and... Agent: Kabushiki Kaisha Toshiba

20110058435 - Semiconductor memory device comprising sense amplifiers configured to stably amplify data: A semiconductor memory device adjusts a timing interval between the activation of first and second amplifiers in a sense amplifier circuit based on the distance between the sense amplifier circuit and corresponding power supply.... Agent: Samsung Electronics Co., Ltd.

20110058436 - Techniques for sensing a semiconductor memory device: Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a... Agent: Innovative Silicon Isi Sa

20110058437 - Clock generating circuit, semiconductor device including the same, and data processing system: A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a... Agent: Elpida Memory, Inc.

20110058438 - Semiconductor memory device and refresh control method of memory system: c

20110058439 - Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the... Agent:

20110058440 - Apparatus, system, and method for power reduction management in a storage device: An apparatus, system, and method are disclosed for power loss management in a nonvolatile data storage device. A monitor module initiates a power loss mode in the nonvolatile data storage device in response to a primary power source failing to supply electric power above a predefined threshold to the nonvolatile... Agent: Fusion-io, Inc.

20110058441 - Data line driving circuit: A data line driving circuit includes: an operation period signal generation unit configured to generate an operation period signal for determining a write period and a read period in response to a read command or a write command; and a read data line driving unit configured to fix a read... Agent: Hynix Semiconductor Inc.

20110058443 - Latency counter, semiconductor memory device including the same, and data processing system: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes... Agent: Elpida Memory, Inc.

20110058444 - Latency counter, semiconductor memory device including the same, and data processing system: A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected each time a... Agent: Elpida Memory, Inc.

20110058445 - Latency counter, semiconductor memory device including the same, and data processing system: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes... Agent: Elpida Memory, Inc.

20110058442 - Semiconductor device having odt function and data processing system including the same: To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic... Agent: Elpida Memory, Inc.

  
03/03/2011 > patent applications in patent subcategories. listing by industry category

20110051483 - Content addressable memory array: A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of... Agent:

20110051482 - Content addressable memory array programmed to perform logic operations: A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either... Agent:

20110051484 - Low active power content addressable memory: A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary... Agent:

20110051485 - Content addressable memory array writing: A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines... Agent:

20110051486 - Content addressable memory reference clock: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled... Agent:

20110051487 - Read only memory cell for storing a multiple bit value: A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output... Agent:

20110051488 - Semiconductor memory device: A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of... Agent:

20110051489 - Semiconductor memory device: A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input... Agent:

20110051490 - Array architecture and operation for magnetic racetrack memory: A high density memory architecture comprising magnetic racetrack memory and a method of operation. The memory architecture comprises a plurality of magnetic memory structures, each the structure formed of magnetic material; a sensing device associated with each magnetic memory structure; first decoder device initiating a track select signal for activating... Agent:

20110051491 - Ferroelectric random access memory and memory system: Certain embodiments provide a ferroelectric random access memory comprising a first buffer, a second buffer, a third buffer, a first controlling unit, a second controlling unit, a memory cell array, a sense amplifier circuit, and a third controlling unit. The first buffer outputs a first signal changed from a first... Agent:

20110051494 - Memory having tunnel barrier and method for writing and reading information to and from this memory: A resistive memory comprises a tunnel barrier. The tunnel barrier is in contact with a memory material which has a memory property that can be changed by a write signal. Because of the exponential dependence of the tunnel resistance on the parameters of the tunnel barrier, a change in the... Agent:

20110051499 - Method for adjusting a resistive change element using a reference: A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second... Agent:

20110051497 - Method of measuring a resistance of a resistive memory device: A method of measuring a resistance of a memory cell in a resistive memory device can be provided by applying a data write pulse to a selected cell of the resistive memory device, applying a resistance read pulse to the selected cell after a delay time measured from a time... Agent:

20110051500 - Nonvolatile memory element and nonvolatile memory device: A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a... Agent:

20110051493 - Nonvolatile semiconductor memory device: A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting... Agent:

20110051495 - Nonvolatile semiconductor memory device with no decrease in read margin and method of reading the same: According to one embodiment, a plurality of memory cells, each composed of a variable-resistance element and a diode, are arranged at the intersections of a plurality of word lines and a plurality of bit lines. The sense amplifier compares a voltage corresponding to current in a memory cell selected from... Agent:

20110051492 - Resistance change memory device: A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it;... Agent:

20110051496 - Resistive random access memory and the method of operating the same: A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each... Agent:

20110051498 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell, a power supply circuit, an interconnection and a discharging circuit. The memory cell includes a variable resistance element whose resistance varies by application of a voltage. The power supply circuit outputs the voltage to be applied to the... Agent:

20110051501 - Memory control with selective retention: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1... Agent:

20110051502 - Flexible word-line pulsing for stt-mram: A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising... Agent:

20110051503 - Magnetic devices and structures: Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is presented. The magnetic device includes a ferromagnet, an antiferromagnet coupled to the ferromagnet, and a nonmagnetic metal proximate to the ferromagnet. The antiferromagnet provides uniaxial anisotropy... Agent:

20110051504 - Creating short program pulses in asymmetric memory arrays: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a... Agent:

20110051506 - Flexible multi-pulse set operation for phase-change memories: Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the... Agent:

20110051507 - Maintenance process to enhance memory endurance: Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.... Agent:

20110051508 - Multilevel programming of phase change memory: A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable... Agent:

20110051505 - Reducing programming time of a memory cell: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected... Agent:

20110051509 - System and method to manufacture magnetic random access memory: A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source... Agent:

20110051511 - Digital filters with memory: A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The... Agent:

20110051510 - Nonvolatile semiconductor memory device which transfers a plurality of voltages to memory cells and method of writing the same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, a bit line, and a voltage generator. The memory cell array includes each of a plurality of memory cells. Each of the memory cells includes a charge storage layer and a control gate and is capable... Agent:

20110051512 - 3d memory devices decoding and routing systems and methods: 3D memory devices are disclosed, such as those that include multiple two-dimensional tiers of memory cells. Each tier may be fully or partially formed over a previous tier to form a memory device having two or more tiers. Each tier may include strings of memory cells where each of the... Agent:

20110051513 - Methods, devices, and systems for dealing with threshold voltage change in memory devices: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated... Agent:

20110051514 - Nonvolatile memory device, memory system incorporating same, and method of operating same: A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based... Agent:

20110051515 - Nonvolatile semiconductor memory: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile... Agent:

20110051516 - Semiconductor device: A semiconductor device comprises a transistor comprising a gate, a source, a drain, and a gate insulating layer, and an auxiliary line formed over the drain and electrically insulated from the drain. During a turn-off operation of the transistor, voltage to increase a resistance of the drain is supplied to... Agent:

20110051517 - Partial speed and full speed programming for non-volatile memory using floating bit lines: Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage... Agent:

20110051518 - Semiconductor memory device and method of operating the same: A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprises: a nonvolatile memory cell array having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and... Agent:

20110051519 - Novel nand-based hybrid nvm design that integrates nand and nor in 1-die with serial interface: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and... Agent:

20110051521 - Flash memory module and method for programming a page of flash memory cells: A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the... Agent:

20110051520 - Nonvolatile memory device, driving method thereof, and memory system having the same: A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and... Agent:

20110051522 - Method of programming flash memory of the differential cell structures for better endurance: A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method... Agent:

20110051524 - Method and apparatus for operation of a nand-like dual charge retaining transistor nor flash memory device: A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of... Agent:

20110051523 - Small unit internal verify read in a memory device: Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected... Agent:

20110051525 - Power saving method and circuit thereof for a semiconductor memory: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first... Agent:

20110051526 - Method for programming a memory structure: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure... Agent:

20110051527 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected... Agent:

20110051528 - Dynamic semiconductor memory with improved refresh mechanism: Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at... Agent:

20110051531 - Data output control circuit of a double data rate (ddr) synchronous semiconductor memory device responsive to a delay locked loop (dll) clock: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is... Agent:

20110051529 - Memory device: Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The... Agent:

20110051530 - Semiconductor memory device and method of updating data stored in the semiconductor memory device: The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.... Agent:

20110051533 - Internal voltage generator circuit and semiconductor memory device using the same: An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and... Agent:

20110051532 - Reference level generation with offset compensation for sense amplifier: An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.... Agent:

20110051534 - Semiconductor storage device and its control method: A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which... Agent:

20110051535 - Fin-type device system and method: A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at... Agent:

20110051537 - Address multiplexing in pseudo-dual port memory: A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to... Agent:

20110051536 - Signal delay circuit and a semiconductor memory device having the same: A signal delay circuit that includes a delay unit configured to delay an input signal for a first delay time and output the delayed input signal; a first delay adjusting unit configured to adjust the first delay time according to a variation in a level of a power supply voltage... Agent:

20110051538 - Methods and memory devices for repairing memory cells: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality... Agent:

20110051540 - Method and structure for sram cell trip voltage measurement: A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor... Agent:

20110051539 - Method and structure for sram vmin/vmax measurement: A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor... Agent:

20110051541 - Semiconductor device: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a... Agent:

20110051542 - Memory circuits, systems, and methods for accessing the memory circuits: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to... Agent:

20110051543 - Sense amplifier and semiconductor integrated circuit using the same: A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is... Agent:

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