|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
02/2011 | Recent | 14: | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval February patent applications/inventions, industry category 02/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/24/2011 > patent applications in patent subcategories. patent applications/inventions, industry category
20110044084 - Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each... Agent: Volentine & Whitt PLLC
20110044085 - Serially interfaced random access memory: A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented... Agent: Wolff & Samson PC Attn: Jeffrey M. Weinick
20110044086 - Optical memory device and method therefor: A nonvolatile memory device and method using phase changes in a substrate to alter optical properties of the substrate for the purpose of data storage. The memory device includes a substrate containing a phase change material having phases comprising amorphous and crystalline phases. The phase change material has optical properties... Agent: Hartman & Hartman, P.C.
20110044087 - Semiconductor memory device: A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end... Agent: Knobbe Martens Olson & Bear LLP
20110044089 - Method for manufacturing a resistive switching memory cell comprising a nickel oxide layer operable at low-power and memory cells obtained thereof: A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20110044093 - Non-volatile memory devices including stacked nand-type resistive memory cell strings: A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality... Agent: Myers Bigel Sibley & Sajovec
20110044090 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines and second lines intersecting each other and a plurality of memory cells connected at intersections of the plurality of first lines and second lines; and a first line control circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110044092 - Semiconductor memory device: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an... Agent: Miles & Stockbridge PC
20110044091 - Two-terminal nanotube devices and systems and methods of making same: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of... Agent: Wilmerhale/boston
20110044088 - Variable resistance nonvolatile storage device and method of forming memory cell: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is... Agent: Wenderoth, Lind & Ponack L.L.P.
20110044094 - 10t sram cell with near dual port functionality: An integrated circuit including a ram array with SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in... Agent: Texas Instruments Incorporated
20110044095 - Semiconductor memory device: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20110044096 - Magnetic tunnel junction structure: In a particular illustrative embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The bottom electrode is coupled to a bottom surface of the fixed layer and extends along at least... Agent: Qualcomm Incorporated
20110044098 - Nonvolatile memory cells having phase changeable patterns therein for data storage: A nonvolatile memory cell includes a substrate and a phase changeable pattern configured to retain a state of the memory cell, on the substrate. An electrically insulating layer is provided, which contains a first electrode therein in contact with the phase changeable pattern. The first electrode has at least one... Agent: Myers Bigel Sibley & Sajovec
20110044097 - Phase change memory and operation method of the same: An operation method of phase change memory (PCM) is provided. The operation method includes applying a RESET pulse to a phase change material of the PCM, wherein the RESET pulse has a profile with a first tail such that a plurality of seeds are formed in the phase change material.... Agent: J C Patents
20110044099 - Heat assisted magnetic write element:
20110044100 - Flash memory cell and method for operating the same: A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor... Agent: Hamre, Schumann, Mueller & Larson, P.C.
20110044101 - Method and system of finding a read voltage for a flash memory: A method and system of finding a read voltage for a flash memory is disclosed. Data are read from array cells of the flash memory with a default read voltage, and a recorded state bit number that is recorded during programming is also read. Determine an optimal read voltage if... Agent: Squire, Sanders & Dempsey L.L.P.
20110044104 - Nonvolatile memory device and system, and method of programming a nonvolatile memory device: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or... Agent: Volentine & Whitt PLLC
20110044105 - Nonvolatile memory device and system, and method of programming a nonvolatile memory device: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N−1)th page programming operations, using an incremental step pulse programming (ISPP) method, to program first through (N−1)th data pages in the MLC memory cells, where each of the first through (N−1)th page... Agent: Volentine & Whitt PLLC
20110044106 - Nonvolatile semiconductor memory and data reading method: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110044103 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110044102 - Selective memory cell program and erase: Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even... Agent: Vierra Magen/sandisk Corporation
20110044108 - Flash memory device and program method of flash memory device using different voltages: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least... Agent: Volentine & Whitt PLLC
20110044107 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device has a drawing wiring drawn out from one end of a gate electrode and connected to a terminal, and has another drawing wiring drawn out from the other end of the gate electrode and connected to a terminal. Lengths of the two drawing wirings are... Agent: Posz Law Group, PLC
20110044109 - Non-volatile static random access memory (nvsram) device: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter... Agent: North America Intellectual Property Corporation
20110044110 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with... Agent: Law Office Of Alan W. Cannon
20110044111 - Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices: The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110044112 - Semiconductor device: A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20110044113 - Nonvolatile memory device, method for programming same, and memory system incorporating same: A nonvolatile memory device performs a program operation on selected memory cells by determining a level of a program voltage based on a degree of deterioration of the memory cells, and executing the program operation using the program voltage.... Agent: Volentine & Whitt PLLC
20110044114 - Apparatus and method for bit lines discharging and sensing: Some embodiments include first bit lines coupled to a first junction bus and second bit lines coupled to a second junction bus. Such embodiments can also include a first network to discharge at least one of the first bit lines through the first junction bus and to discharge at least... Agent: Schwegman, Lundberg & Woessner / Atmel
20110044115 - Non-volatile memory using pyramidal nanocrystals as electron storage elements: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its... Agent: Docket Clerk
20110044116 - System and method for capturing data signals using a data strobe signal: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to... Agent: Dorsey & Whitney LLP Intellectual Property Department
20110044117 - Semiconductor memory device: A semiconductor memory device includes an enable signal generating unit for generating an enable signal in response to an active signal and an internal voltage driving unit driven by the active signal and the enable signal, wherein the internal voltage driving unit drives an internal voltage by comparing the internal... Agent: Cooper & Dunham, LLP
20110044118 - Semiconductor device having variable parameter selection based on temperature and test method: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures... Agent: Foley & Lardner LLP
20110044119 - Semiconductor device having variable parameter selection based on temperature and test method: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures... Agent: Foley & Lardner LLP
20110044120 - Semiconductor device: A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data transmission line to a first potential at the time of a first write mode in which data masking is not performed. The... Agent: Sughrue Mion, PLLC
20110044121 - Semiconductor memory device having device for controlling bit line loading and improving sensing efficiency of bit line sense amplifier: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier... Agent: Lee & Morse, P.C.
20110044122 - Word line driving apparatus: A source potential of a pull-up transistor is increased after predetermined time from a rising timing of a word line selection command signal. To this end, a condenser is provided to couple the source potential and gate potential of the pull-up transistor. Preferably a gate potential control transistor that controls... Agent: Studebaker & Brackett PC
20110044123 - Circuit and methods for eliminating skew between signals in semicoductor integrated circuit: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data... Agent: Volentine & Whitt PLLC02/17/2011 > patent applications in patent subcategories. patent applications/inventions, industry category
20110038194 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110038196 - Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof: In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed... Agent: Winstead PC
20110038195 - Method for resetting a resistive change memory element: A method of resetting a resistive change memory element is disclosed. The method comprises performing a series of programming operations—for example, a programming pulse of a predetermined voltage level and pulse width—on a resistive change memory element in order to incrementally increase the resistance of the memory element above some... Agent: Wilmerhale/new York
20110038197 - Variable resistance memory and memory system including the same: A variable resistance memory array includes at least one variable resistance memory cell, wherein each variable resistance memory cell includes a well having a first type; and a cell structure on the well, the cell structure including a structure having a second type different from the first type and a... Agent: Lee & Morse, P.C.
20110038198 - Electronic devices based on current induced magnetization dynamics in single magnetic layers: The present invention generally relates to magnetic devices used in memory and information processing applications, such as giant magneto-resistance (GMR) devices and tunneling magneto-resistance devices. More specifically, the present invention is directed to a single ferromagnetic layer device in which an electrical current is used to control and change magnetic... Agent: Foley & Lardner LLP
20110038199 - Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the... Agent: Cantor Colburn LLP-ibm Yorktown
20110038200 - Gate drive voltage boost schemes for memory array ii: Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and... Agent: Saile Ackerman LLC
20110038201 - Semiconductor integrated circuit: There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110038202 - Control driver for memory and related method: A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of... Agent: North America Intellectual Property Corporation
20110038203 - Reduction of read disturb errors in nand flash memory: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system utilizing modified or extra FLASH memory cells.... Agent: Locke Lord Bissell & Liddell LLP
20110038207 - Flash memory device, programming and reading methods performed in the same: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from... Agent: Volentine & Whitt PLLC
20110038204 - Method and apparatus for increasing memory programming efficiency through dynamic switching of sense amplifiers: A method and apparatus are described that efficiently program charge-trapping memory cells by dynamically switching sense amplifiers and corresponding drivers depending upon data to be programmed. When a number of sense amplifier/drivers can be operated simultaneously, cells to be programmed to a same level are selected and programmed simultaneously employing... Agent: Stout, Uxa, Buyan & Mullins LLP
20110038209 - Method and system for adaptively finding reference voltages for reading data from a mlc flash memory: A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to... Agent: Squire, Sanders & Dempsey L.L.P.
20110038208 - Method of reading dual-bit memory cell: A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a... Agent: Bacon & Thomas, PLLC
20110038205 - Method of reducing bit error rate for a flash memory: A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages... Agent: Squire, Sanders & Dempsey L.L.P.
20110038206 - Semiconductor storage device to correct threshold distribution of memory cells by rewriting and method of controlling the same: According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110038210 - Electrically erasable programmable read-only memory (eeprom) cell and methods for forming and reading the same: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first... Agent: F. Chau & Associates, LLC
20110038211 - Semiconductor devices and methods of fabricating the same: A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first... Agent: Lee & Morse, P.C.
20110038212 - Controller and non-volatile semiconductor memory device: A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110038214 - Gate-separated type flash memory with shared word line: A gate-separated type flash memory with a shared word line includes: a semiconductor substrate, on which a source electrode area and a drain electrode area are separately arranged; a word line, which is arranged between the source electrode area and the drain electrode area; a first storage bit unit, which... Agent: Rosenberg, Klein & Lee
20110038213 - Multi-dot flash memory: A multi-dot flash memory set potentials of bit lines being disposed at a left side of a selected floating gate to V2(1)>V2(2)>V2(3)> . . . and set potentials of bit lines being disposed at a right side of the selected floating gate to V1(1)<V1(2)<V1(3)< . . . . Where V2(1)... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110038215 - Non-volatile memory device and operating method of the same: A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias voltage based on the sensed temperature.... Agent: Ip & T Group LLP
20110038216 - Method for reading memory cell: Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data.... Agent: Quintero Law Office, PC
20110038217 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a... Agent: Round Lerner, David, Littenberg, Krumholz & Mentlik, LLP
20110038218 - Memory chip and method for operating the same: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110038219 - Apparatus and method for increasing data line noise tolerance: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current... Agent: Leffert Jay & Polglaze, P.A.
20110038220 - Sense amplifier and semiconductor memory device including the same: A sense amplifier includes a first inverter having an input terminal connected to a first line and an output terminal connected to a second line, and a second inverter having an input terminal connected to the second line and an output terminal connected to the first line, wherein an NMOS... Agent: Ip & T Group LLP
20110038221 - Semiconductor memory devices, controllers, and semiconductor memory systems: A semiconductor memory system includes a controller and a memory device that are optical-interconnected. The controller includes a control logic configured to generate a control signal for controlling the memory device and a transmitter configured to convert the control signal into an optical signal, and output the optical signal. The... Agent: Harness, Dickey & Pierce, P.L.C02/10/2011 > patent applications in patent subcategories. patent applications/inventions, industry category
20110032740 - Memory system having improved signal integrity: A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting... Agent: Stanzione & Kim, LLP
20110032741 - Semiconductor memory device: The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input... Agent: Scully Scott Murphy & Presser, PC
20110032742 - One-time programmable memory cell with shiftable threshold voltage transistor: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted... Agent: Farjami & Farjami LLP
20110032743 - Colloidal-processed silicon particle device: Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and separated from the first electrode by a spacing. A colloidal-processed Si particle layer overlies... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski
20110032744 - Recording method for magnetic memory device: [Solving Means] A recording method for a magnetic memory device includes applying, when recording one piece of information, one or more main pulses and one or more sub-pulses in the same direction and applying the one or more sub-pulses after the one or more main pulses, the one or more... Agent: Snr Denton US LLP
20110032749 - Nand based resistive sense memory cell architecture: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110032745 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110032746 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110032748 - Polarity dependent switch for resistive sense memory: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a... Agent: Campbell Nelson Whipps, LLC
20110032747 - Variable resistance memory devices and methods of programming variable resistance memory devices: A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.... Agent: Volentine & Whitt PLLC
20110032750 - Semiconductor memory device comprising a plurality of static memory cells: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power... Agent: Mcdermott Will & Emery LLP
20110032751 - Semiconductor device: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to... Agent: Miles & Stockbridge PC
20110032753 - Memory cells including resistance variable material patterns of different compositions: A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected... Agent: Volentine & Whitt PLLC
20110032752 - Multi-level memory device using resistance material: A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same... Agent: Myers Bigel Sibley & Sajovec
20110032754 - Phase change memory adaptive programming: Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range,... Agent: Schwegman, Lundberg & Woessner/micron
20110032755 - Voltage boosting in mram current drivers: Disclosed is a current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor M18 to control driver currents from the current driver circuit, and wherein the... Agent: Hahn And Moodley, LLP
20110032756 - Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of... Agent: Law Office Of Alan W. Cannon
20110032757 - Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage: Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements... Agent: Vierra Magen/sandisk Corporation
20110032759 - Memory system and related method of programming: A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each... Agent: Volentine & Whitt PLLC
20110032760 - Method of reading data in semiconductor memory device with charge accumulation layer: According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110032761 - Methods of erase verification for a flash memory device: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase... Agent: Knobbe Martens Olson & Bear LLP
20110032758 - Nonvolatile memory device outputting analog signal and memory system having the same: A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation... Agent: Harness, Dickey & Pierce, P.L.C
20110032762 - Multi-dot flash memory: According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110032763 - Semiconductor devices including first and second bit lines: In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line.... Agent: Myers Bigel Sibley & Sajovec
20110032764 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20110032765 - Memory formed by using defects: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20110032766 - N-channel sonos non-volatile memory for embedded in logic: A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on... Agent: Raj Abhyanker, P.C.
20110032768 - Erase degradation reduction in non-volatile memory: Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.
20110032770 - High temperature methods for enhancing retention characteristics of memory devices: Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells,... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20110032767 - Semiconductor memory, system, and method of controlling semiconductor memory: A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft... Agent: Arent Fox LLP
20110032769 - System for verifying non-volatile storage using different voltages: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for... Agent: Vierra Magen/sandisk Corporation
20110032771 - Memory and reading method thereof: A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110032772 - Semiconductor device with vertical gate and method for fabricating the same: A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured... Agent: Ip & T Group LLP
20110032773 - Power supplies in flash memory devices and systems: Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an... Agent: Mosaid Technologies Incorporated
20110032774 - Semiconductor memory with improved memory block switching: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are... Agent: Vierra Magen/sandisk Corporation
20110032775 - Memory devices and method for driving a signal line to a known signal level: A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are... Agent: Trask Britt, P.C./ Micron Technology
20110032776 - Memory circuit and voltage detection circuit including the same: Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.
20110032777 - Semiconductor memory circuit: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20110032778 - Semiconductor memory device: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell... Agent: Turocy & Watson, LLP
20110032779 - Semiconductor memory device: A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The... Agent: Mcdermott Will & Emery LLP
20110032780 - Semiconductor device: The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second... Agent: Mcginn Intellectual Property Law Group, PLLC
20110032781 - Memory device and memory control method: The embodiments of the present invention disclose a memory device having a fast and shared redundancy decision scheme and a memory control method. The memory device includes an address receiver, a command receiver, a command controller, a row address generator, a column address generator and a shared redundancy decision circuit.... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20110032782 - Test method and device for memory device: Provided is a test method for a memory device including a plurality of storage regions and an SPO recovery unit. The test method stores data in the plurality of storage regions. The test method shuts off supply of power to the memory device and resupplies the power to the memory... Agent: Harness, Dickey & Pierce, P.L.C
20110032783 - Semiconductor storage apparatus, and method and system for boosting word lines: A semiconductor storage apparatus includes: a word line coupled to a cell transistor; a first capacitor having a first end coupled to the word line; a boost driver coupled to a second end of the first capacitor; a voltage-drop circuit configured to generate a given voltage drop between a first... Agent: Arent Fox LLP
20110032784 - Semiconductor memory with multiple wordline selection: A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting... Agent: Smart & Biggar
20110032786 - Sub-word line driver circuit and semiconductor memory device having the same: A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active... Agent: Muir Patent Consulting, PLLC
20110032785 - Wordline driver, memory device including the same and method of driving a wordline: A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable... Agent: Muir Patent Consulting, PLLC
20110032787 - Input buffer circuit, semiconductor memory device and memory system: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal... Agent: Volentine & Whitt PLLC02/03/2011 > patent applications in patent subcategories. patent applications/inventions, industry category
20110026287 - Method and apparatus for address allotting and verification in a semiconductor device: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20110026288 - Content addressable memory: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair.... Agent: Mcdermott Will & Emery LLP
20110026289 - Cell structure for dual port sram: A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the... Agent: Duane Morris LLP (tsmc)IPDepartment
20110026290 - Semiconductor device having memory cell array divided into plural memory mats: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of... Agent: Sughrue Mion, PLLC
20110026291 - System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory: Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element,... Agent: Unity Semiconductor Corporation
20110026294 - Information recording and reproducing device: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first state and a second state with a resistance higher... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110026293 - Semiconductor device: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip... Agent: Sughrue Mion, PLLC
20110026292 - Semiconductor device having hierarchically structured bit lines and system including the same: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit... Agent: Mcginn Intellectual Property Law Group, PLLC
20110026295 - Semiconductor memory: To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output... Agent: Foley And Lardner LLP Suite 500
20110026296 - Nonvolatile optical memory element, memory device, and reading method thereof: A nonvolatile optical memory element in which a ferromagnetic body is provided on a semiconductor causes such a problem that in a case where magnetization of the ferromagnetic body is read by light, magneto-optical response becomes very small when the ferromagnetic body is small in volume. The present invention provides... Agent: Squire, Sanders & Dempsey L.L.P.
20110026304 - Memory cell: Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using... Agent: Brooks, Cameron & Huebsch , PLLC
20110026298 - Method of driving storage device: Provided is a method of driving a storage device capable of improving reliability of data write in the storage device including a variable resistance element. At the time of data write operation, a plurality of write pulses having shapes different from each other are applied between electrodes 21 and 24... Agent: K&l Gates LLP
20110026305 - Non-volatile memory array with resistive sense element block erase and uni-directional write: A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110026299 - Nonvolatile semiconductor memory device and method of data write/data erase therein: A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110026306 - Resistance variable memory device reducing word line voltage: A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and... Agent: Volentine & Whitt PLLC
20110026300 - Resistive memory device and operating method thereof: A resistive memory device includes: a storage element; a first line and a second line; a first drive controller; and a second drive controller.... Agent: Rader Fishman & Grauer PLLC
20110026301 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes first select line groups laminated in a vertical direction, and each including first select lines extending in a first direction, second select line groups alternately laminated with the first select line groups, and each including second select lines extending in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110026297 - Variable and reversible resistive element, non-volatile memory device and methods for operating and manufacturing the non-volatile memory device: A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes... Agent: Brian M. Mcinnis
20110026303 - Variable resistance memory device and system thereof: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared... Agent: Harness, Dickey & Pierce, P.L.C
20110026307 - Variable resistive memory punchthrough access method: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor... Agent: Campbell Nelson Whipps, LLC
20110026302 - Write verify method for resistive random access memory: Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting... Agent: Campbell Nelson Whipps, LLC
20110026308 - Cell structure for dual port sram: A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the... Agent: Duane Morris LLP (tsmc)IPDepartment
20110026311 - Memory device using sram circuit: A one read/two write SRAM circuit of which memory cell size is small, and high-speed operation is possible. The SRAM circuit includes first and second flip-flop circuits which are connected in parallel to a common write word line; a first write control circuit which is connected to said first flip-flop... Agent: Staas & Halsey LLP
20110026310 - Power-saving semiconductor memory: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.... Agent: Fiala & Weaver P.l.l.c. C/o Cpa Global
20110026309 - Self-timed write boost for sram cell with self mode control: A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners... Agent: Stmicroelectronics, Inc.
20110026312 - Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor: A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal... Agent: Mcginn Intellectual Property Law Group, PLLC
20110026315 - Single-event upset immune static random access memory cell circuit, system, and method: A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain... Agent: Bae Systems
20110026314 - Static memory device with five transistors and operating method: At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of... Agent: Slater & Matsil, L.L.P.
20110026313 - Transistor-based memory cell and related operating methods: A loadless static random access memory cell is provided. The memory cell includes four transistors. The first transistor has a gate terminal corresponding to a word line of the memory cell, a source/drain terminal corresponding to a first bit line of the memory cell, and a drain/source terminal corresponding to... Agent: Ingrassia Fisher & Lorenz, P.C. (gf)
20110026316 - Magnetoresistive memory elements with separate read and write current paths: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer.... Agent: Campbell Nelson Whipps, LLC
20110026317 - Spin-transfer torque memory self-reference read and write assist methods: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. A magnetic field is applied... Agent: Campbell Nelson Whipps, LLC
20110026318 - Iterative write pausing techniques to improve read latency of memory systems: Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a... Agent: Cantor Colburn LLP-ibm Yorktown
20110026319 - Non-volatile semiconductor memory circuit and method of controlling the same: A non-volatile semiconductor memory circuit for use in compensating for time dependent resistive changes in phase change memory cells is presented. The non-volatile semiconductor memory circuit includes a control signal generation unit and a sensing block. The control signal generation unit is configured to provide a control signal having a... Agent: Ladas & Parry LLP
20110026321 - Magnetic memory with porous non-conductive current confinement layer: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer... Agent: Campbell Nelson Whipps, LLC
20110026322 - Recording method for magnetic memory device: m
20110026320 - Staggered magnetic tunnel junction: A staggered magnetic tunnel junction includes a free magnetic layer extending in a lateral direction between a first end portion and an opposing second end portion and a tunneling barrier disposed between a reference magnetic layer and the first end portion and forming a magnetic tunnel junction. Current flows through... Agent: Campbell Nelson Whipps, LLC
20110026323 - Gated diode memory cells: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate... Agent: F. Chau & Associates, LLC Frank Chau
20110026325 - method of programming a multi level cell: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the... Agent: Townsend And Townsend And Crew, LLP
20110026326 - Memory system including flash memory and method of operating the same: A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with... Agent: Volentine & Whitt PLLC
20110026327 - Bit-line connections for non-volatile storage: Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One... Agent: Vierra Magen/sandisk Corporation
20110026330 - Program method of flash memory device: In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string... Agent: Townsend And Townsend And Crew, LLP
20110026329 - Semiconductor device using charge pump circuit: A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element.... Agent: Sughrue Mion, PLLC
20110026328 - System and method of maintaining data integrity in a flash storage device: A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage... Agent: Mcdermott Will & Emery LLP
20110026331 - Program voltage compensation with word line bias change to suppress charge trapping in memory: Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can... Agent: Vierra Magen/sandisk Corporation
20110026324 - Method for programming a floating gate: The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.... Agent: Michael T. Konczal, Patent Attorney
20110026332 - Semiconductor memory device and its operation method: Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a... Agent: Rader Fishman & Grauer PLLC
20110026333 - Bulk bias voltage generating device and semiconductor memory apparatus including the same: A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external... Agent: Echelon Law Group, PC
20110026334 - Bidirectional equalizer with cmos inductive bias circuit: An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as... Agent: Volentine & Whitt PLLC
20110026335 - Power-up signal generation circuit: A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of... Agent: William Park & Associates Ltd.
20110026336 - Data storage using read-mask-write operation: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110026337 - Data input/output circuit and semiconductor memory apparatus including the same: A circuit includes a data input/output unit configured to connect to a first memory bank and a second memory bank. The data input/output unit includes a data switching unit configured to be selectively coupled with the first or second memory bank in response to a bank selection signal, and an... Agent: Echelon Law Group, PC
20110026338 - Redundancy circuit of semiconductor memory: A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of... Agent: Echelon Law Group, PC
20110026343 - Bist ddr memory interface circuit and method for testing the same: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test... Agent: Texas Instruments Incorporated
20110026340 - Memory test circuit, semiconductor integrated circuit and memory test method: A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundancy portion as... Agent: Foley And Lardner LLP Suite 500
20110026342 - Multi-port memory device: A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode;... Agent: Ip & T Group LLP
20110026341 - Semiconductor memory apparatus: A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test.... Agent: William Park & Associates Ltd.
20110026339 - Semiconductor memory device performing refresh operation and method of testing the same: A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and... Agent: Mcginn Intellectual Property Law Group, PLLC
20110026344 - Data control circuit: The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line... Agent: Ladas & Parry LLP
20110026345 - Precharge control circuits and methods for memory having buffered write commands: Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory... Agent: Dorsey & Whitney LLP Intellectual Property Department
20110026347 - Differential sense amplifier: A differential sense amplifier can perform data sensing using a very low supply voltage.... Agent: Fish & Richardson P.C. (sv)
20110026346 - Self-timed low power sense amplifier: A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to... Agent: Seed Intellectual Property Law Group PLLC
20110026348 - Semiconductor device having hierarchically structured bit lines and system including the same: A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch... Agent: Mcginn Intellectual Property Law Group, PLLC
20110026349 - Circuit for compensating temperature detection range of semiconductor memory apparatus: A circuit for compensating a temperature measurement range of a semiconductor memory apparatus is presented. The circuit includes an oscillator, a temperature variable pulse generating unit, a counter, and an output controlling unit. The counter enable signal generating unit inputs a temperature pulse and outputs a counter enable signal corresponding... Agent: Ladas & Parry LLP
20110026350 - Resettable memory apparatuses and design: In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a... Agent: Blakely Sokoloff Taylor & Zafman LLP
20110026353 - Data refresh for non-volatile storage: Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored... Agent: Vierra Magen/sandisk Corporation
20110026351 - Method of reducing current of memory in self-refreshing mode and related memory: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a... Agent: North America Intellectual Property Corporation
20110026352 - Method of reducing current of memory in self-refreshing mode and related memory: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a... Agent: North America Intellectual Property Corporation
20110026354 - Current leakage reduction: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20110026355 - Interface circuit and semiconductor device incorporating same: An interface circuit includes an input/output terminal, a clock generator, a set of multiple data ports, and a data port selector. The input/output terminal is connected to the external circuit to receive a data signal. The clock generator generates a series of multiple phase-shifted clock signals based on a basic... Agent: Cooper & Dunham, LLPPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20141113:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 0.88007 seconds