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Static information storage and retrieval January recently filed with US Patent Office 01/11Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/27/2011 > patent applications in patent subcategories. recently filed with US Patent Office
20110019455 - Low cost high density rectifier matrix memory: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.... Agent: Goodwin Procter LLP Patent Administrator
20110019456 - Sense amplifier with shielding circuit: A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110019457 - Flash memory: A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad,... Agent: Jackson Intellectual Property Group PLLC
20110019458 - Memory circuits, systems, and methods for routing the memory circuits: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20110019459 - Three-dimensional mask-programmable read-only memory with reserved space: The present invention discloses a three-dimensional mask-programmable read-only memory with reserved space (3D-MPROMRS). It is released in a sequence of versions. In the original version, its storage space comprises an initial-release space and a reserved space. The initial-release space stores the multimedia files from the initial release. The reserved space,... Agent: Guobiao Zhang
20110019460 - Memory circuits, systems, and fabrication methods thereof: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20110019461 - F-sram power-off operation: A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable... Agent: Texas Instruments Incorporated
20110019462 - Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019463 - Static random access memories and access methods thereof: A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110019464 - Smart well assisted sram read and write: An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases... Agent: Texas Instruments Incorporated
20110019465 - Magnetic tunnel junction with compensation element: A magnetic tunnel junction having a compensation element is disclosed. The magnetic tunnel junction includes a synthetic antiferromagnetic reference element, and a synthetic antiferromagnetic compensation element having an opposite magnetization moment to a magnetization moment of the synthetic antiferromagnetic reference element. A free magnetic layer is between the synthetic antiferromagnetic... Agent: Campbell Nelson Whipps, LLC
20110019466 - Stuck-at defect condition repair for a non-volatile memory cell: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110019467 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the... Agent: Dugan & Dugan, PC
20110019468 - Non-linear conductor memory: A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that... Agent: Goodwin Procter LLP Patent Administrator
20110019469 - Semiconductor memory: A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019471 - Nonvolatile memory with correlated multiple pass programming: A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size,... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20110019470 - Nonvolatile semiconductor memory device: A semiconductor memory device, in which a multi-bit region including multi-bit memory cells that store data of two or more bits and a region including memory cells that store data of bits that are less than the bits of the data stored in the multi-bit memory cells are installed, is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019472 - Nonvolatile semiconductor memory device and programming method thereof: A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage... Agent: F. Chau & Associates, LLC
20110019473 - Memory array and method of operating one of a plurality of memory cells: An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of... Agent: Jianq Chyun Intellectual Property Office
20110019474 - Flash memory device with redundant columns: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality... Agent: Knobbe Martens Olson & Bear LLP
20110019475 - Interleaved flash storage system and method: A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally,... Agent: Mcdermott Will & Emery LLP
20110019477 - Nand type flash memory: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019476 - Nonvolatile memory device and programming method thereof: A nonvolatile memory device is provided which includes a plurality of memory blocks, a bias block and a control logic block. The memory blocks are formed in wells, respectively. The bias block biases a well of a selected memory block. The control logic block controls the bias block to pre-charge... Agent: Stanzione & Kim, LLP
20110019478 - Sensing of memory cells in nand flash: An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash... Agent: Leffert Jay & Polglaze, P.A.
20110019480 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; a first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer to electrically connect the first and second semiconductor pillars; a connection portion conductive layer opposing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019479 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory... Agent: Hunton & Williams LLP Intellectual Property Department
20110019481 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line... Agent: Hunton & Williams LLP Intellectual Property Department
20110019482 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory... Agent: Hunton & Williams LLP Intellectual Property Department
20110019483 - Adaptive erase and soft programming for memory: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and... Agent: Vierra Magen/sandisk Corporation
20110019484 - Non-volatile memory and method with improved sensing having bit-line lockout control: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20110019485 - Non-volatile memory and method with shared processing for an aggregate of read/write circuits: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20110019486 - Semiconductor memory device and programming method thereof: A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among... Agent: Stanzione & Kim, LLP
20110019488 - Double-gate floating-body memory device: A memory device is provided comprising a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second insulated gates each comprising a gate electrode. A control circuit is arranged to program the state of said floating body to have an... Agent: HowardIPLaw Group
20110019487 - Apparatus and method for detecting word line leakage in memory devices: According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the... Agent: Townsend And Townsend And Crew, LLP
20110019489 - Apparatus and method for data strobe and timing variation detection of an sdram interface: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into... Agent: Bacon & Thomas, PLLC
20110019491 - Redundancy system for non-volatile memory: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell... Agent: Borden Ladner Gervais LLP Anne Kinsman
20110019490 - Semiconductor memory: A semiconductor storage device includes a memory cell array that stores data and includes a plurality of memory cells two dimensionally arrayed on row and column lines extending along row and column directions, at least one of the memory cells assigned to a redundant memory cell having a lager area... Agent: Staas & Halsey LLP
20110019492 - Test device and test method for resistive random access memory and resistive random access memory device: A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110019493 - Semiconductor memory device: Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line... Agent: Mcginn Intellectual Property Law Group, PLLC
20110019494 - Method of manufacturing semiconductor device and semiconductor device: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is... Agent: Young & Thompson
20110019495 - Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)01/20/2011 > patent applications in patent subcategories. recently filed with US Patent Office
20110013442 - Using storage cells to perform computation: An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment... Agent: Daniel J Swirsky
20110013444 - Low leakage rom architecure: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The... Agent: Evergreen Valley Law Group
20110013443 - Novel high speed two transistor/two bit nor read only memory: A mask programmable NOR ROM circuit includes serially connected ROM transistors. A drain of a topmost ROM transistor is connected to a bit line and a source of a bottommost ROM transistor is connected to a source line. A source of one ROM transistor is solely connected with a drain... Agent: Saile Ackerman LLC
20110013445 - Bias temperature instability-influenced storage cell: In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage... Agent: Ibm Corporation
20110013446 - Refresh circuitry for phase change memory: A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20110013447 - Semiconductor device: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which... Agent: Miles & Stockbridge PC
20110013448 - Magnetic element with a fast spin transfer torque writing procedure: A magnetic tunnel junction, comprising a reference layer having a fixed magnetization direction, a first storage layer having a magnetization direction that is adjustable relative to the magnetization direction of the reference layer by passing a write current through said magnetic tunnel junction, and an insulating layer disposed between said... Agent: Pearne & Gordon LLP
20110013449 - Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20110013450 - Method for adaptive setting of state voltage levels in non-volatile memory: A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including... Agent: Vierra Magen/sandisk Corporation
20110013451 - Non-volatile memory device with both single and multiple level cells: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single... Agent: Round Lerner, David, Littenberg, Krumholz & Mentlik, LLP
20110013452 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110013453 - Nonvolatile memory device including circuit formed of thin film transistors: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.... Agent: Mcdermott Will & Emery LLP
20110013454 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110013455 - Non-volatile memory serial core architecture: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors.... Agent: Borden Ladner Gervais LLP Anne Kinsman
20110013456 - Semiconductor memory device capable of reducing chip size: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110013458 - Memory devices supporting simultaneous programming of multiple cells and programming methods thereof: Some embodiments of the present invention provide methods of programming memory devices that include an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines. In some method embodiments, potentials of the vertical... Agent: Myers Bigel Sibley & Sajovec
20110013457 - Nonvolatile memory devices and programming methods thereof in which a program inhibit voltage is changed during programming: Provided are nonvolatile memory devices and programming methods thereof. A non-volatile memory device is programmed by performing a plurality of programming loops on memory cells in a memory cell array and changing a program inhibit voltage applied to bit lines of the memory cells that have completed programming while performing... Agent: Myers Bigel Sibley & Sajovec
20110013460 - Dynamically adjustable erase and program levels for non-volatile memory: Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify... Agent: Vierra Magen/sandisk Corporation
20110013459 - Method of programming/erasing the nonvolatile memory: A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to... Agent: North America Intellectual Property Corporation
20110013461 - Non-volatile semiconductor storage device: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110013462 - Method for operating memory: A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110013463 - Method of forming memory devices by performing halogen ion implantation and diffusion processes: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process... Agent: Wells St. John P.s.
20110013464 - Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device: The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low... Agent: Harness, Dickey & Pierce, P.L.C
20110013465 - Integrators for delta-sigma modulators: Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.... Agent: Michael G. Fletcher Fletcher Yoder
20110013466 - Semiconductor apparatus and data reading method: A semiconductor device includes multiple memory cells, a first and second digit lines, where either of them is coupled to the memory cell to be read, a sense amplifier having a first and second sense nodes that are respectively connected to the first and second digit lines, a first switch... Agent: Foley And Lardner LLP Suite 500
20110013467 - System and method for reading memory: A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the... Agent: Henneman & Associates, PLC
20110013468 - Semiconductor memory device and method of controlling same: A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects an output signal that... Agent: Knobbe Martens Olson & Bear LLP
20110013469 - Redundancy circuits and semiconductor memory devices: A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has... Agent: Harness, Dickey & Pierce, P.L.C
20110013470 - Structure and method for screening srams: An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM... Agent: Texas Instruments Incorporated
20110013471 - Current mode data sensing and propagation using voltage amplifier: A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from... Agent: Schwegman, Lundberg & Woessner/micron
20110013472 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.01/13/2011 > patent applications in patent subcategories. recently filed with US Patent Office
20110007538 - Systems and methods of cell selection in cross-point array memory devices: The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007539 - Test mode for multi-chip integrated circuit packages: When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal lines of one of the integrated circuit devices of the multi-chip integrated circuit package to permit direct testing of the integrated circuit device.... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum
20110007540 - Magnetic shielding for integrated circuit: A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less... Agent: Campbell Nelson Whipps, LLC
20110007541 - Floating body memory cell system and method of manufacture: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby... Agent: Dugan & Dugan, PC
20110007542 - Testing one time programming devices: A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column... Agent: Lowe Hauptman Ham & Berner, LLP
20110007552 - Active protection device for resistive random access memory (rram) formation: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007546 - Anti-parallel diode structure and method of fabrication: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007543 - Bipolar select device for resistive sense memory: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality... Agent: Campbell Nelson Whipps, LLC
20110007550 - Current magnitude compensation for memory cells in a data storage array: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007548 - Hierarchical cross-point array of non-volatile memory: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007545 - Non-volatile memory cell stack with dual resistive elements: A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007551 - Non-volatile memory cell with non-ohmic selection layer: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007544 - Non-volatile memory with active ionic interface region: A non-volatile memory cell and method of use therefore are disclosed. In accordance with various embodiments, the memory cell comprises a tunneling region disposed between a conducting region and a metal region, wherein the tunneling region comprises an active interface region disposed between a first tunneling barrier and a second... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007553 - Nonvolatile storage device and method for writing into memory cell of the same: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array... Agent: Wenderoth, Lind & Ponack L.L.P.
20110007555 - Resistance change element, semiconductor memory device, manufacturing method and driving method thereof: The resistance change element according to the exemplary embodiment includes three or more electrodes, none of the electrodes supplying ion to a resistance change material (205). It includes a material (206) which does not show resistance change arranged between an electrode (207) and the resistance change material (205), and current... Agent: Mr. Jackson Chen
20110007554 - Semiconductor device: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the... Agent: Young & Thompson
20110007549 - Shared bit line and source line resistive sense memory structure: A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line... Agent: Campbell Nelson Whipps, LLC
20110007547 - Vertical non-volatile switch with punchthrough access and method of fabrication therefor: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007557 - Semiconductor memory device: An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transistors.... Agent: Knobbe Martens Olson & Bear LLP
20110007556 - Sram architecture: A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to... Agent: Kamrath & Associates P.A.
20110007558 - Modular magnetoresistive memory: A magnetoresistive memory element is provided with a read module having a first pinned layer with a magnetoresistance that is readable by a read current received from an external circuit. A write module has a nanocontact that receives a write current from the external circuit and, in turn, imparts a... Agent: Mccarthy Law Group
20110007561 - Self-referenced magnetic random access memory cells: The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a... Agent: Pearne & Gordon LLP
20110007560 - Spin polarised magnetic device: A magnetic device includes a magnetic reference layer with a fixed magnetisation direction located either in the plane of the layer or perpendicular to the plane of the layer, a magnetic storage layer with a variable magnetisation direction, a non-magnetic spacer separating the reference layer and the storage layer and... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20110007562 - Dynamic wordline start voltage for nand programming: The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20110007564 - Flash multi-level threshold distribution scheme: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while... Agent: Borden Ladner Gervais LLP Anne Kinsman
20110007566 - Memory controller self-calibration for removing systemic influence: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as,... Agent: Leffert Jay & Polglaze, P.A.
20110007565 - Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20110007563 - Nonvolatile memory device, system, and related methods of operation: A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.... Agent: Volentine & Whitt PLLC
20110007567 - Temporary locking of an electronic circuit: A method and a circuit for protecting at least one piece of information contained in an electronic circuit by disabling at least one function of the circuit in case of detection of a number of abnormal operations greater than a threshold, in which the disabling of the function is temporary,... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20110007569 - Correcting for over programming non-volatile storage: A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line).... Agent: Vierra Magen/sandisk Corporation
20110007568 - Nand type rom: The invention discloses a NAND type ROM. The NAND type ROM comprises a plurality of bit lines, a plurality of word lines, a first source line, a second source line, and a plurality of NAND strings. The bit lines comprise a plurality of upper bit lines, first lower and second... Agent: Wpat, PC Intellectual Property Attorneys
20110007570 - Method of reading an nvm cell that utilizes a gated diode: A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation
20110007572 - Nand flash memory: m
20110007571 - Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage: Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the... Agent: Myers Bigel Sibley & Sajovec
20110007573 - Gain control for read operations in flash memory: A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach,... Agent: Vierra Magen/sandisk Corporation
20110007574 - Method of erasing an nvm cell that utilizes a gated diode: A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation
20110007575 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with... Agent: Mcdermott Will & Emery LLP
20110007576 - Synchronous dynamic random access memory semiconductor device for controlling output data: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response... Agent: Volentine & Whitt PLLC
20110007577 - Accessing method and a memory using thereof: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20110007579 - Internal voltage generator: An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert... Agent: Knobbe Martens Olson & Bear LLP
20110007578 - Techniques for providing a semiconductor memory device: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled... Agent: Hunton & Williams LLP Intellectual Property Department
20110007581 - Current cancellation for non-volatile memory: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007582 - Information recording apparatus and information recording method, information reproducing method and fade-in memory: An information recording apparatus comprises a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled... Agent: Dickstein Shapiro LLP
20110007580 - Local sensing and feedback for an sram array: An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local sense and feedback circuit connected to... Agent: Texas Instruments Incorporated
20110007583 - Semiconductor memory device and internal data transmission method thereof: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in... Agent: Mills & Onello LLP
20110007584 - Semiconductor device: A semiconductor device, including a plurality of control signal generation units each generating a control signal that is enabled when a column enable signal and a row enable signal are enabled, and a plurality of local sense amplifiers each sensing and amplifying data transmitted via a pair of local input/output... Agent: Lee & Morse, P.C.
20110007586 - Memory interface control circuit: A memory interface control circuit includes an input/output circuit 10 which transmits and receives a data strobe signal DQS to and from a memory, a read control circuit 20 which determines that the data strobe signal DQS associated with a memory read, received from the input/output circuit has repeated a... Agent: Foley And Lardner LLP Suite 500
20110007585 - Method for generating read enable signal and memory system using the method: A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read... Agent: Perkins Coie LLP
20110007587 - Command latency systems and methods: Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop... Agent: Dorsey & Whitney LLP Intellectual Property Department
20110007588 - Defective bit scheme for multi-layer integrated memory device: Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20110007589 - Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated... Agent: Unity Semiconductor Corporation
20110007590 - Semiconductor storage device and method of controlling word line potential: According to one embodiment, a semiconductor storage device includes a memory cell array, word lines, a driver, and a word-line-potential control circuit. In the memory cell array, memory cells are arranged in a matrix shape in a row direction and a column direction. The word lines perform row selection for... Agent: Knobbe Martens Olson & Bear LLP
20110007591 - Data serializers, output buffers, memory devices and methods of serializing: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals... Agent: Dorsey & Whitney LLP Intellectual Property Department
20110007594 - Multi-channel semiconductor memory device and method of refreshing the same: A multi-channel semiconductor memory device and a method of refreshing the same. In the multi-channel semiconductor memory device and method, a common refresh controller is prepared to detect refresh operation states of a plurality of sub-memory circuits (e.g. ICs) and to adjust refresh operation times of multiple sub-memory ICs so... Agent: F. Chau & Associates, LLC
20110007593 - Semiconductor memory device and access method: A semiconductor memory device includes a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; and a command generating circuit configured to issue one of a read command, a write command, and a refresh... Agent: Mcginn Intellectual Property Law Group, PLLC
20110007592 - Semiconductor storage device and refresh control method thereof: In a large capacity semiconductor storage device having a multi-bank configuration, it is desired to reduce a peak current of one refresh operation, to avoid an interference between adjacent banks, and to prevent a data breaking of a memory cell caused by a lack of a data hold time. A... Agent: Mcginn Intellectual Property Law Group, PLLC
20110007595 - Electronic equipment system and semiconductor integrated circuit controller: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on... Agent: Mcdermott Will & Emery LLP
20110007596 - Low-leakage power supply architecture for an sram array: A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and... Agent: Slater & Matsil, L.L.P.
20110007597 - Semiconductor control line address decoding circuit: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)01/06/2011 > patent applications in patent subcategories. recently filed with US Patent Office
20110002151 - Ultimate magnetic random access memory-based ternary cam: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively... Agent: Pearne & Gordon LLP
20110002153 - Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device: The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of... Agent: Buchanan, Ingersoll & Rooney PC
20110002152 - Systems, memories, and methods for repair in open digit memory architectures: Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture... Agent: Trask Britt, P.C./ Micron Technology
20110002155 - Current control element, memory element, and fabrication method thereof: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling... Agent: Mcdermott Will & Emery LLP
20110002158 - Method of programming variable resistance element and variable resistance memory device using the same: A method of programming a variable resistance element to be operated with stability and at a high speed is provided. The method programs a nonvolatile variable resistance element (10) including a variable resistance layer (3), which changes between a high resistance state and a low resistance state depending on a... Agent: Wenderoth, Lind & Ponack L.L.P.
20110002154 - Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal... Agent: Mcdermott Will & Emery LLP
20110002157 - Resistance change type memory: A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110002156 - Semiconductor memory device: A semiconductor memory device includes a plurality of first wirings; a plurality of second wirings; a plurality of memory cells positioned at respective intersections of the first wirings and the second wirings, each of the memory cells having a variable resistance element and a selective element connected to the variable... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110002159 - Semiconductor integrated circuit device: Memory cells each have two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage. The two transistors respectively have gate electrodes respectively connected to a corresponding one of first word lines and a corresponding one of second... Agent: Mcginn Intellectual Property Law Group, PLLC
20110002160 - Method of operating a magnetoresistive ram: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through... Agent: Lee & Morse, P.C.
20110002161 - Phase change memory cell with selecting element: A memory cell comprising a phase-change memory cell stacked in series with a resistive switch. The resistive switch has a material switchable between a high resistance state and a low resistance state by the application of a voltage. A plurality of memory cells are used to form a memory array.... Agent: Campbell Nelson Whipps, LLC
20110002162 - Gate drive voltage boost schemes for memory array: This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which... Agent: Saile Ackerman LLC
20110002163 - Semiconductor device: A semiconductor device includes: a first magnetic random access memory including a first memory cell and a second magnetic random access memory including a second memory cell operating at higher speed than the first memory cell and is provided on the same chip together with the first magnetic random access... Agent: Mr. Jackson Chen
20110002165 - Flash memory: A flash memory according to a present embodiment includes a memory cell array. The memory cell array includes a plurality of memory cells. Each of the memory cells can store n-bit data (n is an integer equal to or larger than 2). A plurality of word line are connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110002166 - Two-bit non-volatile flash memory array: A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between... Agent: Jianq Chyun Intellectual Property Office
20110002167 - Push-pull programmable logic device cell: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a... Agent: Lewis And Roca LLP
20110002168 - Binary logic utilizing mems devices: Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the devices may be used for logic applications. MEMS switches may be used in devices such as FPGAs, NAND devices, nvSRAM devices, AMS chips and general... Agent: Patterson & Sheridan, L.L.P.
20110002169 - Bad column management with bit information in non-volatile memory systems: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20110002170 - Semiconductor memory device having memory block configuration: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the... Agent: Mcdermott Will & Emery LLP
20110002171 - Memory with output control: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device... Agent: Borden Ladner Gervais LLP Anne Kinsman
20110002172 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20110002173 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells.... Agent: Foley And Lardner LLP Suite 500
20110002174 - Flash memory device and program recovery method thereof: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the... Agent: Lee & Morse, P.C. Attorneys And Counselors At Law
20110002164 - Semiconductor device: A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A... Agent: Mcginn Intellectual Property Law Group, PLLC
20110002178 - Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions... Agent: F. Chau & Associates, LLC
20110002175 - Semiconductor memory device: A semiconductor memory device includes: a repair node; a fuse one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse;... Agent: Ip & T Group LLP
20110002176 - Semiconductor memory device: A semiconductor memory device includes a repair node; a fuse, one side of which is coupled to the repair node; a pull-down unit configured to selectively transfer a ground voltage to the repair node; a pull-up unit configured to selectively transfer a driving voltage to another side of the fuse;... Agent: Ip & T Group LLP
20110002177 - Nonvolatile memory device having a plurality of memory blocks: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20110002180 - Circuit for generating data strobe signal and method: A circuit for generating a data strobe signal includes: a control signal generation unit configured to generate a strobe control signal defining an activation time period where a first data strobe signal and a second data strobe signal, which is an inverted signal of the first data strobe signal, are... Agent: Ip & T Group LLP
20110002179 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks... Agent: Ip & T Group LLP
20110002181 - Delay locked loop using hybrid fir filtering technique and semiconductor memory device having the same: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (ΣΔ) modulator to... Agent: Harness, Dickey & Pierce, P.L.C
20110002182 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a source signal generation unit configured to generate a source pulse signal having a pulse width which is determined depending on an interval between an input of an active signal and an input of a column command signal, which is inputted after an active command,... Agent: Ip & T Group LLP
20110002183 - Circuit precharging dram bit line: A bit line pre-charge circuit for a dynamic random access memory (DRAM) uses a charge sharing scheme. The pre-charge circuit includes switching elements disposed between a power voltage node and an output node, capacitors connected between intermediate nodes and ground. The switching elements being operated by successively activated control signals... Agent: Volentine & Whitt PLLC
20110002184 - Method of detecting a light attack against a memory device and memory device employing a method of detecting a light attack: A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a... Agent: Volentine & Whitt PLLC
20110002185 - Semiconductor device with control circuit controlling controlled circuit to the same potential: A device includes a first circuit, a second circuit, and a control circuit controlling the first and the second circuits. The control circuit controls a plurality of output signals of the second circuit so as to have the same potential when the control circuit activates the first circuit and inactivates... Agent: Mcginn Intellectual Property Law Group, PLLC
20110002188 - Apparatus for nonvolatile multi-programmable electronic fuse system: Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the... Agent: Michael J. Chang, LLC
20110002187 - Latch type fuse circuit and operating method thereof: A latch type fuse circuit includes a non-volatile memory, a PMOS transistor, and an output circuit. The non-volatile memory cell stores a logic bit. A voltage level of a source of the PMOS transistor determines the latch type fuse operating in the data program status or the data read status.... Agent: North America Intellectual Property Corporation
20110002186 - Secure electrically programmable fuse and method of operating the same: An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse... Agent: Hitt Gaines, PC Lsi CorporationPrevious industry: Electric power conversion systems
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