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Static information storage and retrieval December patent applications/inventions, industry category 12/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
12/30/2010 > patent applications in patent subcategories. patent applications/inventions, industry category

20100328980 - Multi-chip memory device: A multi-chip memory device includes a number of chips and a control circuit included in each of the chips and configured to generate an internal chip enable signal in response to set data stored therein and an external chip enable signal... Agent: William Park & Associates Ltd.

20100328979 - Nonvolatile memory device and operation method thereof: In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for... Agent: Lowe Hauptman Ham & Berner, LLP

20100328982 - Content addressable memory design: A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100328981 - Content addressable memory device for simultaneously searching multiple flows: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of... Agent: Mahamedi Paradice Kreisman LLP (nlmi)

20100328983 - Memory system with multi-level status signaling and method for operating the same: A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different... Agent: Mpg, LLP And Sandisk

20100328984 - Piezo-effect transistor device and applications: A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises... Agent: Cantor Colburn LLP-ibm Yorktown

20100328985 - Semiconductor device having plural circuit blocks laid out in a matrix form: To include an input circuit block to which a plurality of bits are input and a processing circuit block that processes an internal signal output from the input circuit block. The input circuit block includes a plurality of unit input circuits arranged in an X direction to which the bits... Agent: Sughrue Mion, PLLC

20100328986 - Magnetic shift register memory in stack structure: A magnetic shift register memory in stack structure includes magnetic shift registering layers for forming an unit of stack structure. Each registering layer has multiple magnetic domains and each domain has a magnetization direction corresponding to a stored data. The two adjacent magnetic shift registering layers respectively have an upper... Agent: Jianq Chyun Intellectual Property Office

20100328987 - E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit: An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and... Agent: North America Intellectual Property Corporation

20100328988 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100328989 - Semiconductor device and manufacturing method thereof and method for writing memory element: An object is to provide a higher-performance and higher-reliability memory device and a semiconductor device provided with the memory device at low cost and with high yield. A semiconductor device of the invention has a memory element including an insulating layer and an organic compound layer between first and second... Agent: Robinson Intellectual Property Law Office, P.C.

20100328991 - Semiconductor memory device: A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or... Agent: Mcdermott Will & Emery LLP

20100328990 - Sram device: a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation such that the threshold voltage on the logic signal input gates of the transistors is set at high level.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100328992 - Memory: A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free... Agent: K&l Gates LLP

20100328993 - Recording method of nonvolatile memory and nonvolatile memory: A recording method of a nonvolatile memory including a recording circuit that electrically performs recording of information for an information memory device having a resistance change connected to a power supply for information recording, includes the steps of: recording information in a low-resistance state by the recording circuit under a... Agent: K&l Gates LLP

20100328995 - Methods and apparatus for reducing defect bits in phase change memory: Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100328996 - Phase change memory having one or more non-constant doping profiles: A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100328994 - Phase change memory with finite annular conductive path: A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method... Agent: Law Office Of Ido Tuchman (yor)

20100328997 - Phase-change memory element, phase-change memory cell, vacuum processing apparatus, and phase-change memory element manufacturing method: A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.... Agent: Buchanan, Ingersoll & Rooney PC

20100328999 - Memory and data processing method: A memory includes: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, reads out... Agent: K&l Gates LLP

20100328998 - Memory and write control method: A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data... Agent: K&l Gates LLP

20100329001 - Methods of operating semiconductor memory devices including magnetic films having electrochemical potential difference therebetween: Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic... Agent: Harness, Dickey & Pierce, P.L.C

20100329000 - Non-volatile memory: Non-volatile memories can have data retention problems at high temperatures reducing the reliability of such devices. A non-volatile memory cell is described having a magnet, a ferromagnetic switching element and heating means. The non-volatile memory cell has a set position having a low resistance state and a reset position having... Agent: Haynes And Boone, LLPIPSection

20100329002 - Forecasting program disturb in memory by detecting natural threshold voltage distribution: Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data,... Agent: Vierra Magen/sandisk Corporation

20100329004 - Detecting the completion of programming for non-volatile storage: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when... Agent: Vierra Magen/sandisk Corporation

20100329005 - Semiconductor memory device and programming method thereof: A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among... Agent: William Park & Associates Ltd.

20100329006 - Semiconductor memory device capable of memorizing multivalued data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329008 - Nonvolatile memory device: A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a... Agent: William Park & Associates Ltd.

20100329007 - Pointer based column selection techniques in non-volatile memories: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example,... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100329009 - Smart card capable of sensing light: A smart card is foamed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the... Agent: F. Chau & Associates, LLC

20100329011 - Memory system having nand-based nor and nand flashes and sram integrated in one chip for hybrid data, code and cache storage: A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the... Agent: Lin & Associates Intellectual Property, Inc.

20100329010 - Read operation for memory with compensation for coupling based on write-erase cycles: A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn,... Agent: Vierra Magen/sandisk Corporation

20100329012 - Semiconductor memory device: A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329015 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes reading data stored in a main cell and a flag cell using a first read voltage, the nonvolatile memory device comprising the main cell for storing data including a least significant bit (LSB) and a most significant bit (MSB), and the... Agent: Ip & T Group LLP

20100329018 - Method of operating nonvolatile memory device capable of reading two planes: A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the... Agent: William Park & Associates Ltd.

20100329016 - Semiconductor device: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge... Agent: Miles & Stockbridge PC

20100329017 - Semiconductor device for short-circuiting output terminals of two or more voltage generator circuits at read time and control method for the same: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329014 - Semiconductor memory device and method of reading the same: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data.... Agent: Ip & T Group LLP

20100329013 - Semiconductor memory device including nonvolatile memory cell and data writing method thereof: A semiconductor memory device includes memory cells, bit lines, and first and second control circuits. The first control circuit supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changes a supply state... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329019 - Semiconductor storage device and electronic device using the same: When data is read from a memory cell of a top array block to a bit line, a switching device is closed so that the data is stored in the form of electrical charges at a bit line of a bottom array block. The switching device at a top array... Agent: Mcdermott Will & Emery LLP

20100329020 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of... Agent: Ip & T Group LLP

20100329021 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the... Agent: Ip & T Group LLP

20100329022 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the... Agent: Ip & T Group LLP

20100329003 - Memory employing independent dynamic reference areas: A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing... Agent: Flh/spansion C/o Frommer Lawrence & Haug

20100329024 - Memory employing separate dynamic reference areas: A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal,... Agent: Flh/spansion C/o Frommer Lawrence & Haug

20100329025 - Nonvolatile semiconductor storage device: The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have... Agent: Volentine & Whitt PLLC

20100329026 - Semiconductor memory device with charge accumulation layer: According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329023 - Sense amplifier apparatus and methods: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current... Agent: Schwegman, Lundberg & Woessner / Atmel

20100329031 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense pulse to switching elements coupled between the... Agent: Ip & T Group LLP

20100329028 - Method of performing program verification operation using page buffer of nonvolatile memory device: A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a... Agent: Ip & T Group LLP

20100329032 - Method of programming nonvolatile memory device: A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected... Agent: William Park & Associates Ltd.

20100329027 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a control unit configured to output operation signals, including an operation command signal, a source address, a destination address, and a data signal, to each of a number of memory chips in order to operate the memory chips, a command decoder configured to decode the... Agent: Ip & T Group LLP

20100329030 - Nonvolatile memory device and method of programming the same: In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced.... Agent: Lowe Hauptman Ham & Berner, LLP

20100329029 - Page buffer, nonvolatile semiconductor memory device having the same, and program and data verification method: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal... Agent: Volentine & Whitt PLLC

20100329033 - Nonvolatile semiconductor memory device: In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array including memory cells; and a control unit to control a signal applied to the memory cells. Each of the memory cells are settable to: first, second and third states having first, second and third... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100329034 - Estimating values related to discharge of charge-storing memory cells: One or more groups of charge-storing memory cells are selected from a plurality of regular charge-storing memory cells of a storage device. The selected memory cells are initialized with initial binary data, by charging them with corresponding amounts of electric charge, or the selected memory cells are simply used as... Agent: Toler Law Group

20100329036 - Nonvolatile memory device and reading method thereof: In a nonvolatile memory device and operating method thereof, data programmed into a second memory cell is sensed and a first memory cell adjacent the second memory cell is read in accordance with the data sensed from the second memory cell.... Agent: Lowe Hauptman Ham & Berner, LLP

20100329035 - Nonvolatile semiconductor memory device and discharge circuit thereof: A discharge circuit of a nonvolatile semiconductor memory device includes a memory array region including a plurality of floating gate type MOS memory cell transistors each including a source, a drain and a control gate which are formed in a P-well, where the P-well is formed in an N-well of... Agent: Volentine & Whitt PLLC

20100329037 - Circuit for supplying well voltages in nonvolatile memory device: A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control... Agent: William Park & Associates Ltd.

20100329038 - Methods of operating memory devices including different sets of logical erase blocks: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a... Agent: Attn: Thomas W. Leffert Leffert Jay & Polglaze, P.A.

20100329043 - Two-transistor floating-body dynamic memory cell: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100329040 - Data alignment circuit and method of semiconductor memory apparatus: A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured... Agent: Ladas & Parry LLP

20100329039 - Data buffer control circuit and semiconductor memory apparatus including the same: A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if... Agent: Ladas & Parry LLP

20100329042 - Memory chip package with efficient data i/o control: A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input... Agent: William Park & Associates Ltd.

20100329041 - Semiconductor memory device having power-saving effect: A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when... Agent: F. Chau & Associates, LLC

20100329044 - Assisting write operations to data storage cells: A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a... Agent: Nixon & Vanderhye P.C.

20100329045 - Adjustment of write timing in a memory device: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100329046 - Integrated circuit memory operation apparatus and methods: Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during... Agent: Schwegman, Lundberg & Woessner/micron

20100329047 - Nonvolatile memory device: A nonvolatile memory device, including an X decoder coupling global lines to respective word lines to which memory cells are coupled, a voltage supply unit comprising voltage selection circuits corresponding to the respective global lines and configured to generate operating voltages, wherein each of the voltage selection circuits latches control... Agent: Ip & T Group LLP

20100329051 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman

20100329048 - Precharge signal generator and semiconductor memory device: A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal... Agent: Ladas & Parry LLP

20100329050 - Semiconductor memory device: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.... Agent: Ip & T Group LLP

20100329049 - Semiconductor memory device having a latency controller: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command... Agent: F. Chau & Associates, LLC

20100329053 - Semiconductor memory device having a redundancy area: Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write... Agent: Harness, Dickey & Pierce, P.L.C

20100329052 - Word line defect detecting device and method thereof: Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first... Agent: North America Intellectual Property Corporation

20100329055 - Measuring electrical resistance: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100329054 - Memory built-in self-characterization: A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory.... Agent: Ryan, Mason & Lewis, LLP

20100329057 - Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation: In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line... Agent: Harness, Dickey & Pierce, P.L.C

20100329058 - Processor instruction cache with dual-read modes: A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the... Agent: Harness, Dickey & Pierce P.L.C

20100329056 - Sense amplifier and semiconductor integrated circuit using the same: A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit... Agent: Ladas & Parry LLP

20100329059 - Apparatus and methods for sense amplifiers: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current... Agent: Schwegman, Lundberg & Woessner / Atmel

20100329060 - Counter control signal generator and refresh circuit: A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal including a pulse generated in sync with a cyclic signal... Agent: Ladas & Parry LLP

20100329061 - Electrical fuse circuit for security applications: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage... Agent: K&l Gates LLPIPDocketing

20100329063 - Dynamically controlled voltage regulator for a memory: A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given... Agent: Pvf -- Oracle America, Inc. C/o Park, Vaughan & Fleming LLP

20100329062 - Leakage and nbti reduction technique for memory: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100329064 - Systems, methods and devices for monitoring capacitive elements in devices storing sensitive data: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the... Agent: Crawford Maunu PLLC

20100329065 - Systems, methods and devices for power control in mass storage devices: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage circuit is powered using a variable voltage controlled to limit the current draw from a power supply, to charge the energy storage circuit for providing backup power to... Agent: Crawford Maunu PLLC

20100329066 - Non-blocking multi-port memory formed from smaller multi-port memories: A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the... Agent: Infinera Corporation Ross Carothers

20100329067 - Charge pump and semiconductor device having the same: A charge pump and method of operation are provided. The charge pump includes a first boosting unit configured to receive a pre-charge voltage and electrically charge a first MOS capacitor during a pre-charge period, and to boost a voltage of a connection node to a first output voltage during a... Agent: Volentine & Whitt PLLC

20100329070 - Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof: A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly,... Agent: F. Chau & Associates, LLC

20100329068 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of first and second word lines respectively connected to the memory cells, a plurality of first drivers for driving the first word lines selected during a read... Agent: Staas & Halsey LLP

20100329069 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of... Agent: Staas & Halsey LLP

  
12/23/2010 > patent applications in patent subcategories. patent applications/inventions, industry category

20100321970 - Content addressable memory having programmable interconnect structure: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match... Agent: Mahamedi Paradice Kreisman LLP (nlmi)

20100321971 - Content addressable memory having selectively interconnected counter circuits: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit... Agent: Mahamedi Paradice Kreisman LLP (nlmi)

20100321972 - Systems for implementing sdram controllers, and buses adapted to include advanced high performance bus features: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request... Agent: Christopher P Maiorana, PC Lsi Corporation

20100321973 - Memory module, system and method of making same: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices.... Agent: Trask Britt, P.C./ Micron Technology

20100321974 - Magnetic shift register and reading method: A magnetic shift register including at least one magnetic track is provided. Each magnetic track has at least one set of burst data formed by a plurality of consecutive magnetic domains. Each magnetic domain has a magnetization direction corresponding to a stored data. A head magnetic domain having a given... Agent: Jianq Chyun Intellectual Property Office

20100321975 - Ferroelectric memory device: A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell (32) disposed at an intersection... Agent: Fish & Richardson P.C. (ny)

20100321982 - Nonvolatile storage device and method for writing into the same: To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . )... Agent: Wenderoth, Lind & Ponack L.L.P.

20100321977 - Programming reversible resistance switching elements: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques... Agent: Vierra Magen/sandisk Corporation

20100321979 - Resistance change memory: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectification connected in series between the first and second conductive lines,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100321980 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance... Agent: Knobbe Martens Olson & Bear LLP

20100321978 - Semiconductor memory device and memory cell voltage application method: A semiconductor memory device comprises a plurality of parallel word lines, a plurality of parallel bit lines formed crossing the plurality of word lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Each memory cell has one end connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100321976 - Split path sensing circuit: A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including... Agent: Qualcomm Incorporated

20100321981 - Variable resistance memory devices compensating for word line resistance: Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word... Agent: Myers Bigel Sibley & Sajovec

20100321984 - Configuration random access memory: Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair... Agent: Treyz Law Group

20100321983 - Semiconductor memory device capable of driving non-selected word lines to first and second potentials: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation... Agent: Arent Fox LLP

20100321985 - Boosted gate voltage programming for spin-torque mram array: A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that... Agent: Saile Ackerman LLC

20100321986 - Multi-bit stram memory cells: A multi-bit spin torque magnetic element that has a ferromagnetic pinned layer having a pinned magnetization orientation, a non-magnetic layer, and a ferromagnetic free layer having a magnetization orientation switchable among at least four directions, the at least four directions being defined by a physical shape of the free layer.... Agent: Campbell Nelson Whipps, LLC

20100321991 - Chalcogenide devices exhibiting stable operation from the as-fabricated state: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the... Agent: Kevin L. Bray Energy Conversion Devices, Inc.

20100321988 - Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address... Agent: Trask Britt, P.C./ Micron Technology

20100321989 - Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same: A fusion memory device having phase change memory devices that have different resistance distributions and a corresponding data processing system is presented. The fusion memory device includes a first and a second phase change memory group arranged on the same chip. Because the second phase change memory group exhibits a... Agent: Ladas & Parry LLP

20100321987 - Memory device and method for sensing and fixing margin cells: A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can comprise reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100321990 - Memory including vertical bipolar select device and resistive memory element: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second... Agent: Coats & Bennett/infineon Technologies

20100321992 - Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using same: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive... Agent: Thomas J. D'amico Dickstein Shapiro LLP

20100321994 - Memory self-reference read and write assist methods: A magnetic tunnel junction memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a magnetic tunnel junction memory unit includes applying a first read current through a magnetic tunnel junction data cell to form a first bit line read voltage, then applying a... Agent: Campbell Nelson Whipps, LLC

20100321993 - Methods of forming spin torque devices and structures formed thereby: Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to... Agent: Intel Corporation C/o Cpa Global

20100322001 - Integrated circuit embedded with non-volatile programmable memory having variable coupling and separate read/write paths: A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through... Agent: Law Office Of J. Nicholas Gross, Prof. Corp.

20100321997 - Method and system for obtaining a reference block for a mlc flash memory: A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to... Agent: Squire, Sanders & Dempsey L.L.P.

20100321998 - Nonvolatile memory device and related method of programming: A method of programming a nonvolatile memory device comprises pre-programming multi-bit data in a plurality of multi-level memory cells, reading the pre-programmed multi-bit data from the plurality of multi-level cells based on state group codes indicating state groups of the plurality of multi-level cells, and re-programming the read multi-bit data... Agent: Volentine & Whitt PLLC

20100321999 - Nonvolatile memory device and related programming method: A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells... Agent: Volentine & Whitt PLLC

20100322000 - Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring... Agent: Mills & Onello LLP

20100322002 - Eeprom device: An EEPROM device which prevents disturbance phenomena when writing data on a memory cell. The device includes an on/off switch element for selectively connecting between an individual source line and a common source line in response to a control signal supplied via a control terminal.... Agent: Volentine & Whitt PLLC

20100322003 - Interleaved memory program and verify method, device and system: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory... Agent: Trask Britt, P.C./ Micron Technology

20100322004 - Semiconductor memory device and erase method in the same: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the... Agent: Townsend And Townsend And Crew, LLP

20100322006 - Nand memory cell string having a stacked select gate structure and process for for forming same: A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100322005 - Reduced programming pulse width for enhanced channel boosting in non-volatile storage: Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of... Agent: Vierra Magen/sandisk Corporation

20100322007 - Flash memory device and method of reading data: A flash memory device and method of reading data are disclosed. The method includes; performing a test read operation directed to test data stored in a memory cell array of the flash memory device by iteratively applying a sequence of test read retry operations, wherein each successive test read retry... Agent: Volentine & Whitt PLLC

20100322010 - Non-volatile memory programmable through areal capacitive coupling: A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device.... Agent: Law Office Of J. Nicholas Gross, Prof. Corp.

20100322008 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array including regular memory cells and permanent memory cells and a control circuit. The regular memory cells are capable of switching between a first data storage state and a second data storage state. The permanent memory cells... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100322009 - Semiconductor memory device including charge accumulation layer: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100321995 - Memory cell threshold voltage drift estimation methods and apparatus: Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only a subset of data states of the memory device and, using the determined threshold voltage drift of the two or more reference memory cells, estimating... Agent: Leffert Jay & Polglaze, P.A.

20100321996 - Semiconductor device and method for adjusting reference levels of reference cells: A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100322011 - Semiconductor memory device with memory cells having charge accumulation layer: According to one embodiment, a semiconductor memory device includes memory cells, a memory cell array, a word line, a bit line, a source line, a row decoder, a sense amplifier, and a first MOS transistor. The word line is connected to gates of the memory cells. The bit line is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100322012 - Nonvolatile semiconductor memory device and write method for the same: According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100322013 - Nonvolatile semiconductor memory device: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the... Agent: Miles & Stockbridge PC

20100322014 - Erasing method for nonvolatile memory: The present invention relates to an erasing method for nonvolatile memory, which uses forward bias between the source/drain region and body contact to inject majority carriers into the body, and then accelerates the majority carriers by an electric field between the body and the gate to energize the majority carriers... Agent: Nikolai & Mersereau, P.A.

20100322015 - Split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first... Agent: Dla Piper LLP (us )

20100322017 - Card and host device: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100322016 - Retention of data during stand-by mode: An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is... Agent: Graybeal Jackson LLP

20100322018 - Temperature compensation circuit and method for sensing memory: A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100322019 - Reference voltage regulator for edram with vss-sensing: A reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level includes an oscillator, a control block, a reference generator, a comparator, a pulse generator, a driver, and a reference voltage output, where the oscillator sends requests for sampling and correction to the... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100322020 - Data storage systems and methods using data attribute-based data transfer: Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of... Agent: Myers Bigel Sibley & Sajovec

20100322021 - Semiconductor memory device and memory system having the same: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal... Agent: Muir Patent Consulting, PLLC

20100322022 - Semiconductor storage device: The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first... Agent: Miles & Stockbridge PC

20100322023 - Semiconductor device and semiconductor device test method: A semiconductor device includes a first memory including a first memory cell and a first redundant memory cell; a first test circuit configured to test the first memory and output first defect information indicating a defective portion included in the first memory cell; a first storage part; and a first... Agent: Fujitsu Patent Center Fujitsu Management Services Of America, Inc.

20100322024 - Semiconductor memory, system, operating method of semiconductor memory, and manufacturing method of semiconductor memory: A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks. A block control unit selects the plurality... Agent: Arent Fox LLP

20100322025 - Digit line equilibration using access devices at the edge of sub-arrays: A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second... Agent: Trask Britt, P.C./ Micron Technology

20100322026 - Mechanism for measuring read current variability of sram cells: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100322027 - Memory using multiple supply voltages: A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is... Agent: Freescale Semiconductor, Inc. Law Department

  
12/16/2010 > patent applications in patent subcategories. patent applications/inventions, industry category

20100315852 - Memory and storage device utilizing the same: A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and... Agent: Quintero Law Office, PC

20100315853 - Semiconductor integrated circuit: In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented... Agent: Mcdermott Will & Emery LLP

20100315854 - Magnetic random access memory and initializing method for the same: A domain wall motion type MRAM has: a magnetic recording layer 10 having perpendicular magnetic anisotropy; and a pair of terminals 51 and 52 used for supplying a current to the magnetic recording layer 10. The magnetic recording layer 10 has: a first magnetization region 11 connected to one of... Agent: Mr. Jackson Chen

20100315855 - Rom array with shared bit-lines: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each... Agent: Schwegman, Lundberg & Woessner / Atmel

20100315856 - High-density non-volatile read-only memory arrays and related methods: In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality... Agent: Schwegman, Lundberg & Woessner / Atmel

20100315857 - Resistance change memory: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100315858 - Memory architecture with a current controller and reduced power requirements: Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled... Agent: Law Office Of Tracy P. Jong

20100315859 - Eight-transistor sram memory with shared bit-lines: An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged... Agent: Slater & Matsil, L.L.P.

20100315860 - Integrated circuit with a memory matrix with a delay monitoring column: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100315861 - Sram cell and sram device: In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100315862 - Stable sram cell: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes... Agent: Slater & Matsil, L.L.P.

20100315865 - Diode assisted switching spin-transfer torque memory unit: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured... Agent: Campbell Nelson Whipps, LLC

20100315863 - Magnetic tunnel junction device and fabrication: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.... Agent: Qualcomm Incorporated

20100315864 - Magnetoresistive element and magnetic memory: A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100315866 - Phase change memory device having multi-level and method of driving the same: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are... Agent: Ladas & Parry LLP

20100315868 - Semiconductor device including storage device and method for driving the same: A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes... Agent: Robinson Intellectual Property Law Office, P.C.

20100315867 - Solid-state memory device, data processing system, and data processing device: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a... Agent: Young & Thompson

20100315870 - Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (mtj): A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a... Agent: Ipxlaw Group LLP

20100315869 - Spin torque transfer mram design with low switching current: The invention discloses a method to store digital information through use of spin torque transfer in a device that has a very low critical current. This is achieved by adding a spin filtering layer whose direction of magnetization is fixed to be parallel to the device's pinned layer.... Agent: Saile Ackerman LLC

20100315871 - Dynamic data restore in thyristor-based memory device: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to... Agent: The Webostad Firm, A Professional Corporation

20100315872 - Multilevel cell memory devices having reference point cells: Embodiments of the disclosure include multilevel memory cell devices that utilize reference point cells to determine the states of other cells. Embodiments of the disclosure also include methods of storing data to and retrieving data from multilevel memory cell devices utilizing reference point cells. In one embodiment, a multilevel memory... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.

20100315873 - Nonvolatile memory device and related programming method: A method of programming a nonvolatile memory device comprises receiving program data, detecting logic states of the received program data, identifying adjusted margins to be applied to programmed memory cells based on the absence of one or more logic states in the detected logic states, and programming the program data... Agent: Volentine & Whitt PLLC

20100315874 - Use of emerging non-volatile memory elements with flash memory: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash... Agent: Dickstein Shapiro LLP

20100315875 - Non-volatile memory device having vertical structure and method of operating the same: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and... Agent: Mills & Onello LLP

20100315876 - Memory devices and operations thereof using program state determination based on data value distribution: In a memory device, a proportion of at least one cell state in a unit of the memory is determined. A program state of the unit of the memory is determined based on the determined proportion of the at least one cell state. Determining a proportion of at least one... Agent: Myers Bigel Sibley & Sajovec

20100315877 - Data sensing module and sensing circuit for flash memory: A sensing circuit for a flash memory is provided. The sensing circuit includes a first transistor, a detector, and a charge circuit. A drain of the first transistor is coupled to a bias, a gate thereof receives an inverted signal, and a source thereof receives a data. In addition, the... Agent: J C Patents

20100315878 - Semiconductor memory device including memory cell with charge accumulation layer: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a first MOS transistor, and a current source circuit. The bit line transfers data read from the memory cell and/or data to be written to the memory cell. The sense amplifier charges... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100315880 - Method of operating nonvolatile memory device: A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a fail bit count set to the selected... Agent: William Park & Associates Ltd.

20100315879 - Page buffer of nonvolatile memory device and method of performing program verification operation using the same: A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense... Agent: Ip & T Group LLP

20100315881 - Non-volatile memory device and method of reading data in a non-volatile memory device: A non-volatile memory device includes a row decoder and a memory cell array. The row decoder generates a read voltage, and first, second and third drive voltages. The memory cell array includes a selected word line receiving the read voltage, a first neighboring word line of the selected word line... Agent: Volentine & Whitt PLLC

20100315883 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device comprises a memory cell array including a number of bit lines commonly coupled to a source line and each coupled to a number of memory cells, a delay unit configured to delay a sense signal in response to a voltage level of the source line and... Agent: Ip & T Group LLP

20100315882 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit... Agent: Ip & T Group LLP

20100315884 - Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof: A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases... Agent: Docket Clerk

20100315889 - Sram memory cell with double gate transistors provided with means to improve the write margin: A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100315885 - Circuits, devices, systems, and methods of operation for capturing data signals: Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100315886 - Data transfer apparatus, and method, and semiconductor circuit: Provided is a data transfer apparatus and method that enables fast data transfer, and has a simple circuit configuration and a small area; and a semiconductor circuit. The data transfer apparatus includes: a data pair generation circuit (301) that transfers a generated data pair during one cycle of a handshake... Agent: Mr. Jackson Chen

20100315887 - Semiconductor memory device having physically shared data path and test device for the same: A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data... Agent: Muir Patent Consulting, PLLC

20100315888 - Semiconductor device: A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling... Agent: Sughrue Mion, PLLC

20100315890 - Memory array with corresponding row and column control signals: Some embodiments regard a method comprising: controlling a row of cells of a memory array with a first signal; controlling a column of cells of the memory array with a second signal; transferring data from a cell activated by both the first signal and the second signal to a pair... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100315891 - Memory controller with skew control and method: A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the... Agent: Freescale Semiconductor, Inc. Law Department

20100315892 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system... Agent: Mcdermott Will & Emery LLP

20100315894 - Low power sensing in a multi-port sram using pre-discharged bit lines: A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different... Agent: Cantor Colburn LLP-ibm Burlington

20100315893 - Semiconductor memory device: A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling... Agent: Volentine & Whitt PLLC

20100315895 - Semiconductor device: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1”... Agent: Brundidge & Stanger, P.C.

20100315896 - Temperature detection circuit of semiconductor memory apparatus: A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to... Agent: Venable LLP

  
12/09/2010 > patent applications in patent subcategories. patent applications/inventions, industry category

20100309703 - Compact and accurate analog memory for cmos imaging pixel detectors: The present invention relates to an analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor (102)... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100309704 - In-pakage microelectronic apparatus, and methods of using same: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to... Agent: Intel Corporation C/o Cpa Global

20100309706 - Load reduced memory module and memory system including the same: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control... Agent: Mcginn Intellectual Property Law Group, PLLC

20100309707 - Pcb circuit modification from multiple to individual chip enable signals: A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the... Agent: Vierra Magen/sandisk Corporation

20100309705 - Stacked memory devices: A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the... Agent: Harness, Dickey & Pierce, P.L.C

20100309708 - Semiconductor memory: Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100309709 - Unit cell of nonvolatile memory device and nonvolatile memory device with the same: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output... Agent: North Star Intellectual Property Law, PC

20100309711 - F-ram device with current mirror sense amp: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp.... Agent: Texas Instruments Incorporated

20100309710 - Variable impedance circuit controlled by a ferroelectric capacitor: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second... Agent: The Law Offices Of Calvin B. Ward

20100309712 - Magnetic random access memory: An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization free layer, a first magnetization fixed layer, a second magnetization free layer and a first nonmagnetic layer sandwiched between the first magnetization... Agent: Mr. Jackson Chen

20100309713 - Magnetic random access memory: An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization fixed layer, a first magnetization free layer, a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization... Agent: Mr. Jackson Chen

20100309714 - Methods, structures, and devices for reducing operational energy in phase change memory: Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in... Agent: Trask Britt, P.C./ Micron Technology

20100309717 - Non-volatile multi-bit memory with programmable capacitance: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and... Agent: Campbell Nelson Whipps, LLC

20100309715 - Stable current supply circuit irrespective of pvt variations and semiconductor having same: A current supply circuit comprises a reference voltage generator generating a reference voltage that varies with temperature, a current circuit generating a constant reference current irrespective of the temperature based on the reference voltage, and a current source generating a mirror current by mirroring a base current as a replica... Agent: Volentine & Whitt PLLC

20100309716 - Supply voltage generating circuit and semiconductor device having same: A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The... Agent: Sughrue Mion, PLLC

20100309718 - Semiconductor memory device: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first... Agent: Ip & T Group LLP

20100309719 - Folding data stored in binary format into multi-state format within non-volatile memory devices: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100309721 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cells, a bit line, a sense amplifier, a memory circuit and an arithmetic circuit. The memory cells store multiple values in one memory cell. The bit line connected with the memory cells. The sense amplifier supplies a write... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100309720 - Structure and method for shuffling data within non-volatile memory devices: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100309722 - Semiconductor memory device capable of realizing a chip with high operation reliability and high yield: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20100309723 - Semiconductor memory device capable of realizing a chip with high operation reliability and high yield: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20100309724 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20100309725 - Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device: A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a... Agent: Ip & T Group LLP

20100309726 - Reference voltage optimization for flash memory: A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than... Agent: Harness, Dickey & Pierce P.L.C

20100309727 - Method of operating memory device having page buffer: A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for... Agent: Townsend And Townsend And Crew, LLP

20100309728 - Memory read methods, apparatus, and systems: Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number... Agent: Schwegman, Lundberg & Woessner/micron

20100309729 - Nonvolatile memory device and method of manufacturing the same: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly,... Agent: Stanzione & Kim, LLP

20100309730 - Memory erase methods and devices: Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.... Agent: Leffert Jay & Polglaze, P.A.

20100309736 - Sram with read and write assist: A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to... Agent: Freescale Semiconductor, Inc. Law Department

20100309732 - Data alignment circuit of semiconductor memory apparatus: A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group,... Agent: Ladas & Parry LLP

20100309731 - Keeperless fully complementary static selection circuit: Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When a cell or data input... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100309733 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100309734 - Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuit: An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular... Agent: Dillon & Yudell LLP

20100309735 - Internal power supply circuit, semiconductor device, and semiconductor device manufacturing method: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from... Agent: Morrison & Foerster LLP

20100309737 - Signal adjusting system and signal adjusting method: A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plurality of signal transmitting paths for receiving a first transmitted signal... Agent: North America Intellectual Property Corporation

20100309739 - Semiconductor memory apparatus and probe test control circuit therefor: Disclosed probe test control circuit includes: a bank active circuit configured to generate a bank active signal in response to a bank address and bank-by-bank test control signals; and a mat active circuit configured to generate a mat-by-mat sub-wordline selection signal and provide the mat-by-mat sub-wordline selection signal to a... Agent: Echelon Law Group, PC

20100309738 - Semiconductor memory apparatus and test method thereof: A semiconductor memory apparatus includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier for detecting and amplifying voltage levels of the bit line pair. The semiconductor memory apparatus is configured to perform a test to determine the occurrence of leakage current by... Agent: Ladas & Parry LLP

20100309740 - Low power, single-ended sensing in a multi-port sram using pre-discharged bit lines: An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being... Agent: Cantor Colburn LLP-ibm Burlington

20100309741 - Semiconductor device: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large... Agent: Miles & Stockbridge PC

20100309742 - Method controlling deep power down mode in multi-port semiconductor memory: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode... Agent: Volentine & Whitt PLLC

20100309743 - Power detecting circuit, portable device and method for preventing data loss: In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of the power input terminal. When... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100309744 - Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of... Agent: Ip & T Group LLP

  
12/02/2010 > patent applications in patent subcategories. patent applications/inventions, industry category

20100302828 - Addressing circuit of semiconductor memory device and addressing method therefor: The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to... Agent: Ip & T Group LLP

20100302826 - Cam cell circuit of nonvolatile memory device and method of driving the same: A Code Address Memory (CAM) cell circuit of a nonvolatile memory device includes a CAM cell unit configured to store data, a control circuit unit configured to read data stored in the CAM cell unit and to output data read as read data, and register units each configured to comprise... Agent: Ip & T Group LLP

20100302827 - Code address memory (cam) cell read control circuit of semiconductor memory device and method of reading data of cam cell: A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate... Agent: Ip & T Group LLP

20100302829 - Semiconductor module and data memory module having the same: A semiconductor module and a data memory module having the same are provided. The semiconductor module includes a substrate having a semiconductor device, a ground terminal, a protection pattern, and a switching element. The ground terminal and the protection pattern are formed on the substrate. The switching element connects the... Agent: Sughrue Mion, PLLC

20100302830 - Semiconductor memory device: A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in... Agent: Ip & T Group LLP

20100302831 - Semiconductor storage device: A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also... Agent: Knobbe Martens Olson & Bear LLP

20100302832 - Non-volatile logic devices using magnetic tunnel junctions: The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and... Agent: Pearne & Gordon LLP

20100302833 - Semiconductor device having nonvolatile memory element and manufacturing method thereof: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of... Agent: Mcginn Intellectual Property Law Group, PLLC

20100302834 - F-ram device with current mirror sense amp: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp.... Agent: Texas Instruments Incorporated

20100302835 - Limited charge delivery for programming non-volatile storage elements: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that... Agent: Vierra Magen/sandisk Corporation

20100302836 - Nonvolatile memory cell comprising a diode and a resistance-switching material: In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed... Agent: Dugan & Dugan, PC

20100302837 - Memory with read cycle write back: A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair... Agent: Freescale Semiconductor, Inc. Law Department

20100302838 - Read disturb-free smt reference cell scheme: We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells,... Agent: Saile Ackerman LLC

20100302839 - Statis source plane in stram: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell... Agent: Campbell Nelson Whipps, LLC

20100302841 - Phase change memory apparatus and test circuit therefor: A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.... Agent: Echelon Law Group, PC

20100302840 - Phase change random access memory apparatus for controlling data transmission: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from... Agent: Echelon Law Group, PC

20100302842 - Semiconductor memory device, manufacturing method thereof, data processing system, and data processing device: A semiconductor memory device includes: first and second impurity diffusion layers that form a part of a semiconductor substrate, each of the impurity diffusion layers function as one and the other of an anode and a cathode, respectively of a pn-junction diode; a recording layer connected to the second impurity... Agent: Sughrue Mion, PLLC

20100302843 - Spin transfer torque - magnetic tunnel junction device and method of operation: A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a... Agent: Qualcomm Incorporated

20100302844 - Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling: A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The... Agent: Dickstein Shapiro LLP

20100302846 - Charge retention for flash memory by manipulating the program data methodology: A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then... Agent: Flh/spansion C/o Frommer Lawrence & Haug

20100302845 - Memory device and methods for fabricating and operating the same: The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches.... Agent: J C Patents

20100302847 - Multi-level nand flash memory: According to one embodiment, a multi-level NAND flash memory executes a writing of an upper data to a LM flag. When an address of a flag assigns a bad column, a data transfer control circuit and a address control circuit control a write operation of upper data in the flag... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100302848 - Transistor having peripheral channel: Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain... Agent: Leffert Jay & Polglaze, P.A.

20100302849 - Nand flash memory with integrated bit line capacitance: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100302850 - Storage device and method for reading the same: The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read... Agent: Harness, Dickey & Pierce, P.L.C

20100302851 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device and a method of programming the device includes a memory cell array configured to have a number of memory cells, a row decoder coupled to the memory cells through word lines, page buffers coupled to the memory cells through bit lines, and a control unit configured... Agent: Ip & T Group LLP

20100302852 - Nonvolatile memory device and method of verifying the same: A nonvolatile memory device having a memory cell array configured to include a number of memory cells coupled to a bit line, a control circuit configured to output a code signal in response to a verification operation command signal during a verification operation being performed, a page buffer operation voltage... Agent: Ip & T Group LLP

20100302853 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device includes a high voltage generation unit configured to generate a program voltage and a pass voltage, a block selection unit coupled to the high voltage generation unit through global word lines, a memory cell array coupled to the block selection unit through word lines, a discharge... Agent: Ip & T Group LLP

20100302854 - Area-efficient electrically erasable programmable memory cell: Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In... Agent: Texas Instruments Incorporated

20100302855 - Memory device and methods for fabricating and operating the same: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are... Agent: J C Patents

20100302857 - Method of programming an array of nmos eeprom cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits: A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments... Agent: King & Spalding LLP

20100302856 - Nonvolatile memory device and method of programming and reading the same: A nonvolatile memory device includes a control circuit configured to generate a control signal by counting a number of first data among input data, a buffer unit configured to temporarily store the input data, invert the input data in response to the control signal, and store the inverted data or... Agent: Ip & T Group LLP

20100302858 - Data line management in a memory device: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such... Agent: Leffert Jay & Polglaze, P.A.

20100302862 - Non-volatile memory device: The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a... Agent: Marshall, Gerstein & Borun LLP

20100302859 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device includes a memory block including a number of cell strings, a channel voltage detection unit configured to detect channel voltages of the cell strings in which the channel voltages are changed based on voltages supplied to memory cells of the cell strings during a program operation... Agent: Ip & T Group LLP

20100302860 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data... Agent: Ip & T Group LLP

20100302861 - Program and erase methods for nonvolatile memory: Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a... Agent: Harness, Dickey & Pierce, P.L.C

20100302863 - Reading method for mlc memory and reading circuit using the same: A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100302864 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program... Agent: Ip & T Group LLP

20100302865 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device comprises a memory cell array comprising memory cells, an operation voltage generation unit configured to generate a first pass voltage when a verification voltage for a memory cell to be programmed is higher than a reference voltage and to generate a second pass voltage lower than... Agent: Ip & T Group LLP

20100302867 - Circuit for precharging bit line and nonvolatile memory device including the same: A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up... Agent: Ip & T Group LLP

20100302869 - Flash memory device operating at multiple speeds: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first... Agent: Volentine & Whitt PLLC

20100302868 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell... Agent: Ip & T Group LLP

20100302866 - Method of testing for a leakage current between bit lines of nonvolatile memory device: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second... Agent: Ip & T Group LLP

20100302870 - Nonvolatile memory device and method of operating and fabricating the same: Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be... Agent: Harness, Dickey & Pierce, P.L.C

20100302871 - Concurrent intersymbol interference encoding in a solid state memory: Methods and devices are provided for concurrent intersymbol interference encoding in a solid state memory. In an illustrative embodiment, a write data signal is received as input to a processing component. A channel-effect-corrected encoding of the write data signal is produced, where the channel-effect-corrected encoding is based on the write... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.

20100302872 - Buffer control signal generation circuit and semiconductor device: A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a write pulse into a first period to generate a first burst start signal and shifts the write pulse into a... Agent: Ladas & Parry LLP

20100302873 - Mode-register reading controller and semiconductor memory device: A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal that is activated when the reset command is input during a mode-register reading operation. The first transmitter buffers and transfers the mode-register read signal... Agent: Ladas & Parry LLP

20100302875 - Semiconductor device having nonvolatile memory element and data processing system including the same: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content... Agent: Morrison & Foerster LLP

20100302874 - Semiconductor memory device, information processing system including the same, and controller: To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation... Agent: Morrison & Foerster LLP

20100302877 - Memory device having reduced standby current and memory system including same: A memory device includes a plurality of banks, a first generator generating standby current in response to a standby signal, and a switching circuit supplying the standby current to at least one of the plurality of banks in response to a plurality of active signals.... Agent: Volentine & Whitt PLLC

20100302876 - Package apparatus and method of operating the same: A package apparatus includes at least one memory chip, a voltage detection circuit configured to make a determination of whether a voltage supplied to the memory chip is a specific voltage or higher, and a controller configured to control an operation of the memory chip based on a result of... Agent: Ip & T Group LLP

20100302879 - Semiconductor memory device and method of controlling the same: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage... Agent: Arent Fox LLP

20100302878 - Sense amplifier and driving method thereof, and semiconductor memory device having the sense amplifier: The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive... Agent: Ladas & Parry LLP

20100302880 - Dual power rail word line driver and dual power rail word line driver array: A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100302881 - Voltage generation circuit and nonvolatile memory device using the same: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured... Agent: Ip & T Group LLP

20100302882 - Random access memory for use in an emulation environment: In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second... Agent: Mentor Graphics Corp. Patent Group

20100302883 - Method of estimating self refresh period of semiconductor memory device: In a method of estimating a self refresh period of a semiconductor memory device according to an exemplary embodiment, a plurality of internal address signals are reset in response to a refresh reset signal. The plurality of internal address signals are sequentially changed synchronously with an oscillation signal. A refresh... Agent: Mills & Onello LLP

20100302885 - Delay locked loop and method and electronic device including the same: A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock... Agent: Muir Patent Consulting, PLLC

20100302884 - Method of preventing coupling noises for a non-volatile semiconductor memory device: Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check... Agent: Harness, Dickey & Pierce, P.L.C

20100302886 - Mat compress circuit and semiconductor memory device having the same: A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals... Agent: Ladas & Parry LLP

20100302887 - Semiconductor device: An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected... Agent: Robinson Intellectual Property Law Office, P.C.

20100302888 - Dynamic random access memory device and inspection method thereof: A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on... Agent: Sughrue Mion, PLLC

20100302889 - Semiconductor memory and system: A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of... Agent: Arent Fox LLP

20100302890 - Electrical fuse, semiconductor device having the same, and method of programming and reading the electrical fuse: Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the... Agent: F. Chau & Associates, LLC

20100302891 - Semiconductor device and method of driving the same: A semiconductor device includes a power-up operation unit configured to perform a power-up operation in response to a power-up enable signal and to output a powered-up control signal, and configured to output a power-up completion signal after the power-up operation is completed, an internal circuit configured to operate in response... Agent: Ip & T Group LLP

20100302892 - Semiconductor memory device and method of driving the same: A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.... Agent: Muir Patent Consulting, PLLC

20100302893 - Semiconductor memory device, memory controller that controls the same, and information processing system: To include a power-down control circuit that suspends an operation of a predetermined internal circuit in response to a power-down command, and an external terminal to which a selection signal is input from outside simultaneously with issuance of a power-down command. The power-down control circuit suspends an operation of a... Agent: Sughrue Mion, PLLC

20100302894 - Word line selection circuit and row decoder: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second... Agent: Foley And Lardner LLP Suite 500

20100302895 - Enhanced programmable pulsewidth modulating circuit for array clock generation: A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths.... Agent: Ibm Corporation (jvm)

20100302896 - Systems and methods for stretching clock cycles in the internal clock signal of a memory array macro: Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a... Agent: Law Offices Of Mark L. Berrier

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