|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
11/2010 | Recent | 14: | | | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval November recently filed with US Patent Office 11/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/25/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100296327 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source... Agent: Hunton & Williams LLP Intellectual Property Department
20100296328 - Buried bit line anti-fuse one-time-programmable nonvolatile memory: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over... Agent: Stout, Uxa, Buyan & Mullins LLP
20100296329 - Differential plate line screen test for ferroelectric latch circuits: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes.... Agent: Texas Instruments Incorporated
20100296330 - Semiconductor memory device: There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in... Agent: Birch Stewart Kolasch & Birch
20100296331 - Sensing resistance variable memory: The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold... Agent: Brooks, Cameron & Huebsch , PLLC
20100296333 - 8t sram cell with one word line: An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different... Agent: Texas Instruments Incorporated
20100296332 - Sram cell for single sided write: A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed... Agent: Texas Instruments Incorporated
20100296334 - 6t sram cell with single sided write: An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary... Agent: Texas Instruments Incorporated
20100296337 - 8t sram cell with four load transistors: An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of operating an integrated circuit containing SRAM cells with auxiliary load transistors... Agent: Texas Instruments Incorporated
20100296336 - 8t sram cell with two single sided ports: A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write and read operations, the auxiliary driver transistors... Agent: Texas Instruments Incorporated
20100296335 - Asymmetric sram cell with split transistors on the strong side: An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver... Agent: Texas Instruments Incorporated
20100296338 - Nonvolatile memory cell, nonvolatile memory device and method for driving the same: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of... Agent: Ip & T Group LLP
20100296339 - Nonvolatile semiconductor memory device having protection function for each memory block: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100296340 - Nanotube memory cell with floating gate based on passivated nanoparticles and manufacturing process thereof: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by... Agent: Graybeal Jackson Haley LLP
20100296343 - Non-volatile memory and semiconductor device: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz
20100296342 - Nonvolatile semiconductor memory device: When bit lines or sense amplifiers are checked whether they are defective during a test performed to check whether the bit lines are defectively open, an electrical current supplied from one sense amplifier is detected by another sense amplifier. Thus, if plural bit lines are defectively open, they can be... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100296341 - Semiconductor storage device and method of manufacturing same: The disclosure of this application enhances the data writing speed of an electrically erasable and writable semiconductor memory. In a semiconductor storage device of this application, at a time of writing data, when a positive voltage lower than a voltage at control gate 30 is applied to potential control gate... Agent: Foley & Lardner LLP
20100296344 - Methods of operating nonvolatile memory devices: Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is... Agent: Harness, Dickey & Pierce, P.L.C
20100296345 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100296346 - Nand memory device column charging: Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read... Agent: Schwegman, Lundberg & Woessner/micron
20100296347 - Method of erasing device including complementary nonvolatile memory devices: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and... Agent: Lee & Morse, P.C.
20100296348 - Erase operation control sequencing apparatus, systems, and methods: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied... Agent: Schwegman, Lundberg & Woessner/micron
20100296349 - Non-volatile semiconductor memory circuit with improved resistance distribution: Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability... Agent: Echelon Law Group, PC
20100296350 - Method of setting read voltage minimizing read data errors: A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one... Agent: Volentine & Whitt PLLC
20100296351 - Timing adjustment circuit, timing adjustment method, and correction value computing method: A timing adjustment circuit includes a determination unit for outputting delay information corresponding to a period of a first input signal, a storing unit for storing a plurality of correction values in accordance with a circuit included in the determination unit, a correction unit for correcting the delay information based... Agent: Arent Fox LLP
20100296352 - Memory controller for detecting read latency, memory system and test system having the same: A memory controller includes an I/O circuit, a read latency detector and a clock domain synchronizer. The I/O circuit transmits a first signal to a semiconductor memory device, receives a reflected signal returned from the semiconductor memory device, and delays the reflected signal in response to a delay selection signal... Agent: Volentine & Whitt PLLC
20100296353 - Semiconductor device: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be... Agent: F. Chau & Associates, LLC
20100296354 - Sram and method for accessing sram: A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit connected with the pair of bit lines and configured to precharge the pair of bit lines with a precharge... Agent: Foley And Lardner LLP Suite 500
20100296355 - Semiconductor device: A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The... Agent: Sughrue Mion, PLLC
20100296356 - Circuit for generating refresh period signal and semiconductor integrated circuit using the same: Circuits for generating refresh period signals and semiconductor integrated circuits using the same are presented. The refresh period signal generation circuit can include an oscillator, a pulse generation unit, and a signal controller. The oscillator is configured to generate an oscillation signal in response to a refresh duration correction signal.... Agent: Ladas & Parry LLP
20100296358 - Active driver control circuit for semiconductor memory apparatus: An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled,... Agent: Baker & Mckenzie LLP Patent Department
20100296357 - Semiconductor memory device: A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a... Agent: Ip & T Group LLP11/18/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100290262 - Three dimensional hexagonal matrix memory array: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100290263 - Circuit and method for controlling read cycle: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the... Agent: Ip & T Law Firm PLC
20100290264 - Optoelectronic memory devices: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being... Agent: Schmeiser, Olsen & Watts
20100290265 - Polymer-based ferroelectric memory: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and... Agent: Schwegman, Lundberg & Woessner/micron
20100290266 - Command processing circuit and phase change memory device using the same: A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command... Agent: Ip & T Law Firm PLC
20100290268 - Memory cell, pair of memory cells, and memory array: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which... Agent: Trask Britt, P.C./ Micron Technology
20100290267 - Semiconductor storage device: A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the... Agent: Arent Fox LLP
20100290269 - Static random access memory: Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connected to the power supply node. The variable capacitance circuit includes:... Agent: Knobbe Martens Olson & Bear LLP
20100290270 - Magnetic memory element, magnetic memory having said magnetic memory element, and method for driving magnetic memory: An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100290273 - Nonvolatile memory device: A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to... Agent: Ip & T Law Firm PLC
20100290274 - Nonvolatile memory device: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current... Agent: Ip & T Law Firm PLC
20100290271 - One-transistor, one-resistor, one-capacitor phase change memory: Memory devices and methods for operating such devices are described herein. A memory cell as described herein comprises a transistor electrically coupled to first and second access lines. A programmable resistance memory element is arranged along a current path between the first and second access lines. A capacitor is electrically... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100290275 - Phase change memory apparatus: A phase change memory apparatus is presented. The phase change memory apparatus includes a phase change memory cell, a sense amplifier, and a voltage selecting unit. The sense amplifier is configured to differentially amplify a current that through the memory cell and a comparison voltage. The voltage selecting unit is... Agent: Ladas & Parry LLP
20100290272 - Phase change memory device: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense... Agent: Ip & T Law Firm PLC
20100290277 - Resistive memory cell accessed using two bit lines: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory... Agent: Dicke, Billig & Czaja
20100290278 - Semiconductor memory device rewriting data after execution of multiple read operations: Provided is a semiconductor memory device including a memory cell; a writing driver providing a program current to the memory cell to write data in the memory cell; a sense amplifier processing a read operation reading data written in the memory cell; and a controller providing a rewriting signal for... Agent: Volentine & Whitt PLLC
20100290276 - Semiconductor memory using resistance material: A semiconductor memory includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line in response... Agent: Harness, Dickey & Pierce, P.L.C
20100290281 - Method for recording of information in magnetic recording element and method for recording of information in magnetic random access memory: Provided are a method for recording information in a magnetic recording element and a method for recording information in a magnetic random access memory. The method for recording information in a magnetic recording element includes preparing the magnetic recording element having a magnetic free layer in which a magnetic vortex... Agent: Ladas & Parry LLP
20100290280 - Semiconductor memory device: A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells,... Agent: Ip & T Law Firm PLC
20100290279 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data... Agent: Ip & T Law Firm PLC
20100290282 - Method and system for adaptively finding reference voltages for reading data from a mlc flash memory: A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, information about an initial threshold voltage distribution is firstly provided. A first threshold voltage in the initial threshold voltage distribution is then associated with a... Agent: Squire, Sanders & Dempsey L.L.P.
20100290283 - Programming method for flash memory device: Provided is a programming method that increases writing performance of a flash memory device. The programming method for a flash memory device that includes a plurality of banks including a plurality of memory cells for storing multi-bit data includes the following: programming a most significant bit (MSB) page with respect... Agent: Myers Bigel Sibley & Sajovec
20100290285 - Flash memory device using double patterning technology and method of manufacturing the same: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.... Agent: F. Chau & Associates, LLC
20100290284 - Single-transistor eeprom array and operation methods: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality... Agent: Slater & Matsil, L.L.P.
20100290286 - Multi-page parallel program flash memory: A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.... Agent: Mahamedi Paradice Kreisman LLP
20100290287 - Method circuit and system for operating an array of non-volatile memory (\"nvm\") cells and a corresponding nvm device: Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset... Agent: Professional Patent Solutions
20100290288 - Nonvolatile memory device and method of testing the same: A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read... Agent: Ip & T Law Firm PLC
20100290289 - Operating memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells... Agent: Brooks, Cameron & Huebsch , PLLC
20100290290 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the... Agent: Mcdermott Will & Emery LLP
20100290291 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100290292 - Semiconductor device: The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region,... Agent: Mcdermott Will & Emery LLP
20100290293 - Method of identifying logical information in a programming and erasing cell by on-side reading scheme: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage... Agent: Rabin & Berdo, PC
20100290294 - Signal margin improvement for read operations in a cross-point memory array: A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive... Agent: Unity Semiconductor Corporation
20100290295 - Semiconductor memory and system: A semiconductor memory includes a word line coupled to memory cells that transmits a word line signal; at least one word repeater circuit that includes a first load circuit disposed on the word line; a first dummy word line disposed along the word line that transmits a first dummy word... Agent: Arent Fox LLP
20100290298 - Fuse circuit and redundancy circuit: A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to... Agent: Ip & T Law Firm PLC
20100290299 - Semiconductor chip and method of repair design of the same: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along... Agent: Miles & Stockbridge PC
20100290296 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays... Agent: Ip & T Law Firm PLC
20100290297 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word... Agent: Ip & T Law Firm PLC
20100290300 - Semiconductor integrated device: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines,... Agent: Foley And Lardner LLP Suite 500
20100290301 - Memory array incorporating noise detection line: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected... Agent: Zagorin O'brien Graham LLP (023)
20100290302 - Fuse circuit and driving method thereof: A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit... Agent: Ip & T Law Firm PLC
20100290303 - Semiconductor device: A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the... Agent: Posz Law Group, PLC
20100290304 - Voltage stabilization circuit and semiconductor memory apparatus using the same: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in... Agent: Venable LLP
20100290305 - Systems and methods for dynamic power savings in electronic memory operation: Reduction of line delay is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control the bit line length for address... Agent: Qualcomm Incorporated
20100290306 - Circuit and method for shifting address: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands... Agent: Ladas & Parry LLP11/11/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100284209 - Integrated circuit memory systems and program methods thereof including a magnetic track memory array using magnetic domain wall movement: Provided are nonvolatile memory devices and program methods thereof. an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to... Agent: Myers Bigel Sibley & Sajovec
20100284210 - One-time programmable memory cell: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A... Agent: Farjami & Farjami LLP
20100284214 - Electronically scannable multiplexing device: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control... Agent: Fleit, Gibbons, Gutman, Bongini & Bianco P.l
20100284212 - Method for multilevel programming of phase change cells using adaptive reset pulses: A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or... Agent: Seed Intellectual Property Law Group PLLC
20100284213 - Method of cross-point memory programming and related devices: A reverse recovery current of a diode is used for programming a cross-point memory. Programming of a crossbar memory device, comprising a diode with preferably short charge carriers lifetime and a storage element by keeping the device at one polarity for a period of time and then switching it from... Agent: Daniel R. Shepard Contour Semiconductor, Inc.
20100284211 - Multilevel nonvolatile memory via dual polarity programming: A programming scheme and method of programming a non-volatile memory device for multilevel operation. The scheme includes defining two or more memory states, where at least one of the memory states is programmed with a positive polarity electrical pulse and at least one of the memory states is programmed with... Agent: Kevin L. Bray Ovonyx, Inc.
20100284216 - Information storage devices using magnetic domain wall movement and methods of operating the same: An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion... Agent: Myers Bigel Sibley & Sajovec
20100284215 - Magnetic memory with a thermally assisted writing procedure and reduced writing field: A magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure, comprising a magnetic tunnel junction formed from a ferromagnetic storage layer having a first magnetization adjustable at a high temperature threshold, a ferromagnetic reference layer having a fixed second magnetization direction, and an insulating layer,... Agent: Pearne & Gordon LLP
20100284217 - Magnetic memory element, driving method for the same, and nonvolatile storage device: A magnetic memory element (10) for use in a cross-point type memory is provided with a spin valve structure having a free layer (5), a nonmagnetic layer (4), and a pinned layer (3). The magnetic memory element is also provided with another nonmagnetic layer (6) on one surface of the... Agent: Rabin & Berdo, PC
20100284218 - Superlattice device, manufacturing method thereof, solid-state memory including superlattice device, data processing system, and data processing device: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer,... Agent: Sughrue Mion, PLLC
20100284219 - Multiple level program verify in a memory device: Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming... Agent: Leffert Jay & Polglaze, P.A.
20100284220 - Operation method of non-volatile memory: An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of... Agent: J C Patents
20100284221 - Nonvolatile memory device and method for controlling word line or bit line thereof: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The... Agent: Harness, Dickey & Pierce, P.L.C
20100284222 - Fuse circuit and flash memory device having the same: A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program... Agent: Townsend And Townsend And Crew, LLP
20100284224 - Flash memory device and erase method using the same: A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated... Agent: Townsend And Townsend And Crew, LLP
20100284223 - Nonvolatile semiconductor memory: The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of... Agent: Morrison & Foerster LLP
20100284225 - Nonvolatile memory device: A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral element and configured to generate a negative voltage.... Agent: Ip & T Law Firm PLC
20100284227 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program... Agent: Ip & T Law Firm PLC
20100284226 - Voltage generation circuit and nonvolatile memory device including the same: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first... Agent: Ip & T Law Firm PLC
20100284228 - Semiconductor device having data input/output unit connected to bus line: To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first,... Agent: Mcdermott Will & Emery LLP
20100284229 - Bitline voltage driver: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100284230 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off... Agent: Ip & T Law Firm PLC
20100284231 - Memory system, memory device, and output data strobe signal generating method: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more... Agent: Harness, Dickey & Pierce, P.L.C
20100284232 - Memory circuit and tracking circuit thereof: The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100284234 - Memory control method and memory control device: A memory control method that carries out first-in first-out access control for a memory having a plurality of storage areas, including: selecting, as write positions, an address of a storage area in a storage block having at least one or more storage areas and an address of a storage area... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100284233 - Semiconductor memory device: A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or... Agent: Ip & T Law Firm PLC
20100284235 - Method and control unit for operating a volatile memory, circuit arrangement, and trip recorder: A method for operating a volatile memory supplied with a supply signal arranged either as a first supply signal of a first supply signal source or a second supply signal of a second supply signal source. If an available first supply signal is present it is used otherwise the second... Agent: Cohen, Pontani, Lieberman & Pavane LLP11/04/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100277963 - Ic card: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected... Agent: Miles & Stockbridge PC
20100277962 - Media player with non-volatile memory: A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device,... Agent: Unity Semiconductor Corporation
20100277964 - Multi-bank memory: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.... Agent: Schwegman, Lundberg & Woessner/micron
20100277965 - Memory system having multiple vias at junctions between traces: An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened... Agent: Law Offices Of Mark L. Berrier
20100277966 - Memory array and storage method: A memory arrangement comprises a first memory transistor (11) for non-volatile storage of a first bit, a second memory transistor (17) for non-volatile storage of the first bit in inverted form, and a word line (29) that is connected to a control terminal (12) of the first memory transistor (11)... Agent: Cohen, Pontani, Lieberman & Pavane LLP
20100277967 - Graded metal oxide resistance based semiconductor memory device: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100277968 - Semiconductor memory device: A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100277969 - Structures for resistive random access memory cells: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side... Agent: Campbell Nelson Whipps, LLC
20100277970 - Static random accee memory device: Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100277971 - Method for reducing current density in a magnetoelectronic device: A method for reducing spin-torque current density needed to switch a magnetoelectronic device (200, 300, 400), includes applying (602) a voltage bias having a predetermined polarity to the magnetoelectronic device (200, 300, 400) that creates a spin-polarized current with spin torque transfer to a synthetic antiferromagnet free layer (206), applying... Agent: Ingrassia Fisher & Lorenz, P.C.
20100277972 - Semiconductor memory device including a plurality of memory cell arrays: First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second... Agent: Knobbe Martens Olson & Bear LLP
20100277973 - Metallic-glass-based phase-change memory: A phase-change material for use in a phase-change memory device is provided. The phase-change material includes at least one metal and is reversibly phase-changeable, switchable, to a detectable metallic glass state or to a detectable crystalline state thereof. There is also provided a phase-change memory, that includes at least one... Agent: Zaven Altounian
20100277976 - Magnetic memory devices including magnetic layers having different products of saturated magnetization and thickness and related methods: A magnetic memory device may include a tunnel barrier, a reference layer on a first side of the tunnel barrier, and a free layer on a second side of the tunnel barrier so that the tunnel barrier is between the reference and free layers. The free layer may include a... Agent: Myers Bigel Sibley & Sajovec
20100277975 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate... Agent: Ip & T Law Firm PLC
20100277974 - Single bit line smt mram array architecture and the programming method: An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an... Agent: Saile Ackerman LLC
20100277978 - Flash memory device having improved read operation speed: Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling... Agent: Volentine & Whitt PLLC
20100277979 - Msb-based error correction for flash memory system: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data... Agent: Myers Bigel Sibley & Sajovec
20100277977 - Nand flash memory: A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100277981 - Non-volatile memory with both single and multiple level cells: Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as... Agent: Brooks, Cameron & Huebsch , PLLC
20100277980 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality... Agent: Hogan Lovells US LLP
20100277982 - Semiconductor device with floating gate and electrically floating body: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that... Agent: Hunton & Williams LLP Intellectual Property Department
20100277983 - Two pass erase for non-volatile storage: Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word... Agent: Vierra Magen/sandisk Corporation
20100277984 - Nonvolatile semiconductor memory: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20100277985 - Verification method for nonvolatile semiconductor memory device: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz
20100277986 - Non-volatile field programmable gate array: A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and... Agent: Haynes And Boone, LLPIPSection
20100277989 - Increased capacity heterogeneous storage elements: Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the... Agent: Cantor Colburn LLP-ibm Yorktown
20100277990 - Integrated circuit having memory repair information storage and method therefor: A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to... Agent: Freescale Semiconductor, Inc. Law Department
20100277991 - Semiconductor memory device: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to... Agent: Mcdermott Will & Emery LLP
20100277987 - Semiconductor device and control method thereof: Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (100) from an external data source. MD includes a memory cell array (MCA) for storing the data including numbers in data blocks (DB) or memory cell array planes (MCAP). Each DB... Agent: Flh/spansion C/o Frommer Lawrence & Haug
20100277988 - Internal source voltage generation circuit and generation method thereof: An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal.... Agent: Ip & T Law Firm PLC
20100277992 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes output enable signal generation means configured to be reset in response to an output enable reset signal, count a DLL clock signal and an external clock signal, and generate an output enable signal in correspondence to a read command and an operating frequency; and activation... Agent: Ip & T Law Firm PLC
20100277993 - Method for tuning control signal associated with at least one memory device: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays... Agent: Lexmark International, Inc. Intellectual Property Law Department
20100277994 - Semiconductor memory device and operating method thereof: A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information path, a command path, a transfer block configured to transmit signals coupled... Agent: Ip & T Law Firm PLC
20100277995 - Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof: A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first... Agent: Muir Patent Consulting, PLLC
20100277998 - Maintenance of amplified signals using high-volatage-threshold transistors: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the... Agent: Leffert Jay & Polglaze, P.A.
20100277996 - Semiconductor device: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a... Agent: Miles & Stockbridge PC
20100277997 - Semiconductor memory device: The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured... Agent: Harness, Dickey & Pierce, P.L.C
20100277999 - Fuse circuit and semiconductor device having the same: A fuse circuit includes a fuse unit configured to drive an output terminal via a current path including a fuse in response to a fuse enable signal; and a comparison unit configured to be activated in response to an activation signal for comparing a reference voltage having a predetermined level... Agent: Ip & T Law Firm PLC
20100278002 - Circuit and method of providing current compensation: Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line.... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20100278000 - Memory device control for self-refresh mode: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii)... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100278001 - Semiconductor memory device: A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit... Agent: Volentine & Whitt PLLC
20100278003 - Address decoder and/or access line driver and method for memory devices: Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100278004 - Address receiving circuit for a semiconductor apparatus: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according... Agent: Baker & Mckenzie LLP Patent DepartmentPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150122:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.4211 seconds