|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
10/2010 | Recent | 14: Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval October categorized by USPTO classification 10/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/28/2010 > patent applications in patent subcategories. categorized by USPTO classification
20100271854 - Ternary content addressable memory having reduced leakage effects: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is... Agent: Mahamedi Paradice Kreisman LLP (nlmi)
20100271855 - Memory cell arrangements: In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region... Agent: Viering, Jentschura & Partner
20100271856 - Semiconductor memory device having hierarchically-constructed i/o lines: To provide main I/O lines(MIOX) arranged along an X direction; a plurality of I/O nodes(ND) arranged along the X direction; an amplifier circuit area(AMPA) including a plurality of amplifier circuits(AMP); a plurality of main I/O lines(MIOY) arranged along a Y direction, which respectively connect each of the main I/O lines(MIOX)... Agent: Young & Thompson
20100271857 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line... Agent: Hunton & Williams LLP Intellectual Property Department
20100271858 - Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines: Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may... Agent: Hunton & Williams LLP Intellectual Property Department
20100271860 - Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device: A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage... Agent: Wenderoth, Lind & Ponack L.L.P.
20100271863 - Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively... Agent: Wells St. John P.s.
20100271862 - Nonvolatile memory device: A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a... Agent: F. Chau & Associates, LLC
20100271859 - Nonvolatile memory element, nonvolatile semiconductor memory apparatus, and reading method and writing method therefor: A nonvolatile memory element (101) of the present invention comprises a resistance variable layer (112) which intervenes between a first electrode (111) and a second electrode (113) and is configured to include at least an oxide of a metal element of VI group, V group or VI group, and when... Agent: Mcdermott Will & Emery LLP
20100271861 - Variable-resistance memory device and its operation method: A variable-resistance memory device includes: memory cells; first wires; a second wire; a drive/control section; and a sense amplifier.... Agent: Sonnenschein Nath & Rosenthal LLP
20100271864 - Semiconductor device: A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of... Agent: Miles & Stockbridge PC
20100271865 - Semiconductor memory and program: A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is... Agent: Ogilvie Law Firm
20100271866 - Nonvolatile latch circuit: A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in... Agent: Mr. Jackson Chen
20100271869 - Phase change memory device having decentralized driving units: A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving... Agent: Ladas & Parry LLP
20100271868 - Phase change memory devices and memory systems including the same: A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a... Agent: Harness, Dickey & Pierce, P.L.C
20100271867 - Variable resistive memory device compensating bit line resistance: Provided is a variable resistance memory device. The variable resistance memory device may include first and second memory cells connected to different lengths of bit lines, respectively, and a select circuit, configured to select the first and second memory cells, which is connected to the first and second memory cells... Agent: Harness, Dickey & Pierce, P.L.C
20100271870 - Magnetic stack having assist layer: A magnetic memory cell having a ferromagnetic free layer and a ferromagnetic pinned reference layer, each having an out-of-plane magnetic anisotropy and an out-of-plane magnetization orientation and switchable by spin torque. The cell includes a ferromagnetic assist layer proximate the free layer, the assist layer having a low magnetic anisotropy... Agent: Campbell Nelson Whipps, LLC
20100271874 - Read disturb mitigation in non-volatile memory: Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for... Agent: Vierra Magen/sandisk Corporation
20100271875 - Compensating for variations in memory cell programmed state distributions: Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100271877 - Method, apparatus, and system for erasing memory: Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored... Agent: Schwegman, Lundberg & Woessner/micron
20100271876 - Semiconductor memory device with memory cell having charge accumulation layer and control gate and memory system: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2i, where i is a natural number and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100271878 - Injection method with schottky source/drain: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins, LLP
20100271879 - Semiconductor integrated circuit device: A semiconductor integrated circuit includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a common voltage generating circuit which maintains a fixed voltage supply capability, and a plurality of voltage generating circuits which are disposed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100271882 - Nonvolatile semiconductor memory apparatus comprising charge accumulation layer and control gate: A nonvolatile semiconductor memory apparatus includes memory cell strings, first and second bit lines, a first buffer, a second buffer, and a controlling unit. The memory cell strings each include memory cells. The first and second bit lines connected to the memory cell strings. The first buffer connects to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100271881 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100271880 - Techniques for controlling a direct injection semiconductor memory device: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first region via a bit line and... Agent: Hunton & Williams LLP Intellectual Property Department
20100271873 - 3-level non-volatile semiconductor memory device and method of driving the same: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch... Agent: Volentine & Whitt PLLC
20100271872 - Analog read and write paths in a solid state memory device: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20100271871 - Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage: Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less... Agent: Leffert Jay & Polglaze, P.A.
20100271883 - Method of erasing in non-volatile memory device: An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are... Agent: Muir Patent Consulting, PLLC
20100271884 - Communication device and method for erasing data from a communication device: A communication device and method for erasing data include setting erasing parameters and initializing the erasing parameters, erasing data in a target data block of the flash memory once, and calculate a current erasing count of the erased block, setting a first bit of the erased block as “0”. The... Agent: Altis Law Group, Inc. Attn: Steven Reiss
20100271885 - Reduced complexity array line drivers for 3d matrix arrays: A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100271886 - Semiconductor memory device and latency signal generating method thereof: A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to... Agent: Harness, Dickey & Pierce, P.L.C
20100271890 - Data i/o control signal generating circuit in a semiconductor memory apparatus: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the... Agent: Baker & Mckenzie LLP Patent Department
20100271889 - Delay locked loop circuit and method: Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter... Agent: Schwegman, Lundberg & Woessner/micron
20100271887 - Semiconductor memory device comprising variable delay unit: A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode... Agent: Volentine & Whitt PLLC
20100271888 - System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal... Agent: Fish & Richardson P.C.
20100271891 - Accessing memory cells in a memory circuit: Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell... Agent: Ryan, Mason & Lewis, LLP
20100271892 - Precharge method of semiconductor memory device and semiconductor memory device using the same: A precharge method of a semiconductor memory device that controls a precharge start time of each bank during a bank precharge operation, and a semiconductor memory device using the method, are provided. The device may latch an active or write order of respective banks and differently control precharge start times... Agent: F. Chau & Associates, LLC
20100271893 - Semiconductor memory device and data write and read methods thereof: A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating... Agent: Volentine & Whitt PLLC
20100271894 - Methods and apparatus for extending the effective thermal operating range of a memory: Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a... Agent: Dugan & Dugan, PC
20100271896 - Memory malfunction prediction system and method: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100271895 - Sram compatible embedded dram system with hidden refresh and dual port capabilities: An SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities includes a memory cell array comprised of a plurality of single-port memory cells with dual-port capability, a first and a second port access units connected to the memory cell array in order to access the memory cells,... Agent: Bacon & Thomas, PLLC
20100271897 - Anti-fuse memory cell and semiconductor memory device: An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a third voltage supplied... Agent: Mcginn Intellectual Property Law Group, PLLC
20100271898 - Access to multi-port devices: Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)
20100271899 - Digital filters for semiconductor devices: A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.... Agent: Fletcher Yoder (micron Technology, Inc.)10/21/2010 > patent applications in patent subcategories. categorized by USPTO classification
20100265748 - High density ternary content addressable memory: A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device... Agent: Law Office Of Ido Tuchman (yor)
20100265750 - Memory system with data line switching scheme: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block... Agent: Vierra Magen/sandisk Corporation
20100265751 - Multi-chip packages providing reduced signal skew and related methods of operation: A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip... Agent: Myers Bigel Sibley & Sajovec
20100265752 - Semiconductor storage device and method of fabricating the same: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first... Agent: Mcdermott Will & Emery LLP
20100265753 - Systems, methods and devices for arbitrating die stack position in a multi-die stack device: Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes an input/output buffer that drives an output... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100265749 - Three dimensionally stacked non volatile memory units: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a... Agent: Campbell Nelson Whipps, LLC
20100265754 - Semiconductor memory device and data processing device: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command,... Agent: Nixon Peabody, LLP
20100265755 - One time programmable read only memory and programming method thereof: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first... Agent: Jianq Chyun Intellectual Property Office
20100265756 - Ferroelectric memory bake for screening and repairing bits: A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data to the first capacitor, and (304) baking the first capacitor for a first specified period of time at a first selected temperature. A same state read... Agent: Texas Instruments Incorporated
20100265757 - Resistance change memory device and operation method of the same: A resistance change memory device includes: memory cells each having a current path in which a storage element, whose resistance changes according to the voltage applied, and an access transistor are connected in series; first wirings each connected to one end of the current path; second wirings each connected to... Agent: Sonnenschein Nath & Rosenthal LLP
20100265758 - Method for implementing an sram memory information storage device: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.
20100265760 - Nonvolatile latch circuit and logic circuit using the same: A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that... Agent: Mr. Jackson Chen
20100265759 - Raising programming current of magnetic tunnel junctions by applying p-sub bias and adjusting threshold voltage: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device and a word line selector having a source-drain path serially coupled to the MTJ device. A negative substrate bias voltage is connected to a body of the... Agent: Slater & Matsil, L.L.P.
20100265762 - Continuous plane of thin-film materials for a two-terminal cross-point memory: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of... Agent: Unity Semiconductor Corporation
20100265763 - Memory device including an electrode having an outer portion with greater resistivity: A memory cell includes a first electrode having a first region and a second region, a second electrode and a phase change material. The phase change material is interposed between the first electrode and the second electrode with the first region of the first electrode arranged closer to the phase... Agent: Coats & Bennett/qimonda
20100265761 - Non-volatile semiconductor memory circuit for generating write voltage: A non-volatile semiconductor memory circuit for generating a write voltage is presented. The non-volatile semiconductor memory circuit includes a memory cell and a voltage generator. The voltage generator provides a write voltage at a given target level that varies in accordance with an amount of current detected by the memory... Agent: Ladas & Parry LLP
20100265764 - Methods of accessing storage devices: Methods of accessing storage devices. The methods include rearranging a writing order of continuous first and second data according to a reading order, and writing the first and second data in a first and second storage region of the storage device, respectively, according to the writing order. The reading order... Agent: Harness, Dickey & Pierce, P.L.C
20100265765 - Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that... Agent: Lee & Morse, P.C.
20100265766 - Bandgap engineered charge trapping memory in two-transistor nor architecture: A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100265767 - Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100265768 - Semiconductor storage apparatus, control apparatus and control method: A semiconductor storage apparatus comprising: a plurality of cells that store data; a threshold determination section that determines, based on management information that is used to manage data, a binary or multiple-valued form by which values are written to a plurality of the individual cells and determines a threshold based... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100265769 - Semiconductor memory device: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between... Agent: F. Chau & Associates, LLC
20100265770 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory comprising: a first semiconductor layer having a first stripe-shaped region and a second stripe-shaped region which is adjacent to the first stripe-shaped region; a first NAND string formed on the first stripe-shaped region, the first NAND string having a plurality of first memory cell transistors connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100265771 - Method of programming memory cells of series strings of memory cells: Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string located between the target memory cell and a first end of the string, and verifying the programming of... Agent: Leffert Jay & Polglaze,p.a. Attn: Andrew C. Walseth
20100265772 - Nand memory device and programming methods: A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed... Agent: Schwegman, Lundberg & Woessner/micron
20100265773 - 3d memory array arranged for fn tunneling program and erase: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100265774 - Method for determining native threshold voltage of nonvolatile memory: A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell by using F-N tunneling effect to obtain a... Agent: J C Patents
20100265775 - Erasing flash memory using adaptive drain and/or gate bias: A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100265776 - Data bus power-reduced semiconductor storage apparatus: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100265777 - Memory device having strobe terminals with multiple functions: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of... Agent: Schwegman, Lundberg & Woessner/micron
20100265779 - Compensatory memory system: A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.... Agent: Texas Instruments Incorporated
20100265778 - Semiconductor memory device: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control... Agent: International Business Machines Corporation Dept. 18g
20100265780 - Semiconductor memory device having reduced power consumption during latency: A semiconductor memory device comprises a latency delay unit that toggles a delay clock signal on during a first interval between a time point where read burst signal is activated and a time point where a latency signal is activated, and subsequently toggling the delay clock signal on during a... Agent: Volentine & Whitt PLLC
20100265781 - Data retention kill function: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are... Agent: Michael G. Fletcher Fletcher Yoder
20100265782 - Hybrid sense amplifier and method, and memory device using same: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100265783 - Self-timed integrating differential current: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell.... Agent: Eschweiler & Associates LLC
20100265784 - Address control circuit of semiconductor memory apparatus: An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to... Agent: Ladas & Parry LLP
20100265785 - Protection circuit and power supply system for flash memory: A protection circuit, applied to a flash memory including a power supply pin, includes a capacitor and a switch. A power supply provides a reference voltage. The capacitor is electrically connected to the power supply pin and a ground point. The switch is electrically connected between the power supply pin... Agent: Edell, Shapiro & Finnan, LLC- None available for 10/01/2010
- None available for 10/7/2010
Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140306:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 0.41231 seconds