|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval September class, title,number 09/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/30/2010 > patent applications in patent subcategories. class, title,number
20100246234 - Stacked memory devices: A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups,... Agent: Harness, Dickey & Pierce, P.L.C
20100246235 - Memory cell heating elements: The present disclosure relates to the heating of memory cells.... Agent: Lee & Hayes, PLLC
20100246236 - Semiconductor memory device having layout area reduced: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a... Agent: Mcdermott Will & Emery LLP
20100246237 - Anti-fuse element: Programmable anti-fuse circuitry including at least one anti-fuse cell having a first anti-fuse device coupled between a supply voltage and a first node and a second anti-fuse device coupled between the first node and a ground voltage, and control logic coupled to the first node and arranged to generate a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100246238 - Method for mitigating imprint in a ferroelectric memory: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit... Agent: Hogan Lovells US LLP
20100246239 - Memory device using a variable resistive element: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory... Agent: Lee & Morse, P.C.
20100246240 - Semiconductor device configuration method: A plurality of three-terminal variable resistance switching elements each having a source electrode, a drain electrode, and a gate electrode are connected to each other in series. The source electrode of each of the three-terminal variable resistance switching elements and the drain electrode of its adjacent three-terminal variable resistance switching... Agent: Mr. Jackson Chen
20100246241 - Semiconductor device with source lines extending in a different direction: A semiconductor device includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction, a plurality of source lines formed along a third direction which is different from the first and the second directions, and a source line control circuit... Agent: Sughrue Mion, PLLC
20100246242 - Soft error robust storage sram cells and flip-flops: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes... Agent: Manoj Sachdev
20100246243 - Semiconductor storage device: A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a plurality of bit lines each connected... Agent: Young & Thompson
20100246244 - Magnetoresistive effect memory: A magnetoresistive effect memory of an aspect of the present invention including a magnetoresistive effect element including a first magnetic layer having an invariable magnetization direction, a second magnetic layer having a variable magnetization direction, and an interlayer provided between the first magnetic layer and the second magnetic layer, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246245 - Spin-torque memory with unidirectional write scheme: Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in... Agent: Campbell Nelson Whipps, LLC
20100246249 - Charge carrier stream generating electronic device and method: The present invention discloses an electronic device comprising a generator for generating a stream (125) of charge carriers. The generator comprises a bipolar transistor (100) having an emitter region (120), a collector region (160) and a base region (140) oriented between the emitter region (120) and the collector region (160),... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100246248 - Memory cell array biasing method and a semiconductor memory device: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first... Agent: F. Chau & Associates, LLC
20100246246 - Memory device, memory system having the same, and programming method of a memory cell: A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory... Agent: Lee & Morse, P.C.
20100246247 - Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same: A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured... Agent: Harness, Dickey & Pierce, P.L.C
20100246253 - Magnetic memory device, and manufacturing method thereof: To provide a magnetic memory device that can suppress the reduction of function of a magnetic memory element, and a manufacturing method thereof. A magnetic memory device includes a magnetic memory element capable of holding data based on a magnetized state thereof, and a digit line and a bit line... Agent: Mcdermott Will & Emery LLP
20100246254 - Magnetic memory with a thermally assisted writing procedure: A magnetic memory device of MRAM type with a thermally-assisted writing procedure, the magnetic memory device being formed from a plurality of memory cells, each memory cell comprising a magnetic tunnel junction, the magnetic tunnel junction comprising a magnetic storage layer in which data can be written in a writing... Agent: Pearne & Gordon LLP
20100246252 - Nonvolatile solid state magnetic memory and recording method thereof: A nonvolatile solid state magnetic memory with a ultra-low power consumption and a recording method thereof, the memory including a magnetic material having a magnetic anisotropy that can be changed by increasing or decreasing a carrier concentration, wherein a direction of an easy axis of magnetization, in which the magnetization... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246250 - Pipeline sensing using voltage storage elements to read non-volatile memory cells: Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100246251 - Predictive thermal preconditioning and timing control for non-volatile memory cells: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100246257 - Fabricating and operating a memory array having a multi-level cell region and a single-level cell region: Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the... Agent: Vierra Magen/sandisk Corporation
20100246259 - Flash memory device, programming method and memory system: Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a... Agent: Volentine & Whitt PLLC
20100246262 - Methods and control circuitry for programming memory cells: Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20100246258 - Nonvolatile memory device and related method of programming: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory... Agent: Volentine & Whitt PLLC
20100246260 - Nonvolatile memory device, system, and programming method: A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory... Agent: Volentine & Whitt PLLC
20100246261 - Programming a memory with varying bits per cell: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals... Agent: Leffert Jay & Polglaze, P.A.
20100246263 - Non-volatile memory device: This patent relates to a non-volatile memory device and a driving method thereof. The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate... Agent: Marshall, Gerstein & Borun LLP
20100246264 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the... Agent: Law Office Of Alan W. Cannon
20100246265 - Erase cycle counter usage in a memory device: Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in... Agent: Leffert Jay & Polglaze, P.A.
20100246266 - Nonvolatile memory device and related programming method: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program... Agent: Volentine & Whitt PLLC
20100246267 - Systems and methods of providing programmable voltage and current reference devices: The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a first source, a first drain, and a first gate. The first gate is... Agent: Troutman Sanders LLP 5200 Bank Of America Plaza
20100246268 - Method of programming nonvolatile memory device: In a method of programming a nonvolatile memory device, when a program is performed, a program voltage is applied to a first word line selected for the program. A first pass voltage is applied to three second word lines neighboring the first word line toward a source select line. First... Agent: Ip & T Law Firm PLC
20100246269 - Nonvolatile memory and methods for manufacturing the same with molecule-engineered tunneling barriers: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling... Agent: Marjama Muldoon Blasiak & Sullivan LLP
20100246271 - Analog sensing of memory cells with a source follower driver in a semiconductor memory device: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20100246272 - Apparatus comparing verified data to original data in the programming of a memory array: Apparatus configured to perform a programming operation on at least one memory cell of the memory array in response to original data, and further configured to perform a comparison of verified data of the at least one memory cell of the memory array to the original data following success of... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20100246270 - Charge loss compensation during programming of a memory device: A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed.... Agent: Leffert Jay & Polglaze, P.A.
20100246256 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes: a lower semiconductor layer; a first cell string having a plurality of memory cells formed on the lower semiconductor layer; an upper semiconductor layer formed above the lower semiconductor layer; and a second cell string having a plurality of memory cells formed on the upper... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246255 - Nonvolatile semiconductor storage device and method for controlling the same: A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246273 - Nonvolatile memory device and method of programming the device: A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register,... Agent: Ip & T Law Firm PLC
20100246274 - Semiconductor memory device having bit line pre-charge unit separated from data register: A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100246285 - Methods, devices, and systems relating to a memory cell having a floating body: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and... Agent: Trask Britt, P.C./ Micron Technology
20100246275 - Methods and apparatus related to a shared memory buffer for variable-sized cells: In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The... Agent: Juniper Networks, Inc.
20100246276 - Semiconductor memory device having swap function for data output pads: A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation... Agent: Lee & Morse, P.C.
20100246277 - Method of maintaining the state of semiconductor memory having electrically floating body transistor: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of... Agent: Law Office Of Alan W. Cannon
20100246278 - Accessing data within a memory formed of memory banks: A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said... Agent: Nixon & Vanderhye P.C.
20100246279 - Pipe latch circuit and semiconductor memory device using the same: A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation,... Agent: Cooper & Dunham, LLP
20100246280 - Semiconductor device having reset command: A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246281 - Sensing and latching circuit for memory arrays: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a... Agent: Michael Farjami, Esq. Farjami & Farjami LLP
20100246283 - Reference potential generating circuit of semiconductor memory: There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor... Agent: Volentine & Whitt PLLC
20100246284 - Semiconductor memory having electrically floating body transistor: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from... Agent: Law Office Of Alan W. Cannon
20100246282 - Voltage generator for memory array: A high voltage may be generated for programming memory cells in a memory array. A middle voltage may also be generated for reading memory cells in the memory array. Control logic and switches may be used to select between the high voltage and the middle voltage. A first oscillator generates... Agent: Schwegman, Lundberg & Woessner / Atmel
20100246286 - Nonvolatile memory device, method, system including the same, and operating method thereof: In a method of operating a nonvolatile memory device, data is read using a read level, and a range of logic values for erasure-decoding the read data is set. The bits of the read data corresponding to the set range of logic values are set as erasure bits, and an... Agent: Harness, Dickey & Pierce, P.L.C
20100246288 - Circuit and method for outputting data in semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to... Agent: Venable LLP
20100246287 - Storage devices with soft processing: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of... Agent: Occhiuti Rohlicek & Tsao, LLP
20100246289 - Storage devices with soft processing: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of... Agent: Occhiuti Rohlicek & Tsao, LLP
20100246292 - Cell inferiority test circuit: A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal... Agent: Cooper & Dunham, LLP
20100246291 - Method and apparatus for determining write leveling delay for memory interfaces: An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to... Agent: Patent Venture Group
20100246290 - Method and apparatus for gate training in memory interfaces: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the... Agent: Patent Venture Group
20100246295 - Semiconductor memory device comprising variable delay circuit: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external... Agent: Volentine & Whitt PLLC
20100246294 - System and method for delay locked loop relock mode: Embodiments of the present invention describe a memory device comprising a delay line and a feedback circuit coupled to the delay line. The feedback circuit has the capability to adjust a delay interval, which is then locked on the delay line. The feedback circuit is switched off after the delay... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100246293 - Tracking circuit for reducing faults in a memory: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the... Agent: Ryan, Mason & Lewis, LLP
20100246296 - Write driver and semiconductor memory device using the same: A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a... Agent: Ip & T Law Firm PLC
20100246297 - Integrated circuit having an embedded memory and method for testing the memory: A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional... Agent: Freescale Semiconductor, Inc. Law Department
20100246298 - Integrated circuit memory having assisted access and method therefor: A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for... Agent: Freescale Semiconductor, Inc. Law Department
20100246299 - Semiconductor storage device and redundancy method: A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100246301 - Method for testing a main memory: A method for testing a working memory which includes a matrix of memory cells, an address bus/address coder and a write circuit/read circuit, consists of two method parts with which in one step, at least a part of the address bus/address coder is tested with regard to address faults and... Agent: Panitch Schwarze Belisario & Nadel LLP
20100246300 - Semiconductor memory devices including burn-in test circuits: A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit... Agent: Myers Bigel Sibley & Sajovec
20100246302 - Semiconductor memory device: In a semiconductor memory device storing a resistance difference as information, a long time is taken so as to charge and/or discharge a selected cell by an equalizer circuit, which results in a difficulty of a high speed operation. A selection circuit puts, in a selected state, at least three... Agent: Sughrue Mion, PLLC
20100246303 - Sense amplifiers and exemplary applications: Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate... Agent: Lowe Hauptman Ham & Berner, LLP
20100246304 - Semiconductor memory device and refresh control method: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by... Agent: Scully Scott Murphy & Presser, PC
20100246305 - Regulators regulating charge pump and memory circuits thereof: A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with... Agent: Lowe Hauptman Ham & Berner, LLP
20100246306 - Start-up circuit of internal power supply of semiconductor memory: There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to... Agent: Volentine & Whitt PLLC
20100246307 - Internal power supply control circuit of semiconductor memory: An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined... Agent: Volentine & Whitt PLLC
20100246308 - Semiconductor storage device and control methods thereof: A semiconductor storage device and control method are provided. The semiconductor storage device includes a storage unit including a plurality of storage elements specified by addresses and divided into a plurality of blocks each corresponding to a plurality of the addresses, a write address decoding circuit that decodes a write... Agent: Staas & Halsey LLP
20100246309 - Semiconductor memory: An SRAM module includes bit cells arranged within an SRAM array of N×M, and a replica SRAM cell array of a replica bit cell used for bit cell performance measurement, and can control the number of replica bit cells used for performance measurement. When the clock generator circuit generates an... Agent: Miles & Stockbridge PC
20100246310 - Address converting circuit and semiconductor memory device using the same: A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address... Agent: Cooper & Dunham, LLP
20100246311 - Clock generators, memory circuits, systems, and methods for providing an internal clock signal: A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second... Agent: Lowe Hauptman Ham & Berner, LLP09/23/2010 > patent applications in patent subcategories. class, title,number
20100238693 - Configurable bandwidth memory devices and methods: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron
20100238695 - Memory module including memory chips: To provide a module substrate, memory chips mounted on the module substrate, and data input/output wirings that are connected respectively to the memory chips and read data or write data is transmitted thereto. The number of memory chips is equal to the number of bits of read data or write... Agent: Sughrue Mion, PLLC
20100238696 - Multi-chip packages including extra memory chips to define additional logical packages and related devices: A packaged integrated circuit device includes a primary chip stack and a secondary chip stack. The primary chip stack includes memory chips therein that define a logical package addressable by a memory controller. The secondary chip stack includes fewer memory chips than the primary chip stack. The memory chips of... Agent: Myers Bigel Sibley & Sajovec
20100238694 - Semiconductor storage device: A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold... Agent: Volentine & Whitt PLLC
20100238697 - Systems and devices including local data lines and methods of using, making, and operating the same: Disclosed are methods, systems and devices including local data lines. In some embodiments, the device includes a local data line connected to a plurality of access devices, at least a portion of a capacitor plate connected to the plurality of access devices, and a global data line connected to the... Agent: Mechael G. Fletcher Fletcher Yoder
20100238698 - Data writing and reading method for memory device employing magnetic domain wall movement: A method of data recording and reading for a memory device employing magnetic domain wall movement. The memory device includes a writing track, an interconnecting layer formed on the writing track, and a recording track formed on the interconnecting layer... Agent: Harness, Dickey & Pierce, P.L.C
20100238699 - Semiconductor memory and test method for the semiconducor memory: Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad... Agent: Knobbe Martens Olson & Bear LLP
20100238703 - Information recording/reproducing device: An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238709 - Memory devices including decoders having different transistor channel dimensions and related devices: An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass... Agent: Myers Bigel Sibley & Sajovec
20100238713 - Non-volatile register: A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element.... Agent: Unity Semiconductor Corporation
20100238710 - Nonvolatile memory device: A nonvolatile memory device, includes: a memory layer having a resistance changeable by performing at least one selected from applying an electric field and providing a current, the storage layer having a first major surface; a plurality of first electrodes provided on the first major surface; a plurality of probe... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238705 - Nonvolatile memory device and method system including the same: A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the... Agent: F. Chau & Associates, LLC
20100238708 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells shearing the same first wiring to configure a page;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238706 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device includes a memory core that includes plural banks, the bank including plural memory cells and a data write circuit that supplies a bias voltage to the memory cell, the memory core being logically divided into plural pages, the page including a predetermined number of memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238700 - Quiescent testing of non-volatile memory array: A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100238707 - Resistance change memory device: A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the... Agent: Knobbe Martens Olson & Bear LLP
20100238711 - Resistance-change memory: A resistance-change memory of an aspect of the present invention including a first bit line, second and third bit lines extending in a direction intersecting with the first bit line, first and second word lines, a first select transistor in which a control terminal thereof is connected to the first... Agent: Knobbe Martens Olson & Bear LLP
20100238701 - Semiconductor memory device: A memory cell arranged between first and second wirings includes a variable-resistor element. A controller controls a voltage applied between the first and second wirings. The controller performs a first operation that applies a first voltage between the first and second wirings to switch the variable-resistor element from a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238702 - Semiconductor memory device: A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition metal oxide, a proportion... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238704 - Semiconductor memory device, method of manufacturing the same, and method of screening the same: A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a second conductive film having one surface contacted with another surface of the variable resistance film. A width of the first conductive film or the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238712 - Variable write and read methods for resistive random access memory: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the... Agent: Campbell Nelson Whipps, LLC
20100238716 - Semiconductor memory device and semiconductor device group: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100238714 - Volatile memory elements with soft error upset immunity: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement... Agent: Treyz Law Group
20100238715 - Volatile memory elements with soft error upset immunity: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement... Agent: Treyz Law Group
20100238719 - Magnetic random access memory and operating method of the same: A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically... Agent: Mr. Jackson Chen
20100238717 - Magnetoresistive device and magnetic random access memory: A magnetoresistive device includes: a magnetic recording layer including a first magnetic layer having perpendicular magnetic anisotropy, and a second magnetic layer having in-plane magnetic anisotropy and being exchange-coupled to the first magnetic layer, Curie temperature of the second magnetic layer being lower than Curie temperature of the first magnetic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238718 - Semiconductor memory device: A semiconductor memory device includes a semiconductor substrate including an active area, a first select transistor in the active area, a first interconnection layer above the semiconductor substrate configured to run in a first direction, a first magnetoresistive element above the first interconnection layer including a fixed layer having a... Agent: Knobbe Martens Olson & Bear LLP
20100238720 - Electronic device, and method of operating an electronic device: An electronic device (100) comprising a heat transfer structure (103) and a phase change structure (104) which is convertible between two phase states by heating, wherein the phase change structure (104) is electrically conductive in at least one of the two phase states, wherein the heat transfer structure (103) is... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100238721 - Stuck-at defect condition repair for a non-volatile memory cell: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100238726 - Flash memory with multi-bit read: A memory device is described that comprises determining which read data state of more than 2X read data states a memory cell is in after the memory cell has been programmed to one of 2X program data states, wherein the determined read data state corresponds to X digits of read... Agent: Schwegman, Lundberg & Woessner/micron
20100238723 - Nonvolatile semiconductor memory device and method of operating the same: A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238725 - Nonvolatile semiconductor storage device and method of programming data therein: Each of the memory cells stores multiple bits of data by way of a threshold voltage distribution having a negative value and representing an erase state, and a plurality of threshold voltage distributions each having a value higher than the threshold voltage distribution representing the erase state and representing a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238724 - Semiconductor memory device and control method of the same: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by the counter circuit with a reference number (M),... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238727 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238728 - Method and apparatus of operating a non-volatile dram: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is... Agent: Saile Ackerman LLC
20100238729 - Non-volatile memory with reduced leakage current for unselected blocks and method for operating same: A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read... Agent: Vierra Magen/sandisk Corporation
20100238730 - Controlling select gate voltage during erase to improve endurance in non-volatile memory: A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In... Agent: Vierra Magen/sandisk Corporation
20100238733 - Nand flash memory: A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238732 - Non-volatile semiconductor storage device: When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238731 - Partial local self-boosting of a memory cell channel: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100238735 - Nonvolatile semiconductor memory device: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device,... Agent: Mcdermott Will & Emery LLP
20100238734 - Semiconductor non-volatile memory, charge accumulating method for semiconductor non-volatile memory, charge accumulating program storage medium: There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where... Agent: Volentine & Whitt PLLC
20100238722 - Nonvolatile semiconductor memory devices and voltage control circuit: A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2N (N=integer) where a reference resistance is indicated by R with the Ns being different from each other; and transistors corresponding to the respective resistance elements, the transistors being... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238736 - Semiconductor storage device: 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the... Agent: Posz Law Group, PLC
20100238737 - Bit line select voltage generator and nonvolatile memory device using the same: A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the... Agent: Townsend And Townsend And Crew, LLP
20100238738 - Eeprom having single gate structure and method of operating the same: An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions... Agent: Frank Chau, Esq. F. Chau & Associates, LLC
20100238739 - Nor flash memory device and related methods of operation: A NOR flash memory device is programmed by selecting one of a plurality of global bit lines and sequentially selecting a plurality of local bit lines commonly connected with the selected global bit line to supply a program voltage to memory cells.... Agent: Volentine & Whitt PLLC
20100238743 - Fast embedded bicmos-thyristor latch-up nonvolatile memory: This disclosure describes a new semiconductor non-volatile memory that can be potentially faster than DRAM and FLASH, and the manufacturing cost can be lower than SRAM, which is volatile. It is possible to fabricate an ULSI microprocessor and this type of new memory array in the same chip—realizing the “embedded”... Agent: James Pan
20100238741 - Semiconductor device and write control method for semiconductor device: To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell... Agent: Sughrue Mion, PLLC
20100238740 - Semiconductor memory device and driving method of the same: A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100238742 - Apparatus and method for outputting data of semiconductor memory apparatus: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or... Agent: Venable LLP
20100238745 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20100238744 - Semiconductor stroage device: A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have... Agent: Mcginn Intellectual Property Law Group, PLLC
20100238746 - Reading circuitry in memory: A reading circuit in a memory, having a first memory cell coupled to a first bit line and a second bit line, a second memory cell coupled to the second bit line and a third bit line and a third memory cell coupled to the third bit line and a... Agent: Rabin & Berdo, PC
20100238747 - Method and circuit of calibrating data strobe signal in memory controller: A method for calibrating a data strobe (DQS) signal and associated circuit is provided. The calibrating method includes determining N buffers from a delay chain having M buffers to delay a predetermined phase during a first period; serially connecting the N buffers of the delay chain during a second period;... Agent: Lee & Hayes, PLLC
20100238748 - Semiconductor memory device: A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100238749 - Semiconductor storage device: After a bit line is pre-charged by a pre-charge circuit that pre-charges the bit line, the voltage of a power supply for actuating a sense amplifier, which amplifies a signal read out from a memory cell, is switched.... Agent: Knobbe Martens Olson & Bear LLP
20100238750 - Control of inputs to a memory device: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy... Agent: Knobbe Martens Olson & Bear LLP
20100238751 - Method and apparatus for increasing yield in a memory device: An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply... Agent: Ryan, Mason & Lewis, LLP
20100238752 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a first region configured to operate at a specified first voltage, a second region configured to operate at a varying second voltage, and a memory device formed between the first region and the second region so as to straddle the first and second regions, wherein... Agent: SprinkleIPLaw Group
20100238754 - Clock and power fault detection for memory modules: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the... Agent: Perkins Coie LLP
20100238753 - Integrated circuits, systems, and methods for reducing leakage currents in a retention mode: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the... Agent: Lowe Hauptman Ham & Berner, LLP
20100238755 - Semiconductor memory device having power saving mode: A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit... Agent: Volentine & Whitt PLLC
20100238756 - Self reset clock buffer in memory devices: A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the... Agent: Qualcomm Incorporated09/16/2010 > patent applications in patent subcategories. class, title,number
20100232195 - Content addressable memory (cam) array capable of implementing read or write operations during search operations: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search... Agent: Mahamedi Paradice Kreisman LLP (nlmi)
20100232194 - Content addressable memory having bidirectional lines that support passing read/write data and search data: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense... Agent: Mahamedi Paradice Kreisman LLP (nlmi)
20100232197 - Data storage device: A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip activation signal generator to combine... Agent: Stanzione & Kim, LLP
20100232196 - Multi-chip package semiconductor memory device providing active termination control: A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second... Agent: Volentine & Whitt PLLC
20100232198 - Semiconductor storage device: A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232199 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232201 - Stacked semiconductor memory device: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory... Agent: Young & Thompson
20100232200 - Vertical switch three-dimensional memory array: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F2.... Agent: Goodwin Procter LLP Patent Administrator
20100232202 - Dual port memory device: A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first... Agent: Larson Newman & Abel, LLP
20100232203 - Electrical anti-fuse and related applications: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause... Agent: Lowe Hauptman Ham & Berner, LLP
20100232209 - Control circuit for forming process on nonvolatile variable resistive element and control method for forming process: A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line)... Agent: Nixon & Vanderhye, PC
20100232211 - Memory array with read reference voltage cells: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage... Agent: Campbell Nelson Whipps, LLC
20100232208 - Method of executing a forming operation to variable resistance element: A method of executing a forming operation to a variable resistance element to render a resistance value of the variable resistance element capable of transition, the variable resistance element being included in a memory cell connected between a first wiring and a second wiring and changing the resistance value by... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232206 - Non-volatile memory read/write verify: An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100232207 - Nonvolatile semiconductor memory device and method of resetting the same: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232205 - Programmable resistance memory: A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.... Agent: Ovonyx, Inc
20100232204 - Resistance variable element, nonvolatile switching element, and resistance variable memory apparatus: A resistance variable element comprises a first electrode (2), a second electrode (4), and a resistance variable layer (3) which is disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, wherein the resistance variable layer comprises material including TaOX... Agent: Mcdermott Will & Emery LLP
20100232210 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes variable resistance elements arranged in a memory area and configured to store data according to a resistance variation, each of the variable resistance elements having a first terminal electrically connected to a first line and a second terminal electrically connected to a second line, and... Agent: Knobbe Martens Olson & Bear LLP
20100232213 - Control signal transmitting system of a semiconductor device: Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half... Agent: F. Chau & Associates, LLC
20100232212 - Split-gate dram with lateral control-gate mugfet: A semiconductor structure of an array of dynamic random access memory cells. The structure includes: a first fin of a first split-gate fin-type field effect transistor (FinFET) device on a substrate; a second fin of a second split-gate fin-type field effect transistor (FinFET) device on the substrate; and a back-gate... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department
20100232214 - Static memory memory point and application to an image sensor: The invention relates to a memory point of SRAM (static memory) type memory. The memory point conventionally comprises two inverters mounted head-to-tail between two nodes, and at least one access transistor able to be made conductive during a writing phase and linked between a first node and a line of... Agent: Lowe Hauptman Ham & Berner, LLP
20100232215 - Mram with coupling valve switching: The free layer in a magneto-resistive memory element is stabilized through being pinned by an antiferromagnetic layer. A control valve layer provides exchange coupling between this antiferromagnetic layer and the free layer. When writing data into the free layer, the control valve layer is heated above its curie point thereby... Agent: Saile Ackerman LLC
20100232217 - Method for efficiently driving a phase change memory device: A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state.... Agent: Ladas & Parry LLP
20100232218 - Method of testing pram device: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data... Agent: Volentine & Whitt PLLC
20100232216 - Phase-change memory device: A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each... Agent: Ip & T Law Firm PLC
20100232220 - Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic devices and methods of making electronic devices: Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first... Agent: Trask Britt, P.C./ Micron Technology
20100232219 - Micromagnetic elements, logic devices and related methods: Micromagnetic elements, logic devices and methods of fabricating and using them to store data and perform logic operations are disclosed. Micromagnetic elements for data storage, as well as those providing output from a logic device, are at least partially covered with an optical coating that facilitates determination of the magnetic... Agent: Lathrop & Gage LLP
20100232222 - Memory page boosting method, device and system: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When... Agent: Trask Britt, P.C./ Micron Technology
20100232221 - Nonvolatile memory device and method of reading same: A method of reading a nonvolatile memory device comprises sensing data stored in memory cells adjacent to selected memory cells to identify adjacent aggressor cells, and performing separate precharge operations on bitlines connected to selected memory cells having adjacent aggressor cells and on bitlines connected to selected memory cells having... Agent: Volentine & Whitt PLLC
20100232223 - Defective block handling method for a multiple data channel flash memory storege device: The block groups of a multiple data channel flash memory storage device are detected for defective blocks. The block group containing any defective blocks is divided into subgroups, each of which contains only defective blocks or only good blocks. The subgroups containing only good blocks are selected to establish a... Agent: Rosenberg, Klein & Lee
20100232224 - Non-volatile semiconductor storage device: A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portions, and a joining portion formed to join the lower ends thereof. An electric... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232225 - Semiconductor storage device: A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232228 - Memory device, memory system and programming method: A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing... Agent: Volentine & Whitt PLLC
20100232227 - Non-volatile memory device and program method thereof: A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be... Agent: F. Chau & Associates, LLC
20100232226 - Solid state storage system for uniformly using memory area and method controlling the same: A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and... Agent: Ladas & Parry LLP
20100232229 - Semiconductor memory device including stacked gate including charge accumulation layer and control gate: A semiconductor memory device includes a memory cell, a bit line, a source line, a source line driver, a sense amplifier, a counter, a detector, a controller. The sense amplifier reads the data by sensing current flowing through the bit line. The counter counts ON memory cells and/or OFF memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232230 - Non-volatile semiconductor memory device: When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232231 - Semiconductor nonvolatile memory device: e
20100232233 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device in which a negative-threshold cell read operation is performed by biasing a source line and well line to a positive voltage includes a first drive circuit that sets at least unselected word line in a floating state at a negative-threshold cell read time.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100232232 - Semiconductor integrated circuit device: This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes... Agent: Miles & Stockbridge PC
20100232235 - Memory device having buried boosting plate and methods of operating the same: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array.... Agent: Fletcher Yoder (micron Technology, Inc.)
20100232234 - Memory device having improved programming operation: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.... Agent: Schwegman, Lundberg & Woessner/micron
20100232236 - Sram leakage reduction circuit: A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vth across the memory cells, where... Agent: Patent Law Office Of D.r. Haszko C/o Dennis R. Haszko
20100232237 - High speed dram architecture with uniform access latency: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100232238 - Dual port memory device, memory device and method of operating the dual port memory device: A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port... Agent: Birch Stewart Kolasch & Birch
20100232239 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a... Agent: Ladas & Parry LLP
20100232240 - Columnar replacement of defective memory cells: Circuits and methods to compensate for defective memory in BEOL third dimensional memory technology are described. An integrated circuit is configured to perform columnar replacement of defective BEOL multi-layered memory. For example, the integrated circuit can include a primary BEOL memory array having a plurality of BEOL memory cells being... Agent: Unity Semiconductor Corporation
20100232241 - Redundancy architecture for an integrated circuit memory: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group... Agent: Nixon & Vanderhye, PC
20100232242 - Method for constructing shmoo plots for srams: A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.... Agent: Texas Instruments Incorporated
20100232243 - Differential sense amplifier: The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second differential amplification unit that detects a difference between one... Agent: Sughrue Mion, PLLC
20100232244 - Semiconductor memory device: A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the... Agent: Knobbe Martens Olson & Bear LLP
20100232245 - Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation: Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100232247 - Data storage apparatus and control method of data storage apparatus: In a data storage apparatus having data storage means, if it is judged that a condition of transitioning the data storage apparatus into a power saving state is established, it is controlled so that states of signals to be output by operation control means of controlling an operation of the... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100232246 - Refresh control circuit and method for semiconductor memory apparatus: A refresh control circuit of a semiconductor memory apparatus includes: a variable oscillator configured to generate a room-temperature oscillation signal and a limit-temperature oscillation signal in response to a temperature state signal; a cycle selector configured to selectively output the room temperature oscillation signal and the limit-temperature oscillation signal as... Agent: Echelon Law Group, PC
20100232248 - Implementing efuse resistance determination before initiating efuse blow: A method and an eFuse programming circuit for implementing resistance determination of an eFuse before initiating eFuse blow, and a design structure on which the subject circuit resides are provided. An eFuse on a chip is used to set current flow through a known resistor and measure the eFuse resistance.... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100232249 - Multi-port semiconductor memory device having variable access paths and method therefor: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and... Agent: Muir Patent Consulting, PLLC
20100232250 - Interface circuit and method for coupling between a memory device and processing circuitry: Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder... Agent: Nixon & Vanderhye P.C.
20100232251 - Method and system for coding and read out of information in a microscopic cluster comprising coupled functional islands: A method and a system for coding and reading out information in a microscopic cluster formed with coupled functional islands includes: generating the cluster by forming a regular microscopic pattern for locating the functional islands; making use of a physical or chemical property of each individual island and making use... Agent: Lerner Greenberg Stemer LLP09/09/2010 > patent applications in patent subcategories. class, title,number
20100226161 - Ternary content addressable memory using phase change devices: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements... Agent: Law Office Of Ido Tuchman (yor)
20100226162 - Memory array power domain partitioning: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.... Agent: Texas Instruments Incorporated
20100226163 - Method of resistive memory programming and associated devices and materials: A pulse coupled with a microwave field is used for programming a resistive memory into one of non-volatile states. As the result, the programming becomes faster and more energy efficient. Related devices and materials are also described.... Agent: Daniel R. Shepard Contour Semiconductor, Inc
20100226164 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100226165 - Resistive memory devices having a stacked structure and methods of operation thereof: A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes... Agent: Myers Bigel Sibley & Sajovec
20100226166 - Mos capacitor and charge pump with mos capacitor: A MOS capacitor in a charge pump includes a MOS device with at least one body bias region and a device body of a same conductivity type for providing maximum capacitance over a wide voltage range. The MOS capacitor also includes a gate forming a first terminal of the MOS... Agent: Law Office Of Monica H Choi
20100226167 - Magnetic memory: A spin-transfer magnetic memory includes a magnetoresistive element having a pinned layer, a free layer and a tunnel insulating layer provided between the pinned layer and the free layer, a bit line connected to one terminal of the magnetoresistive element, a select transistor having a current path whose one terminal... Agent: Knobbe Martens Olson & Bear LLP
20100226168 - Programming methods for phase-change memory: Set pulses with finite rise time that heat up phase change alloy between about nucleation temperature and about average of crystallization and melting temperatures are proposed for programming phase change memory from reset to set state in order to minimize energy during this transition and to achieve uniform set state... Agent: Daniel R. Shepard Contour Semiconductor, Inc.
20100226169 - Stram with compensation element and method of making the same: Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic... Agent: Campbell Nelson Whipps, LLC
20100226175 - Memory devices and methods of writing data to memory devices utilizing analog voltage levels: Memory devices, and methods of writing data to memory devices, utilizing analog voltage levels indicative of threshold voltages and desired threshold voltages of memory cells.... Agent: Leffert Jay Polglaze, P.A. Attn: Thomas W. Leffert
20100226176 - Method for non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100226171 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes receiving a program command, performing program and verification operations in response to each of a number of program pulse, and performing an n number of program operations, where n is a positive integer and at least one verification operation for the... Agent: Ip & T Law Firm PLC
20100226172 - Method of reading data and method of inputting and outputting data in non-volatile memory device: A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of... Agent: F. Chau & Associates, LLC
20100226174 - Multiple bit per cell non volatile memory apparatus and system having polarity control and method of programming same: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize... Agent: Mosaid Technologies Incorporated
20100226170 - Non-volatile memory array having circuitry to complete programming operation in the event of power interrupt: An electrically programmable non-volatile memory device comprises a memory circuit which includes an array of non-volatile memory cells. Each memory cell is capable of being programmed. A programming circuit can generate a programming signal to program one or more of the memory cells. A voltage detector circuit is connected to... Agent: Dla Piper LLP (us )
20100226177 - Non-volatile multilevel memory cells: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a... Agent: Brooks, Cameron & Huebsch , PLLC
20100226178 - Apparatus and methods for correcting over-erased flash memory cells: A method and flash memory device that correct over-erased memory cells are described. The device includes flash memory cells, erase circuitry, measuring circuitry, and a pulse generator. The method includes performing an erase operation on a first plurality of memory cells, measuring at least one memory cell of a second... Agent: Viering, Jentschura & Partner
20100226179 - Nand flash architecture with multi-level row decoding: A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select... Agent: Smart & Biggar P.o. Box 2999, Station D
20100226180 - Memory array and method of operating a memory: A memory array is described, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source... Agent: J C Patents
20100226181 - Array of non-volatile memory cells including embedded local and global reference cells and system: A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection... Agent: Dla Piper LLP (us )
20100226182 - Methods of forming and operating nand memory with side-tunneling: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from... Agent: Patterson Thuente Christensen Pedersen, P.A.
20100226173 - Nonvolatile semiconductor memory device: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20100226183 - Partial block erase architecture for flash memory: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore,... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100226186 - Partial write-back in read and write-back of a memory: An integrated circuit having a functional memory and methods of operating and reducing an operating power of the integrated circuit are provided. The functional memory includes an array of memory cells connected to row and column periphery units and organized in corresponding rows and columns. The memory also includes a... Agent: Texas Instruments Incorporated
20100226184 - Data input/output circuit and method of semiconductor memory apparatus: A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the... Agent: Venable LLP
20100226185 - Semiconductor memory module and semiconductor memory system having termination resistor units: A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a... Agent: Volentine & Whitt PLLC
20100226187 - Semiconductor memory device: A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair... Agent: Mills & Onello LLP
20100226189 - Delay locked loop circuit including delay line with reduced sensitivity to variation in pvt: A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control... Agent: Muir Patent Consulting, PLLC
20100226188 - First delay locking method, delay-locked loop, and semiconductor memory device including the same: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the... Agent: Muir Patent Consulting, PLLC
20100226190 - Sram and testing method of sram: An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the... Agent: Young & Thompson
20100226191 - Leakage reduction in memory devices: A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches... Agent: Qualcomm Incorporated
20100226192 - Semiconductor memory device having improved local input/output line precharge scheme: A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of... Agent: Lee & Morse, P.C.
20100226193 - Semiconductor memory device: A unit memory circuit includes a fuse element capable of electrically programming data. A sense amplifier circuit is connected to the fuse element. The sense amplifier circuit senses data of the fuse element. Either of a first interconnect and a second interconnect is selectively formed by changing an interconnect formation... Agent: Turocy & Watson, LLP
20100226194 - Power-failure protection circuit for non-volatile semiconductor storage devices and method for preventing unexpected power-failure using the same: A power failure protection circuit (10) for a non-volatile semiconductor storage device includes at least an energy storage unit (C1) that serves as a backup power supply for providing backup electrical energy when a power failure occurs. During normal operation of the device, a main control unit (12) is responsible... Agent: Matthias Scholl
20100226195 - Integrated circuit self aligned 3d memory array and manufacturing method: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100226196 - Duty cycle corrector preventing excessive duty cycle correction in low-frequency domain: Provided is a duty cycle corrector including a low frequency detector detecting whether an input clock signal frequency is less than or greater than a predetermined frequency. If less than, a common mode control circuit controlling a common mode of a duty cycle correction amplifier amplifying the input clock signal... Agent: Volentine & Whitt PLLC09/02/2010 > patent applications in patent subcategories. class, title,number
20100220509 - Selective activation of programming schemes in analog memory cell arrays: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not... Agent: D. Kligler I.p. Services Ltd
20100220510 - Optimized selection of memory chips in multi-chips memory devices: A method includes accepting a definition of a type of multi-unit memory device (28) including a set of memory units (24), each having a respective nominal storage capacity, the definition specifying a target memory size of the memory device such that a sum of nominal storage capacities of the memory... Agent: D. Kligler I.p. Services Ltd
20100220511 - Low power antifuse sensing scheme with improved reliability: Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100220513 - Bi-directional resistive memory devices and related memory systems and methods of writing data: A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and... Agent: Myers Bigel Sibley & Sajovec
20100220512 - Programmable power source using array of resistive sense memory cells: Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100220514 - Storage devices with soft processing: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of... Agent: Occhiuti Rohlicek & Tsao, LLP
20100220515 - Semiconductor memory device and test method therefor: Provided is a semiconductor memory device including: first and second SRAM cells; a first bit line pair provided with the first SRAM cell; a second bit line pair provided with the second SRAM cell; a first switch circuit provided between the first bit line pair and the second bit line... Agent: Foley And Lardner LLP Suite 500
20100220516 - Reducing source loading effect in spin torque transfer magnetoresisitive random access memory (stt-mram): Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an... Agent: Qualcomm Incorporated
20100220517 - Semiconductor device: Data which sets up operation parameters, etc. of an internal circuit is supplied stably over a long period of time. In a cell array in which MRAM cells are arranged, read/write of test data is performed in a PROM mode. Finally, data writing is specifically performed to the memory cells... Agent: Mcdermott Will & Emery LLP
20100220518 - Thermally assisted multi-bit mram: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.... Agent: Campbell Nelson Whipps, LLC
20100220520 - Multi-bit phase change memory devices: A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three... Agent: Harness, Dickey & Pierce, P.L.C
20100220522 - Phase change random access memory and method of controlling read operation thereof: A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is... Agent: Volentine & Whitt PLLC
20100220521 - Phase change random access memory device and related methods of operation: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of... Agent: Volentine & Whitt PLLC
20100220519 - Sensing characteristic evaluating apparatus for semiconductor device and method thereof: A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an input/output line during a test mode for evaluating a sensing characteristic, and a sensing amplifying circuit configured to receive the test current from the input/output line, to... Agent: Ip & T Law Firm PLC
20100220523 - Stochastic synapse memory element with spike-timing dependent plasticity (stdp): An active memory element is provided. One embodiment of the invention includes a bi-polar memory two-terminal element having polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a difference between received signals at... Agent: Kenneth L. Sherman, Esq. C/o Myers Andras Sherman LLP
20100220524 - Magnetic booster for magnetic random access memory: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost... Agent: Hahn And Moodley, LLP
20100220525 - Non-volatile memory device and erase and read methods thereof: An erase method of a non-volatile memory device includes first erasing memory cells of a non-volatile memory device with a first erase voltage; in response to a judgment that the erasure of at least one of the memory cells has failed, determining an amount of voltage to add to the... Agent: F. Chau & Associates, LLC
20100220526 - Nonvolatile memory device, system, and programming method: A nonvolatile memory device stores program data in a first address area, determines whether the first address area is a most significant address area and whether the program data is reliable data, and upon determining that the first address area is not a most significant address area and that the... Agent: Volentine & Whitt PLLC
20100220527 - Non-volatile fifo with third dimension memory: A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that... Agent: Unity Semiconductor Corporation
20100220528 - Nand with back biased operation: Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of... Agent: Leffert Jay & Polglaze, P.A.
20100220529 - Non-volatile memory device: A non-volatile memory device includes a sensing circuit that is configured to detect a charge of a common source line and a voltage controller that is configured to vary a level of a voltage being inputted to a word line in response to a result of the detection of the... Agent: Townsend And Townsend And Crew, LLP
20100220530 - Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory: An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100220531 - Semiconductor integrated circuit: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold... Agent: Miles & Stockbridge PC
20100220532 - Readout circuit for rewritable memories and readout method for same: In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by... Agent: Cohen, Pontani, Lieberman & Pavane LLP
20100220533 - Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from... Agent: Dla Piper LLP (us )
20100220534 - Memory device with reduced buffer current during power-down mode: A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part... Agent: Ryan, Mason & Lewis, LLP
20100220535 - Non-volatile memory device: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline.... Agent: Volentine & Whitt PLLC
20100220536 - Advanced memory device having reduced power and improved performance: A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits... Agent: Cantor Colburn LLP-ibm Yorktown
20100220537 - Active termination circuit and method for controlling the impedance of external integrated circuit terminals: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled... Agent: Round Lerner, David, Littenberg, Krumholz & Mentlik, LLP
20100220538 - Integrated circuit memory power supply: An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12. Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34. The power supply circuitry 10, 12 is then configured to alter the voltage supply to... Agent: Nixon & Vanderhye P.C.
20100220539 - Memory circuits, systems, and operating methods thereof: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBLref to the bit line, wherein a... Agent: Lowe Hauptman Ham & Berner, LLP
20100220540 - Semiconductor memory device capable of driving non-selected word lines to first and second potentials: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation... Agent: Arent Fox LLP
20100220541 - Switched-capacitor charge pumps: A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level... Agent: Ibm Corporation (jvm)
20100220542 - Integrated circuit memory access mechanisms: A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40... Agent: Nixon & Vanderhye P.C.
20100220543 - Circuitry and method for indicating a memory: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of... Agent: Unity Semiconductor CorporationPrevious industry: Electric power conversion systems
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