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Static information storage and retrieval August inventions list 08/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/26/2010 > patent applications in patent subcategories.
20100214811 - Coding techniques for improving the sense margin in content addressable memories: A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the... Agent: Law Office Of Ido Tuchman (yor)
20100214813 - Memory module having a plurality of phase change memories, buffer ram and nand flash memory: A memory module comprises a plurality of main memories; a buffer RAM configured to temporarily store data being provided to or read from the main memories and to perform a buffer function between an external device and the main memories; and a NAND flash memory configured to store data of... Agent: Harness, Dickey & Pierce, P.L.C
20100214812 - Stacked semiconductor devices including a master device: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).... Agent: Mosaid Technologies Incorporated
20100214814 - Semiconductor memory device, memory device support and memory module: In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include... Agent: Harness, Dickey & Pierce, P.L.C
20100214815 - Multiple threshold voltage register file cell: In one embodiment, a memory circuit comprises a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage.... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20100214816 - Semiconductor devices supporting multiple fuse programming modes: Semiconductor devices include a plurality of fuses and a plurality of program circuits, respective ones of which are configured to program respective ones of the plurality of fuses. The devices further include a shift register configured to activate at least two of the program circuits. In some embodiments, the shift... Agent: Myers Bigel Sibley & Sajovec
20100214817 - Semiconductor storage device and storage system: A pn junction type solar cell is formed in a predetermined region on a substrate made of glass. Light emitted from a light emitting unit reaches an n-type semiconductor layer after it passed through substrate. The solar cell generates electromotive force corresponding to a quantity of the emitted light. A... Agent: Birch Stewart Kolasch & Birch
20100214821 - Capacitive divider sensing of memory cells: The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.... Agent: Brooks, Cameron & Huebsch , PLLC
20100214818 - Memory device and operation method of the same: Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a voltage applied and an access transistor connected in series between the first and second wires; driving control sections controlling... Agent: Rader Fishman & Grauer PLLC
20100214819 - Resistive memory devices, memory systems and methods of controlling input and output operations of the same: A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage,... Agent: Myers Bigel Sibley & Sajovec
20100214820 - Semiconductor memory device: A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines and a control circuit configured to apply a first voltage to selected one or more of the first lines, and to apply... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214823 - Semiconductor device including memory cell having capacitor: A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100214822 - Voltage-stepped low-power memory device: This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part... Agent: Pvf -- Rambus, Inc. C/o Park, Vaughan & Fleming, LLP
20100214824 - Converting sram cells to rom cells: A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled... Agent: Nixon & Vanderhye P.C.
20100214826 - Magnetic random access memory, write method therefor, and magnetoresistance effect element: A magnetic random access memory includes: a first ferromagnetic layet; an insulating layer provided adjacent to the first ferromagnetic layer; and a first magnetization pinned layer provided adjacent to the insulating layer on a side opposite to the first ferromagnetic layer. The first ferromagnetic layer includes a magnetization free region,... Agent: Mr. Jackson Chen
20100214825 - Programming mram cells using probability write: A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the... Agent: Slater & Matsil, L.L.P.
20100214827 - Integrated circuit with memory cells comprising a programmable resistor and method for addressing memory cells comprising a programmable resistor: A module comprises a bus invert encoder (24) for determining whether a set of data bits should be inverted prior to transmission over a communication bus. The bus invert encoder (24) produces a bus invert signal BI which controls a selective inversion means (28), for example a multiplexer. A partial... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100214831 - Memory device, memory system having the same, and programming method of a memory cell: A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing... Agent: Lee & Morse, P.C.
20100214829 - Memory programming: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits... Agent: Cantor Colburn LLP-ibm Yorktown
20100214830 - Memory reading method for resistance drift mitigation: Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes... Agent: Law Office Of Ido Tuchman (yor)
20100214832 - Phase-change random access memory: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of... Agent: F. Chau & Associates, LLC
20100214828 - Semiconductor device: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current.... Agent: Miles & Stockbridge PC
20100214833 - Semiconductor device: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the... Agent: Mattingly & Malur, P.C.
20100214834 - Thin film magnetic memory device including memory cells having a magnetic tunnel junction: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read data bus... Agent: Mcdermott Will & Emery LLP
20100214835 - Magnetic shielding in magnetic multilayer structures: Techniques and device designs associated with devices having magnetically shielded magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves that are configured to operate based on spin-transfer torque switching.... Agent: Fish & Richardson, PC
20100214837 - Nonvolatile semiconductor memory with charge storage layers and control gates: A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214838 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214840 - Multi-dot flash memory and method of manufacturing the same: A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214839 - Nand flash memory string apparatus and methods of operation thereof: A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP
20100214846 - Flash memory devices, methods for programming the same, and memory systems including the same: A programming method of a nonvolatile memory device is provided including: applying a local voltage to a first unselected word line; applying a local voltage to a second unselected word line, after the local voltage is applied to the first unselected word line; and applying a pass voltage to the... Agent: Myers Bigel Sibley & Sajovec
20100214841 - Memory apparatus and method thereof for operating memory: A memory apparatus and a method thereof for operating a memory are provided herein. The apparatus has the memory and a controller. The memory has a plurality of memory cells, and each the memory cells has a first side and the second side. Each of the first side and the... Agent: J C Patents
20100214844 - Memory system and programming method thereof: Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming... Agent: Harness, Dickey & Pierce, P.L.C
20100214845 - Nand memory cell array, nand flash memory having nand memory cell array, data processing method for nand flash memory: A NAND memory cell array which can be programmed in a hot carrier injection scheme, a NAND flash memory having the NAND memory cell array, and a data processing method for the NAND flash memory are provided. The NAND memory cell array includes one select transistor and at least two... Agent: Jae Y. Park
20100214843 - Nonvolatile memory device and memory system having the same: A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the... Agent: F. Chau & Associates, LLC
20100214842 - Nonvolatile semiconductor memory including charge accumulation layer and control gate: A nonvolatile semiconductor memory includes a transistor, a first MOS, a second MOS, a first voltage circuit, and a second voltage circuit. The transistor includes a accumulation layer, a control gate, and a first impurity diffused layer. The first MOS includes a first electrode and a second layer. The second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214847 - Semiconductor storage device and read voltage correction method: A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214836 - Semiconductor storage apparatus: A semiconductor storage apparatus has a control circuit. The control circuit deactivates the first and second amplifier circuits, turns off the first, second, fourth and fifth switch circuits, and turns on the third and sixth switch circuits in response to an external signal based on reduction of current dissipation of... Agent: Posz Law Group, PLC
20100214848 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a first node, a current source configured to have a current value determined according to a voltage supplied to the first node, and a memory cell string coupled to the first node, the memory cell string including at least one memory cell. Whether a memory... Agent: Ip & T Law Firm PLC
20100214849 - Page buffer circuit of nonvolatile memory device and method of operating the same: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation... Agent: Ip & T Law Firm PLC
20100214850 - Semiconductor memory device and method of erasing data therein: A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214851 - System and method for bit-line control: In one embodiment, a bit-line driver is disclosed. The driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal... Agent: Slater & Matsil LLP
20100214852 - Semiconductor memory device which stores plural data in a cell: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100214853 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare... Agent: Ip & T Law Firm PLC
20100214854 - Shift register providing glitch free operation in power saving mode: Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller. The drive operation controller includes; a first logic gate configured to receive and logically combine selected outputs from selected ones of the... Agent: Volentine & Whitt PLLC
20100214855 - Methods of quantizing signals using variable reference signals: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may... Agent: Fletcher Yoder (micron Technology, Inc.)
20100214856 - Method to improve the write speed for memory products: A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write... Agent: Saile Ackerman LLC
20100214857 - Memory circuits, systems, and method of interleaving accesses thereof: An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block... Agent: Lowe Hauptman Ham & Berner, LLP
20100214858 - Delay locked loop circuit for preventing failure of coarse locking: A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a... Agent: Harness, Dickey & Pierce, P.L.C
20100214859 - Implementing boosted wordline voltage in memories: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100214860 - Sense amplifier scheme for low voltage sram and register files: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise... Agent: Lowe Hauptman Ham & Berner, LLP
20100214861 - Semiconductor memory cell array and semiconductor memory device having the same: A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are... Agent: Lee & Morse, P.C.
20100214862 - Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same: A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a... Agent: Myers Bigel Sibley & Sajovec
20100214863 - Memory power gating circuit and methods: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal... Agent: Lowe Hauptman Ham & Berner, LLP
20100214864 - Memory device command decoding system and memory device and processor-based system using same: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100214865 - Semiconductor memory apparatus and method of controlling the same: A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate... Agent: Echelon Law Group, PC
20100214866 - Semiconductor memory device with reduced power noise: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured... Agent: F. Chau & Associates, LLC08/19/2010 > patent applications in patent subcategories.
20100208503 - Three-dimensional semiconductor structure and method of fabricating the same: A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100208504 - Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices: In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure... Agent: Mills & Onello LLP
20100208505 - Anti-cross-talk circuitry for rom arrays: A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic... Agent: Schwegman, Lundberg & Woessner / Atmel
20100208506 - Read only memory and method of reading same: A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects... Agent: Onda Techno Intl. Patent Attys.
20100208507 - Luminescence device and method of manufacturing the same: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer.... Agent: Hosoon Lee
20100208511 - Memory devices and wireless devices including the same: A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and... Agent: Myers Bigel Sibley & Sajovec
20100208508 - Multi-level nonvolatile memory devices using variable resistive elements: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the... Agent: Harness, Dickey & Pierce, P.L.C
20100208509 - Nonvolatile semiconductor memory device, and production method thereof: A nonvolatile semiconductor memory device according to the present invention includes a memory cell array layer including a first line; a plurality of second and third lines that are formed below or above the first line and cross each other; and a plurality of memory cells arranged at each intersection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100208510 - Semiconductor memory device and method of operating the same: A semiconductor memory device comprises: a memory cell array having memory cells disposed at a crossing-point of a plurality of first lines and a plurality of second lines; and a control circuit configured to apply a first voltage to selected one of the first lines, and to apply a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100208512 - Semiconductor memory device provided with resistance change element: A latch circuit is connected to a first common node, a first, second output node, and a first, second connection node. A first resistance change element is connected to the first connection node, and a second common node. A second resistance change element is connected to the second connection node,... Agent: Knobbe Martens Olson & Bear LLP
20100208513 - Memory with separate read and write paths: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is... Agent: Campbell Nelson Whipps, LLC
20100208516 - Active strap magnetic random access memory cells: A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of... Agent: Pearne & Gordon LLP
20100208514 - Magnetic memory cell and method of fabricating same: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array... Agent: Hahn And Moodley, LLP
20100208515 - Magnetic random access memory: The spin torque transfer magnetic random access memory includes a magnetic tunnel junction element including a pinned layer, a free layer, and a tunnel insulating film formed between the pinned layer and the free layer, and a memory cell select transistor having one diffused region electrically connected to a side... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100208517 - Pin diode device and architecture: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the... Agent: Flh/spansion C/o Frommer Lawrence & Haug
20100208518 - Mis-transistor-based nonvolatile memory circuit with stable and enhanced performance: A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second... Agent: Ipusa, P.l.l.c
20100208519 - Semiconductor memory device and method of reading the same: Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100208520 - Array and control method for flash based fpga cell: A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the... Agent: Lewis And Roca LLP
20100208521 - Nonvolatile memory device, method of operating nonvolatile memory device and memory system including nonvolatile memory device: The method of operating the nonvolatile memory device may include performing a read operation on a first address region, comparing a read time of the first address region with a reference time, and storing read data from the read from the first address region in a second address region based... Agent: Harness, Dickey & Pierce, P.L.C
20100208522 - Memory device and reading method thereof: A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional... Agent: Masao Yoshimura, Chen Yoshimura LLP
20100208523 - Dynamic soft program trims: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory... Agent: Robert A. Manware Fletcher Yoder
20100208524 - Soft landing for desired program threshold voltage: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.... Agent: Leffert Jay & Polglaze, P.A.
20100208525 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a sense amplifier, first and second bit lines that are connected to the sense amplifier, a first memory cell column that is connected to the first bit line, the first memory cell column being formed by a plurality of MONOS type transistors, a first... Agent: Foley And Lardner LLP Suite 500
20100208526 - Non-volatile memory device and method of operation therefor: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is... Agent: Harness, Dickey & Pierce, P.L.C
20100208527 - Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time,... Agent: Turocy & Watson, LLP
20100208530 - Two bits per cell non-volatile memory architecture: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical... Agent: Lng/mosys Joint Customer C/o Luedeka, Neely & Graham, P.C.
20100208528 - Semiconductor device having nonvolatile memory element and data processing system including the same: A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content... Agent: Morrison & Foerster LLP
20100208529 - Memory with reduced power supply voltage for a write operation: A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for... Agent: Freescale Semiconductor, Inc. Law Department
20100208531 - Data reading circuit: There is provided a data reading circuit which is low in current consumption. In a read period, a signal (φ2) is low, and hence an NMOS transistor (14) turns off. Accordingly, no current flows in the NMOS transistor (14). Further, data (D2) is high, and hence an output voltage of... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.
20100208532 - Memory circuit: Provided is a memory circuit including: memory cells (A) arranged in columns and rows; memory cells (B) each provided for each of the rows for storing information indicative of whether writing into the memory cells (A) of the each of the rows has been completed or not; and a circuit... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.
20100208533 - Systems and methods for issuing address and data signals to a memory array: Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100208534 - Semiconductor memory device, memory module including the same, and data processing system: To provide a semiconductor device including a skew detecting circuit activated in a write leveling mode, and an ODT control circuit that activates a terminating resistance circuit connected to a data strobe terminal by using an ODT signal. The ODT control circuit selects a first resistance mode when a dynamic... Agent: Sughrue Mion, PLLC
20100208535 - Semiconductor memory device, memory module including the same, and data processing system: To provide a semiconductor device including a skew detecting circuit activated in a write leveling mode, and an ODT control circuit that activates a terminating resistance circuit connected to a data strobe terminal by using an ODT signal. The ODT control circuit includes counters that delay the ODT signal, activates... Agent: Sughrue Mion, PLLC
20100208537 - Dynamic random access memory (dram) refresh: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more... Agent: Freescale Semiconductor, Inc. Law Department
20100208536 - Structure and methods for measuring margins in an sram bit: Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array... Agent: Texas Instruments Incorporated
20100208538 - Sensing circuit for semiconductor memory: A sensing circuit for a semiconductor memory includes a multiplexer coupled to a bit line and a data line coupling the multiplexer to a sense amplifier. The data line is configured to be precharged to a voltage level higher than a precharge voltage level of the bit line.... Agent: Onda Techno Intl. Patent Attys.
20100208539 - Voltage regulator for memory: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference... Agent: Schwegman, Lundberg & Woessner / Atmel
20100208540 - Integrated circuit with multiported memory supercell and data path switching circuitry: An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups. Each... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20100208541 - Cache memory: Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a... Agent: Robert Plotkin, PC
20100208542 - Clock divider and clock dividing method for a dll circuit: A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller for receiving an output signal of... Agent: Ladas & Parry LLP08/12/2010 > patent applications in patent subcategories.
20100202178 - Offset removal circuit, associative memory including the same, and offset voltage removal method: An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal... Agent: Foley & Lardner LLP
20100202179 - Memory device: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy... Agent: J C Patents
20100202180 - Memory module cutting off dm pad leakage current: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground... Agent: Volentine & Whitt PLLC
20100202182 - Memory devices, systems and methods using multiple 1/n page arrays and multiple write/read circuits: A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays.... Agent: Myers Bigel Sibley & Sajovec
20100202181 - Semiconductor memory device: A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100202183 - High reliability otp memory: A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100202184 - One-time programmable fuse with ultra low programming current: A method of operating a FinFET fuse includes providing the FinFET fuse including a drain, a gate, a source, and a channel between the drain and the source; and applying a program voltage to one of the source and the drain of the FinFET fuse to cause a punch-through in... Agent: Slater & Matsil, L.L.P.
20100202187 - Data read/ write device: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100202188 - Low read current architecture for memory: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.... Agent: Unity Semiconductor Corporation
20100202185 - Nonvolatile memory device and method of writing data to nonvolatile memory device: A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric... Agent: Mcdermott Will & Emery LLP
20100202186 - Semiconductor memory device, method of manufacturing the same, and method of screening the same: A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100202190 - Compact and highly efficient dram cell: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a... Agent: Mcandrews Held & Malloy, Ltd
20100202189 - Semiconductor memory device having a discharge path generator for global i/o lines: A data path circuit includes a bit line sense amplifier, a local input/output line precharger connected to a local input/output line pair, a global input/output line precharger connected to a global input/output line pair, a column selector connecting a bit line pair connected to the bit line sense amplifier and... Agent: F. Chau & Associates, LLC
20100202191 - Nvsram having variable magnetic resistors: Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.... Agent: Campbell Nelson Whipps, LLC
20100202192 - Static memory devices: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100202194 - Dynamically allocable regions in non-volatile memories: An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the... Agent: Graybeal Jackson LLP
20100202193 - Non-volatile memory device: A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100202195 - Phase change memory: The present disclosure includes devices and methods for operating resistance variable memory cells. One or more embodiments include applying a programming signal to a resistance variable material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of... Agent: Brooks, Cameron & Huebsch , PLLC
20100202196 - Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method: A nonvolatile memory device includes a read margin critical value calculation unit configured to calculate a critical value of a read margin between a read voltage and a threshold voltage of a specific cell, an interference value calculation unit configured to calculate an interference value affecting the threshold voltage of... Agent: Ip & T Law Firm PLC
20100202197 - Operation methods of nonvolatile memory device: An operation method includes performing a first program operation and a first program verification operation on an even page memory cell group wherein the first program operation is performed such that the even page memory cell group is programmed to have a threshold voltage less than a target threshold voltage,... Agent: Ip & T Law Firm PLC
20100202200 - Power line compensation for flash memory sense amplifiers: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can... Agent: Dla Piper LLP (us )
20100202198 - Semiconductor memory device and data processing method thereof: Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code... Agent: Harness, Dickey & Pierce, P.L.C
20100202199 - Tracking cells for a memory system: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust... Agent: Vierra Magen/sandisk Corporation
20100202201 - Memory array with inverted data-line pairs: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is... Agent: Leffert Jay & Polglaze, P.A.
20100202202 - Adjusting for charge loss in a memory: Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of charge leakage from the analog storage... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20100202203 - Data restoration method for a non-volatile memory: A method and apparatus for selectively restoring data in a non-volatile memory array based on failure type. Weakened data and erroneous data are identified by performing two readings of a specific memory section. Alternatively, an error correction code is used after a first reading of data to identify erroneous data.... Agent: Mosys Incorporated Patent Counsel
20100202204 - Page-buffer and non-volatile semiconductor memory including page buffer: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device... Agent: Volentine & Whitt PLLC
20100202205 - Semiconductor device: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first... Agent: Miles & Stockbridge PC
20100202207 - All-bit-line erase verify and soft program verify: Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with... Agent: Vierra Magen/sandisk Corporation
20100202206 - Non-volatile memory devices including vertical nand channels and methods of forming the same: A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.... Agent: Myers Bigel Sibley & Sajovec
20100202209 - Flash memory device and program method thereof: A flash memory device includes a memory cell array on which data is stored, and page buffers that are connected to the memory cells through the bit lines and apply one of the first voltage, second voltage or third voltage between the first and second voltage, to the respective bit... Agent: Townsend And Townsend And Crew, LLP
20100202210 - Reducing effects of program disturb in a memory device: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage... Agent: Leffert Jay & Polglaze, P.A.
20100202208 - Semiconductor device including contact plug having an elliptical sectional shape: A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conductivity are formed on the semiconductor substrate. The first contact... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100202211 - Nonvolatile memory device and method for programming the same: Provided are a nonvolatile memory device and a method for programming the same. The method for programming the nonvolatile memory device includes programming at least one memory cell of the nonvolatile memory device by repeating program loops. A first self-boosting method is applied to at least one of the program... Agent: Volentine & Whitt PLLC
20100202213 - Current-mode sense amplifying method: A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100202212 - Non-volatile memory with power-saving multi-pass sensing: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100202214 - Verifying an erase threshold in a memory device: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well... Agent: Leffert Jay & Polglaze, P. A Attn: Kenneth W. Bolvin
20100202215 - Methods for programming nonvolatile memory devices: Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of... Agent: Myers Bigel Sibley & Sajovec
20100202216 - Non-volatile memory device and system having reduced bit line bias time: A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data... Agent: Volentine & Whitt PLLC
20100202217 - Nand flash memory programming: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices... Agent: Schwegman, Lundberg & Woessner/micron
20100202218 - System and method for level shifter: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the... Agent: Slater & Matsil LLP
20100202219 - Burn-in methods for static random access memories and chips: A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are... Agent: Quintero Law Office, PC
20100202220 - Memory circuits, systems, and methods for providing bit line equalization voltages: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line.... Agent: Lowe Hauptman Ham & Berner, LLP
20100202221 - Method of reading memory cell: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to... Agent: Onda Techno Intl. Patent Attys.
20100202222 - Semiconductor memory device: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first... Agent: Ip & T Law Firm PLC
20100202223 - Memory interface and operation method of it: A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data to a memory through said... Agent: Sughrue Mion, PLLC
20100202224 - Memory with data control: In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC
20100202226 - Bank precharge signal generation circuit: A bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and... Agent: Cooper & Dunham, LLP
20100202225 - Data input circuit technical field: A data input circuit comprises a sensing control unit which delays an internal write command by a predetermined period and generates a sense amplifier enable signal in response to a first clock signal, and a data sensing unit which senses align data and transfers the sensed data to a global... Agent: Cooper & Dunham, LLP
20100202227 - Reference voltage and impedance calibration in a multi-mode interface: A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through... Agent: Pvf -- Rambus, Inc. C/o Park, Vaughan & Fleming, LLP
20100202228 - Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100202230 - Memories with front end precharge: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where... Agent: Schwabe Williamson & Wyatt Pacwest Center, Suite 1900
20100202229 - Method and apparatus for selective dram precharge: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100202231 - Thermally stable reference voltage generator for mram: A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100202232 - Refreshing method: A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each... Agent: J C Patents
20100202233 - Semiconductor storage device and control method of the same: A semiconductor storage device includes a timing allocation unit that sets refresh timing to preferentially perform a refresh operation for maintaining data and data access timing to preferentially perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory... Agent: Young & Thompson
20100202235 - Device and method for state retention power gating: A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of... Agent: Freescale Semiconductor, Inc. Law Department
20100202234 - Power-on management circuit for memory: A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a... Agent: Volpe And Koenig, P.C.
20100202238 - Flash backed dram module including logic for isolating the dram: A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides... Agent: Wilmerhale/boston
20100202237 - Flash backed dram module with a selectable number of flash chips: A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, each of which... Agent: Wilmerhale/boston
20100202236 - Rapid safeguarding of nvs data during power loss event: A method, system, and computer program product for safeguarding nonvolatile storage (NVS) data by a processor in communication with a memory device following a power loss event is provided. A first portion of the NVS data is encrypted using a first buffer module. Subsequently the first portion of the NVS... Agent: Griffiths & Seaton PLLC (ibm)
20100202239 - Staged-backup flash backed dram module: A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss... Agent: Wilmerhale/boston
20100202240 - State of health monitored flash backed dram module: A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary... Agent: Wilmerhale/boston
20100202241 - Word line driving circuit and method: A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit... Agent: F. Chau & Associates, LLC
20100202242 - Semiconductor memory device using bus inversion scheme: A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can... Agent: Blakely Sokoloff Taylor & Zafman LLP08/05/2010 > patent applications in patent subcategories.
20100195363 - Multiple layers of memory implemented as different memory technology: Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory... Agent: Unity Semiconductor Corporation
20100195362 - Non-volatile dual port third dimensional memory: Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the... Agent: Unity Semiconductor Corporation
20100195364 - Semiconductor device: The invention provides a semiconductor device having, in each of stacked chip dies, not only vias the number of which corresponds to the number of signals input to and output from a single chip die but also vias the number of which corresponds to the number of signals input to... Agent: Mcginn Intellectual Property Law Group, PLLC
20100195366 - Reducing leakage current in a memory device: Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a... Agent: Qualcomm Incorporated
20100195365 - Rom array: A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own... Agent: Nixon & Vanderhye P.C.
20100195367 - Nonvolatile memory and writing method thereof, and semiconductor device: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus,... Agent: Fish & Richardson P.C.
20100195368 - F-ram device with current mirror sense amp: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp.... Agent: Texas Instruments Incorporated
20100195369 - Multilayer ferroelectric data storage system with regenerative read: A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that... Agent: Kinney & Lange, P.A.
20100195371 - Memory element and memory device: The capability of retaining a resistance value of a stored state and an erased state is improved in a resistance variation-type memory device. A memory layer 5 including a high-resistance layer 2 and an ion source layer 3 is provided between a lower electrode 1 and an upper electrode 4.... Agent: K&l Gates LLP
20100195370 - Nonvolatile semiconductor memory device and method for performing verify write operation on the same: Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit,... Agent: Rader Fishman & Grauer PLLC
20100195372 - Resistance-changing memory device: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100195373 - Method of operating a memory circuit using memory cells with independent-gate controlled access devices: A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the... Agent: Ryan, Mason & Lewis, LLP
20100195374 - Eight transistor soft error robust storage cell: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes... Agent: Manoj Sachdev
20100195375 - Full cmos sram: A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and... Agent: Stanzione & Kim, LLP
20100195376 - Bit line voltage control in spin transfer torque magnetoresistive random access memory: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit... Agent: Qualcomm Incorporated
20100195378 - Phase change memory with dual word lines and source lines and method of operating same: A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100195377 - Semiconductor memory apparatus and method of testing the same: A semiconductor memory apparatus includes a sense amplifier coupled to a plurality of bit lines, a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal, a mode selecting unit configured to selectively couple the first node... Agent: Ladas & Parry LLP
20100195380 - Non-volatile memory cell with precessional switching: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100195381 - Switchable element: A switchable element. The element includes a source electrode, a drain electrode, a conducting channel between the source electrode and the drain electrode, and a gate with multiferroic material being switchable, by application of an electrical signal to the gate, between a first switching state with a first spontaneous polarization... Agent: Ibm Corporation, T.j. Watson Research Center
20100195379 - System and method of pulse generation: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes... Agent: Qualcomm Incorporated
20100195382 - Thin film magnetic memory device capable of conducting stable data read and write operations: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic... Agent: Mcdermott Will & Emery LLP
20100195383 - Isolated p-well architecture for a memory device: A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read,... Agent: Cool Patent, P.C. C/o Cpa Global
20100195384 - System and method to read data subject to a disturb condition: Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory. The characteristics correspond to a plurality of values including a first value stored at a particular cell and a second value stored at a second... Agent: Toler Law Group
20100195389 - Flash memory device and methods programming/reading flash memory device: Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory... Agent: Volentine & Whitt PLLC
20100195390 - Memory device with negative thresholds: A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read... Agent: D. Kligler I.p. Services Ltd
20100195385 - Method of programming nonvolatile memory device: A method of sequentially performing a LSB program operation and an MSB program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled with the memory... Agent: Ip & T Law Firm PLC
20100195388 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1)th logical pages stored... Agent: Ip & T Law Firm PLC
20100195387 - Non-volatile memory device and ispp programming method: A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation... Agent: Volentine & Whitt PLLC
20100195386 - Page buffer circuit and nonvolatile memory device: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line... Agent: Ip & T Law Firm PLC
20100195391 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100195392 - Capacitor structure having improved area efficiency, a memory device including the same, and a method of forming the same: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices.... Agent: Trask Britt, P.C./ Micron Technology
20100195393 - Data storage system with refresh in place: A data storage system for refreshing in place data stored in a non-volatile re-writeable memory is disclosed. Data from a location memory can be read into a temporary storage location; the data at the memory location can be erased; the read data error corrected if necessary; and then the read... Agent: Unity Semiconductor Corporation
20100195394 - Nonvolatile memory device: A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of cells to be programmed, and a 1-bit... Agent: Ip & T Law Firm PLC
20100195398 - Applying different body bias to different substrate portions for non-volatile storage: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or... Agent: Vierra Magen/sandisk Corporation
20100195397 - Controlled boosting in non-volatile memory soft programming: A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The... Agent: Vierra Magen/sandisk Corporation
20100195395 - Non-volatile memory device having vertical structure and method of operating the same: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality... Agent: Mills & Onello LLP
20100195396 - Semiconductor memory device and self-test method of the same: A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the buffer unit includes a volatile memory, a self-test interface includes a data input/output pin, and a controller which controls... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100195399 - Memory segment accessing in a memory device: Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are read at substantially the same time by coupling a selected memory segment, and at some of the data lines of any intervening segments, to... Agent: Leffert Jay & Polglaze, P.A.
20100195401 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on... Agent: Ip & T Law Firm PLC
20100195400 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells... Agent: Ip & T Law Firm PLC
20100195402 - Page buffer circuit: A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second... Agent: Ip & T Law Firm PLC
20100195403 - Erase verify in memory devices: In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a sample are not erased, either directly or indirectly. The number of unerased cells in the sample can be compared to a threshold. An erase operation... Agent: Leffert Jay & Polglaze, P.A.
20100195404 - Method and apparatus for management of over-erasure in nand-based nor-type flash memory: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array... Agent: Saile Ackerman LLC
20100195405 - Segmented bitscan for verification of programming: A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether... Agent: Vierra Magen/sandisk Corporation
20100195406 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read... Agent: Ip & T Law Firm PLC
20100195407 - Read operation method of memory device: A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell during a... Agent: Volentine & Whitt PLLC
20100195409 - Fuse elemetns based on two-terminal re-writeable non-volatile memory: A margin restore fuse element is described, including a latch configured to store data, a first memory element coupled to the latch and configured to store a first resistive value, a second memory element coupled to the latch and configured to store a second resistive value, a restore circuit coupled... Agent: Unity Semiconductor Corporation
20100195408 - Non-body contacted sense amplifier with negligible history effect: In a method of mitigating hysteresis effect in a sense amplifier circuit, a data value is sensed from a data source with the sense amplifier during a first period. The data value is stored in a latch. The data valued stored in the latch is inverted, thereby generating an inverted... Agent: Ibm Corporation
20100195412 - Semiconductor device, method for controlling the same, and semiconductor system: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh... Agent: Sughrue Mion, PLLC
20100195413 - Semiconductor memory device: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that... Agent: Sughrue Mion, PLLC
20100195411 - Semiconductor memory device and fail bit detection method in semiconductor memory device: A memory cell array includes a plurality of pages. Each page of the plurality of pages is divided into a plurality of segments, and one segment is constituted of a plurality of bytes. A fail detection circuit receives signals of the plurality of fail bit detection signal lines, and the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100195410 - Semiconductor memory device having shift registers: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100195414 - Level detector, internal voltage generator including level detector, and semiconductor memory device including internal voltage generator: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and... Agent: F. Chau & Associates, LLC
20100195415 - Semiconductor memory device and reading method therefor: A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100195416 - Anti-fuse circuit and semiconductor memory device: An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100195417 - Semiconductor device, circuit of controlling signal lines and method of controlling signal lines: A semiconductor device includes first and second lines, and a switch between the first and second lines. The switch temporary and electrically connects the first and second lines to each other, when the first signal line is transitioned from a first level to a second level while the second signal... Agent: Sughrue Mion, PLLC
20100195418 - Semiconductor memory device and system: Provided is a semiconductor memory device. The semiconductor memory device includes first and second memory chips and a control logic configured to execute an interleave program between the first and second memory chips. The control logic receives write data to be written into first and second memory blocks of the... Agent: Volentine & Whitt PLLC
20100195419 - Configurable write policy in a memory system: A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used.... Agent: Connolly Bove Lodge & Hutz LLP
20100195420 - Semiconductor memory device and system: A semiconductor memory system includes a memory controller and a memory. The memory controller includes a control signal converting unit converting a control signal into a converted control signal including n sequential clock pulses and a target clock pulse activated after a time period has elapsed from a start point... Agent: F. Chau & Associates, LLC
20100195421 - Stacked-die memory systems and methods for training stacked-die memory systems: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to... Agent: Schwegman, Lundberg & Woessner/micron
20100195423 - Semiconductor device and operating method thereof: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100195422 - Semiconductor integrated circuit and method for controlling the same: A semiconductor integrated circuit includes: a current difference sense type of a sense amplifier including: an input line connected to memory cells as a target to be read, a reference line connected to reference cells, and a first pre-charge circuit configured to pre-charge the input line and the reference line;... Agent: Turocy & Watson, LLP
20100195425 - Semiconductor device, semiconductor package and memory repair method: A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being... Agent: SprinkleIPLaw Group
20100195424 - Semiconductor memory device: In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main... Agent: Mcdermott Will & Emery LLP
20100195426 - Semiconductor memory device and method of testing the same: A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the... Agent: Mcginn Intellectual Property Law Group, PLLC
20100195427 - 1-transistor type dram cell, dram device and dram comprising thereof and driving method thereof and manufacturing method thereof: The present invention relates to a semiconductor device, and more precisely to an 1-transisotr type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data... Agent: Ladas & Parry LLP
20100195428 - Semiconductor device: A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts... Agent: Morrison & Foerster LLP
20100195429 - Semiconductor memory device: A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates... Agent: Foley And Lardner LLP Suite 500
20100195430 - Method and apparatus for managing behavior of memory devices: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed... Agent: Dickstein Shapiro LLP
20100195431 - Semiconductor memory device and manufacturing method of semiconductor memory device: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors... Agent: Young & ThompsonPrevious industry: Electric power conversion systems
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