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Static information storage and retrieval July category listing 07/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
07/29/2010 > patent applications in patent subcategories. category listing

20100188878 - Semiconductor device that supresses malfunctions due to voltage reduction: A semiconductor device includes a first pad that supplies power to sense amplifiers, a second pad that supplies power to a first circuit connected to the sense amplifiers, a third pad that receives a signal input or outputs a signal at a frequency equal to or higher than a first... Agent: Sughrue Mion, PLLC

20100188877 - Storage device: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC

20100188879 - Cross-point semiconductor memory device and method of manufacturing the same: A cross-point semiconductor memory device includes: a plurality of first wirings extending in a first direction; a plurality of second wirings positioned on a layer different from the first wirings to extend in a second direction different from the first direction; and memory parts provided in overlap areas of the... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20100188880 - Power switching for portable applications: A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The... Agent: Kenyon & Kenyon LLP

20100188881 - Method and device for correcting and obtaining reference voltage: The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an... Agent: Baker & Hostetler LLP

20100188882 - Nonvolatile ferroelectric memory and control device using the same: A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged... Agent: Townsend And Townsend And Crew, LLP

20100188884 - Nonvolatile memory element, nonvolatile memory apparatus, and method of writing data to nonvolatile memory element: A nonvolatile memory element comprises a first electrode (503), a second electrode (505), and a resistance variable layer (504) disposed between the first electrode and the second electrode, a resistance value between the first electrode and the second electrode being switchable reversibly in response to positive and negative electric signals... Agent: Mcdermott Will & Emery LLP

20100188885 - Resistance change memory device and programming method thereof: A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100188883 - Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array: Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100188886 - Implementing enhanced sram stability and enhanced chip yield with configurable wordline voltage levels: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A... Agent: Ibm Corporation RochesterIPLaw Dept 917

20100188887 - Semiconductor integrated circuit device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit... Agent: Stanley P. Fisher Reed Smith LLP

20100188889 - Back gated sram cell: Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The... Agent: Brooks, Cameron & Huebsch , PLLC

20100188888 - Implementing enhanced dual mode sram performance screen ring oscillator: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the... Agent: Ibm Corporation RochesterIPLaw Dept 917

20100188890 - Magnetoresistance effect element and magnetic random access memory: A magnetoresistance effect element includes: a magnetization free layer; a spacer layer provided adjacent to the magnetization free layer; a first magnetization fixed layer provided adjacent to the spacer layer on a side opposite to the magnetization free layer; and at least two second magnetization fixed layers provided adjacent to... Agent: Mr. Jackson Chen

20100188891 - Semiconductor device: The semiconductor device has: a first magnetoresistance element; a second magnetoresistance element. The first and second magnetoresistance elements each includes a free layer which can be changed in spin orientation therein and a pinned layer which is fixed in spin orientation therein. The first magnetoresistance element is coupled to a... Agent: Miles & Stockbridge PC

20100188892 - Electric device comprising phase change material and heating element: An electric device has a resistor including a phase change material changeable between a first phase and a second phase within a switching zone. The resistor has a first resistance when the phase change material is in the first phase and a different second resistance, when the phase change material... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100188893 - Heat assisted switching and separated read-write mram: A MRAM structure is described that has a dedicated data storage layer formed between first and second electrodes and a dedicated data sensing layer between second and third electrodes to enable separate read and write functions. A diode between the storage layer and first electrode allows a heating current to... Agent: Saile Ackerman LLC

20100188894 - In-situ resistance measurement for magnetic random access memory (mram): A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined.... Agent: Qualcomm Incorporated

20100188895 - Staggered stram cell: Spin-transfer torque memory having a free magnetic layer having a thickness extending in a out-of-plane direction and extending in a lateral direction in an in-plane direction between a first end portion and an opposing second end portion. A tunneling barrier separates a reference magnetic layer from the first end portion... Agent: Campbell Nelson Whipps, LLC

20100188897 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation

20100188898 - Reducing effects of program disturb in a memory device: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well... Agent: Leffert Jay & Polglaze, P.A.

20100188899 - Nonvolatile analog memory: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor. a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current... Agent: Jianq Chyun Intellectual Property Office

20100188900 - Array and pitch of non-volatile memory cells: An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation,... Agent: Dla Piper LLP (us )

20100188901 - Three-terminal single poly nmos non-volatile memory cell: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20100188896 - Nonvolatile semiconductor memory and method for detecting leakage defects of the same: There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode is selected, thus... Agent: Taft, Stettinius & Hollister LLP

20100188902 - Differential, level-shifted eeprom structures: Memory embodiments are provided to operate in memory systems which are configured to have a system ground and a system substrate that are biased at different voltages. At least one of these embodiments includes a memory cell and write and read circuits in which the memory cell is coupled to... Agent: Koppel, Patrick, Heybl & Dawson

20100188904 - Memory voltage cycle adjustment: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an... Agent: Brooks, Cameron & Huebsch , PLLC

20100188903 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes performing a first program operation and a first verification operation on memory cells until a cell, having a threshold voltage higher than a first reference voltage, occurs and, when a cell having the threshold voltage higher than the first reference voltage... Agent: Ip & T Law Firm PLC

20100188905 - Spin device: According to an embodiment of the present invention, a spin device includes an intermediate semiconductor region arranged between a first terminal and a second terminal, wherein the first terminal is adapted to provide a current having a first degree of spin polarization to the intermediate semiconductor region, and wherein the... Agent: Slater & Matsil LLP

20100188908 - Setting memory device vref in a memory controller and memory device interface in a communication bus: A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device... Agent: Ibm-rochester C/o Toler Law Group

20100188907 - Semiconductor device, control method for semiconductor device, and electronic device: A semiconductor device including a first switch coupled to a first power supply line, a second switch coupled to the first switch and to a second power supply line, and a storage part provided in a path which is between the second power supply line and the first switch, and... Agent: Fujitsu Patent Center Fujitsu Management Services Of America, Inc.

20100188906 - Strobe apparatus, systems, and methods: A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron

20100188909 - Memory having negative voltage write assist circuit and method therefor: A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that... Agent: Freescale Semiconductor, Inc. Law Department

20100188910 - Clock synchronization in a memory system: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal... Agent: Rambus Lerner, David, Et Al.

20100188911 - Memory-write timing calibration including generation of multiple delayed timing signals: A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third... Agent: Shemwell / Rambus

20100188912 - Semiconductor memory circuit and control method for reading data: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit... Agent: Staas & Halsey LLP

20100188913 - Semiconductor memory device having sense amplifier: A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100188914 - Self refresh operation of semiconductor memory device: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100188915 - Self refresh operation of semiconductor memory device: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100188919 - Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears... Agent: Ibm-rochester C/o Toler Law Group

20100188920 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100188918 - Setting controller vref in a memory controller and memory device interface in a communication bus: A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The... Agent: Ibm-rochester C/o Toler Law Group

20100188916 - Setting memory controller driver to memory device termination value in a communication bus: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is... Agent: Ibm-rochester C/o Toler Law Group

20100188917 - Setting memory device termination in a memory device and memory controller interface in a communication bus: A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values... Agent: Ibm-rochester C/o Toler Law Group

20100188921 - Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same: Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate insulator to provide a low output impedance despite having a semiconductor channel width that is relatively small. The output transistor is protected from damage by a clamping circuit... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100188922 - Semiconductor storage device and electric apparatus: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in... Agent: Arent Fox LLP

20100188923 - Semiconductor device: A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decoder to the memory cell and a... Agent: Masao Yoshimura, Chen Yoshimura LLP

20100188924 - Data transfer system: The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus... Agent: Morrison & Foerster LLP

  
07/22/2010 > patent applications in patent subcategories. category listing

20100182815 - Content addressable memory: For receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, a content addressable memory is disclosed to include a plurality of content addressable memory units connected in series, each content addressable memory unit being adapted to receive the... Agent: The Weintraub Group, P.L.C

20100182816 - Power saving static-based comparator circuits and methods and content-addressable memory (cam) circuits employing same: Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator... Agent: Qualcomm Incorporated

20100182817 - Memory system, semiconductor memory device, and wiring substrate: A memory system includes a plurality of semiconductor memory devices each including a termination resistance circuit that can be controlled to be turned on or off from an outside by a termination resistance control signal, and a memory controller. The memory controller includes a termination resistance control unit that outputs... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182818 - Non-volatile semiconductor memory device and method of writing data therein: A device includes a memory cell array and a control circuit, the memory cell array inclusing word-lines, bit-lines, and memory cells arranged at the intersections of the word-lines and the bit-lines, each memory cell inclusing an electrically programmable antifuse element. The control circuit may perform, as a first step, applying... Agent: Posz Law Group, PLC

20100182819 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100182821 - Memory device, memory circuit and semiconductor integrated circuit having variable resistance: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between... Agent: Mcdermott Will & Emery LLP

20100182820 - Variable resistance memory device: A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line... Agent: Rader Fishman & Grauer PLLC

20100182822 - Device and method for using dynamic cell plate sensing in a dram memory cell: A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are... Agent: Trask Britt, P.C./ Micron Technology

20100182823 - Low leakage high performance static random access memory cell using dual-technology transistors: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and... Agent: Qualcomm Incorporated

20100182824 - Magnetic random access memory: An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a... Agent: Mr. Jackson Chen

20100182827 - High margin multilevel phase-change memory via pulse width programming: An electronic device and method of programming for binary and multilevel memory operation. The active material of the device is a phase-change material. The method includes utilization of the pulse duration of electrical pulses as a programming variable to program a phase-change device to two or more memory states that... Agent: Kevin L. Bray Ovonyx, Inc.

20100182825 - Programmable resistance memory: A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.... Agent: Ovonyx, Inc

20100182826 - Reduction of drift in phase-change memory via thermally-managed programming: A method of programming a phase-change material. The method includes providing a transformation pulse to the phase-change material, where the transformation pulse includes a programming waveform and a conditioning waveform. The programming waveform provides sufficient energy to alter the structural state of the phase-change material. In one embodiment, the programming... Agent: Kevin L. Bray Ovonyx, Inc.

20100182829 - Semiconductor memory device: To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier is requested while a data write... Agent: Morrison & Foerster LLP

20100182828 - Semiconductor storage device: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and... Agent: Miles & Stockbridge PC

20100182831 - Non-volatile memory and method with reduced neighboring field errors: A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100182832 - Non-volatile multilevel memory cell programming: The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page. One method includes programming a first lower page, programming a second lower page, programming a third lower page, programming an upper page, and... Agent: Brooks, Cameron & Huebsch , PLLC

20100182833 - Memory and boundary searching method thereof: A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution... Agent: J C Patents

20100182835 - Block decoder of flash memory device: A block decoder of a flash memory device includes a discharge control unit configured to output a discharge signal in response to a program precharge signal and one or more of a number of address signals, and a selection line control unit configured to apply a ground voltage to source... Agent: Ip & T Law Firm PLC

20100182836 - Nonvolatile memory having plurality of memory blocks each including data storage area and discrimination area: A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182834 - Twisted data lines to avoid over-erase cell result coupling to normal cell result: Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing... Agent: Stout, Uxa, Buyan & Mullins LLP

20100182838 - Flash memory device with data output control: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the... Agent: Borden Ladner Gervais LLP Anne Kinsman

20100182837 - Magnetic floating gate memory: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.... Agent: Campbell Nelson Whipps, LLC

20100182839 - Method of programming nonvolatile memory device: According to a method of programming a nonvolatile memory device, a program operation is performed on a first page by applying a program pulse to the first page. A verification operation is performed on the program operation by applying a verification voltage to the first page. If the program operation... Agent: Ip & T Law Firm PLC

20100182830 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes an encoder configured to perform a scramble operation on input data, a digital sum value (DSV) generator configured to generate a DSV indicating a difference between a number of data ‘0’ and a number of data ‘1’ in the input data encoded by the encoder,... Agent: Ip & T Law Firm PLC

20100182843 - Current sensing for flash: A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source to provide current to the bit line. The voltage level of the bit line is then set by the current... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.

20100182841 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a data latch unit configured to store data to be programmed into a memory cell or store data read from a memory cell, and page buffers each comprising a sense node discharge unit configured to selectively ground a sense node depending on data stored in... Agent: Ip & T Law Firm PLC

20100182840 - Nonvolatile memory device and program or verification method using the same: A nonvolatile memory device includes a bit line sensing signal supply unit configured to output a bit line sensing signal, having a rising voltage level that rises in discrete steps, in response to a control signal, and a bit line sensing unit configured to selectively connect a bit line and... Agent: Ip & T Law Firm PLC

20100182842 - Sense amplifier and data sensing method thereof: A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100182844 - Operating method used in read or verification method of nonvolatile memory device: In an operating method in a read or verification operation of a nonvolatile memory device, selected bit lines are precharged to a logic high level and, at the same time, unselected bit lines are discharged to a logic low level. The selected and unselected bit lines are connected to respective... Agent: Ip & T Law Firm PLC

20100182845 - Non-volatile memory device and method for copy-back thereof: A method for performing a copy-back operation in a non-volatile memory device includes: measuring and recording a maximum program voltage used to program a part of target data to copy-back when a copy-back command is inputted; and performing a copy-back operation using the recorded maximum program voltage.... Agent: Ip & T Law Firm PLC

20100182846 - Flash memory with two-stage sensing scheme: For the flash memory, two-stage sensing scheme is realized such that a tiny local sense amp is devised in order to insert between memory cells, which minimizes area penalty, wherein the local sense amp is connected to a global sense amp through a global bit line for configuring two-stage sensing... Agent: Juhan Kim

20100182847 - Nonvolatile memory system, semiconductor memory and writing method: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and... Agent: Mattingly & Malur, P.C.

20100182853 - Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word... Agent: Banner & Witcoff, Ltd.

20100182848 - Semiconductor device and data processor: Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the... Agent: Miles & Stockbridge PC

20100182849 - Synchronous semiconductor device and data processing system including the same: A semiconductor device includes first, second and third terminals respectively receiving first, second and third input signals from outside, first, second and third input buffers respectively coupled to the first, second and third terminals, the first, second and third input buffers producing first, second and third buffered signals responsive to... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182850 - Dynamic leakage control for memory arrays: A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20100182852 - Oscillation circuit and semiconductor memory device including the same: An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal... Agent: Myers Bigel Sibley & Sajovec

20100182851 - Refresh control circuit and semiconductor memory device and memory system including the same: A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control signal based on a chip select signal and an external self refresh control signal. The memory cell array is refreshed in response to the internal auto... Agent: Mills & Onello LLP

20100182854 - Operation guarantee system: An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence... Agent: Greenblum & Bernstein, P.L.C

20100182856 - Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device: A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system clock, a synchronous circuit selection circuit that performs switching between... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182855 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A semiconductor memory device and a data transmission system that operate in synchronization with a high speed system clock without using a synchronizing circuit such as a DLL or PLL. A semiconductor memory device that operates in synchronization with a system clock provided from outside, outputs a data strobe signal... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182857 - Tester for semiconductor device and semiconductor device: An apparatus testing a semiconductor device may include, but is not limited to, a first strobe signal generating circuit and a detecting circuit. The first strobe signal generating circuit generates a first strobe signal in response to a reference clock supplied from the semiconductor device. The detecting circuit detects a... Agent: Young & Thompson

20100182858 - Nonvolatile semiconductor memory device and method of programming: A nonvolatile semiconductor memory device includes a memory cell, a precharge control circuit, a power supply circuit, a bit line driver, a word line driver, a first multiplexer, and a second multiplexer. The memory cell includes an anti-fuse storage element and a selection transistor. Before data are written into the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100182859 - Method and apparatus for testing a memory device: Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a... Agent: Ryan, Mason & Lewis, LLP

20100182860 - Semiconductor memory device implementing full-vdd bit line precharge scheme using bit line sense amplifier: A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and... Agent: Mills & Onello LLP

20100182861 - Sense amplifier with a compensating circuit: A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to the drain of the transistor. The output end of... Agent: North America Intellectual Property Corporation

20100182863 - Semiconductor memory device: A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device 1 that has a recording area 30 formed by a... Agent: Sughrue Mion, PLLC

20100182862 - Semiconductor memory device and method of controlling auto-refresh: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.... Agent: Mcginn Intellectual Property Law Group, PLLC

20100182864 - Semiconductor memory device requiring refresh operation: To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that... Agent: Sughrue Mion, PLLC

20100182867 - Internal voltage generating circuit of semiconductor memory device: An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal... Agent: F. Chau & Associates, LLC

20100182865 - Negative-voltage generator with power tracking for improved sram write ability: An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell.... Agent: Slater & Matsil, L.L.P.

20100182866 - Semiconductor memory device for compensating for operating voltage difference between near cell and far cell in consideration of cell position, and memory card and memory system including the same: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into at least two local bit line groups arranged to be alternately connected with at least two global bit lines and coupled... Agent: Sughrue Mion, PLLC

  
07/15/2010 > patent applications in patent subcategories. category listing

20100177544 - Generating rom bit cell arrays: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells... Agent: Nixon & Vanderhye P.C.

20100177545 - Memory circuits and routing of conductive layers thereof: A memory circuit includes at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. The memory circuit includes a first conductive layer, a second conductive layer... Agent: Lowe Hauptman Ham & Berner, LLP

20100177546 - Semiconductor device: A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100177547 - Memory device and memory access method: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20100177548 - Multilevel one-time programmable memory device: A multilevel one-time programmable memory device includes a plurality of memory cells, wherein each of the plurality of memory cells includes: a first electrode to which a first voltage is applied, a second electrode to which a second voltage is applied and a plurality of fuse lines performing a fusing... Agent: F. Chau & Associates, LLC

20100177549 - Silicide-silicon oxide-semiconductor antifuse device and method of making: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20100177550 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an aspect of the invention includes a memory cell array and a power supply circuit. The memory cell array includes memory cells each having an insulating film and being programmed to store information by inflicting an electric stress on the insulating film to break... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100177554 - Bipolar cmos select device for resistive sense memory: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and... Agent: Campbell Nelson Whipps, LLC

20100177551 - Bit set modes for a resistive sense memory cell array: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100177553 - Rewritable memory device: Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100177552 - Table-based reference voltage characterization scheme: Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell.... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100177555 - Variable resistance nonvolatile storage device: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301)... Agent: Wenderoth, Lind & Ponack L.L.P.

20100177556 - Asymmetric static random access memory: An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a... Agent: Quintero Law Office, PC

20100177558 - Mram having variable word line drive potential: An MRAM of a spin transfer type according to the invention is provided with a memory cell 10 and a word driver 30. The memory cell 10 has a magnetic resistance element 1 and a selection transistor TR having one of source/drain electrodes which is connected with one end of... Agent: Young & Thompson

20100177557 - Stt-mram cell structures: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a... Agent: Fletcher Yoder (micron Technology, Inc.)

20100177559 - Method for setting pcram devices: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a bias arrangement to a memory cell to change the resistance state from a higher resistance state to a lower resistance state. The bias arrangement comprises a first voltage pulse and a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100177560 - Non-volatile memory circuit including voltage divider with phase change memory devices: A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset... Agent: Mauriel Kapouytian & Treffert LLP

20100177562 - Computer memory device with multiple interfaces: Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100177561 - Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the... Agent: Fletcher Yoder (micron Technology, Inc.)

20100177563 - Nonvolatile semiconductor memory, method for reading out thereof, and memory card: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100177564 - Method for detecting flash program failures: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value... Agent: Fletcher Yoder (micron Technology, Inc.)

20100177565 - Method of operating a flash memory device: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in... Agent: Townsend And Townsend And Crew, LLP

20100177566 - Non-volatile memory device having stacked structure, and memory card and electronic system including the same: Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND... Agent: Harness, Dickey & Pierce, P.L.C

20100177567 - Nonvolatile semiconductor memory device which can electrically rewrite data and system therefor: A nonvolatile semiconductor memory device includes a memory cell, latch circuits, and an arithmetic operation circuit. The memory cell stores data by a difference in threshold voltage. A read operation is performed twice or more on the memory cell under the same read conditions, and the latch circuits store a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100177568 - Read mode for flash memory: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell... Agent: Harrity & Harrity, LLP

20100177569 - Single poly eeprom allowing continuous adjustment of its threshold voltage: A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read... Agent: Texas Instruments Incorporated

20100177570 - Semiconductor memory device capable of compensating variation with time of program voltage: A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100177571 - Memory bank signal coupling buffer and method: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction,... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100177572 - Semiconductor device capable of adjusting page size: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality... Agent: F. Chau & Associates, LLC

20100177573 - Semiconductor memory device and semiconductor memory device driving method: A memory includes a latch circuit latching data from a first and a second bit lines to a first and a second sense nodes; a first data line reading-out the data from the first sense node to an outside; a second data line reading-out the data from the second sense... Agent: Knobbe Martens Olson & Bear LLP

20100177574 - System and method for mitigating reverse bias leakage: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of... Agent: Brooks, Cameron & Huebsch , PLLC

20100177575 - Apparatus and method for controlling write access to a group of storage elements: An apparatus and method for controlling write access to a group of storage elements is provided. Each storage element within the group is identified by an n-bit address, and the total number of storage elements in the group is less than 2n. Write enable circuitry is responsive to an access... Agent: Nixon & Vanderhye P.C.

20100177576 - Semiconductor memory device: A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense... Agent: F. Chau & Associates, LLC

20100177577 - Signal transfer apparatus and methods: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes... Agent: Schwegman, Lundberg & Woessner/micron

20100177578 - Tri-state driver circuits having automatic high-impedance enabling: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100177579 - Semiconductor memory device having faulty cells: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100177580 - Semiconductor integrated circuit device and operating method thereof: Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access... Agent: Miles & Stockbridge PC

20100177582 - Semiconductor memory device: A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the... Agent: F. Chau & Associates, LLC

20100177581 - Very small swing high performance asynchronous cmos static memory (multi-port register file) with power reducing column multiplexing scheme: The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements... Agent: Mcandrews Held & Malloy, Ltd

20100177583 - Semiconductor memory device, memory system including memory controller, and refresh control method for a semiconductor memory device: A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to... Agent: Sughrue Mion, PLLC

20100177584 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality of banks are disposed such that a sum... Agent: Sughrue Mion, PLLC

20100177585 - Memory subsystem: Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by,... Agent: North Weber & Baugh LLP

20100177586 - Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines: Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a... Agent: Brake Hughes Bellermann LLP C/o Cpa Global

20100177587 - Circuit and method for controlling dram column-command address: The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output... Agent: Volpe And Koenig, P.C.

20100177588 - Calibration circuit and calibration method: A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers... Agent: Morrison & Foerster LLP

20100177589 - Semiconductor device having latency counter: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based... Agent: Sughrue Mion, PLLC

20100177590 - Burst mode control circuit: A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period... Agent: Cooper & Dunham, LLP

  
07/08/2010 > patent applications in patent subcategories. category listing

20100172169 - Magnetic structures, information storage devices including magnetic structures, methods of manufacturing and methods of operating the same: A magnetic structure includes a first portion and a plurality of second portions. The first portion extends in a first direction. The plurality of second portions extend from ends of the first portion in a second direction. The first and second directions are perpendicular to one another. Two magnetic domains... Agent: Harness, Dickey & Pierce, P.L.C

20100172171 - Resistance variable memory apparatus: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a... Agent: Mcdermott Will & Emery LLP

20100172172 - Semiconductor device, semiconductor system including the same, and voltage supply method of semiconductor device: A semiconductor device, a semiconductor system including the same, and a voltage supply method of the semiconductor device are provided. The semiconductor device includes at least two semiconductor memory devices and a voltage supply controller configured to selectively supply a voltage to each of the at least two semiconductor memory... Agent: Sughrue Mion, PLLC

20100172170 - Variable resistive element, manufacturing method for same, and non-volatile semiconductor memory device: Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first... Agent: Nixon & Vanderhye, PC

20100172173 - System and method to read and write data a magnetic tunnel junction element: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.... Agent: Qualcomm Incorporated

20100172174 - Semiconductor device having architecture for reducing area and semiconductor system including the same: A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially... Agent: Sughrue Mion, PLLC

20100172175 - Memory device and method having charge level assignments selected to minimize signal coupling: A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100172177 - Memory device having sub-bit lines and memory system: A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array... Agent: Volentine & Whitt PLLC

20100172178 - Semiconductor device manufacturing method and semiconductor integrated circuit device: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20100172176 - Semiconductor device, a method of using a semiconductor device, a programmable memory device, and method of producing a semiconductor device: A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel... Agent: Slater & Matsil LLP

20100172179 - Spare block management of non-volatile memories: Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into two sections (for example a binary section and a multi-state section), where blocks of one section are more prone to... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100172180 - Non-volatile memory and method with write cache partitioning: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100172181 - Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method: Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14v-1 including a bit line selector... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100172182 - Nonvolatile memory device and method for operating the same: Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells... Agent: Harness, Dickey & Pierce, P.L.C

20100172184 - Asymmetric single poly nmos non-volatile memory cell: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20100172183 - Method and apparatus to suppress fringing field interference of charge trapping nand memory: With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100172185 - Method for operating a flash memory device: A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a... Agent: Marshall, Gerstein & Borun LLP

20100172186 - Programming and/or erasing a memory device in response to its program and/or erase history: For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20100172187 - Robust sensing circuit and method: A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first... Agent: Vierra Magen/sandisk Corporation

20100172188 - Method for conducting over-erase correction: A method for conducting an over-erase correction comprises the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a... Agent: Wpat, PC Intellectual Property Attorneys

20100172189 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100172194 - Dual-threshold-voltage two-port sub-threshold sram cell apparatus: The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for... Agent: Bacon & Thomas, PLLC

20100172191 - Voltage regulation method and memory applying thereof: A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100172192 - Reference voltage generation circuit and semiconductor memory: A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each... Agent: Knobbe Martens Olson & Bear LLP

20100172193 - Semiconductor memory device and method of reducing consumption of standby current therein: A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to... Agent: Lee & Morse, P.C.

20100172195 - Ultra-low-power variation-tolerant radiation-hardened cache design: A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by precharging the control section to a virtual drain voltage.... Agent: Gates & Cooper LLP Howard Hughes Center

20100172190 - Processor arrays made of standard memory cells: Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells,... Agent: Daniel J Swirsky

20100172196 - Circuit for generating data strobe signal in ddr memory device and method therefor: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input... Agent: Marshall, Gerstein & Borun LLP

20100172197 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure

20100172198 - Data storage element sensing device: A sensing device for a data storage system may include a sensing circuit, a pull-down circuit, and a pull-up circuit. The sensing circuit may sense discharging of a desired bit line or a complementary bit line and may generate a desired output. The pull-down circuit may be coupled to the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20100172199 - Balanced sense amplifier for single ended bitline memory architecture: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding... Agent: Docket Clerk

20100172200 - Memory device, memory controller and memory system: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a... Agent: Arent Fox LLP

20100172201 - Semiconductor device having plurality of operation modes: A semiconductor device includes: a first level detecting circuit for detecting a voltage level at a control terminal after a prescribed time period from when a power supply voltage is supplied to a power supply terminal, a control unit for selecting in which operation mode among a plurality of operation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

  
07/01/2010 > patent applications in patent subcategories. category listing

20100165689 - Rejuvenation of analog memory cells: A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the... Agent: D. Kligler I.p. Services Ltd

20100165690 - Segmented ternary content addressable memory search architecture: A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored... Agent: Texas Instruments Incorporated

20100165691 - Content addressable memory: s

20100165693 - Semiconductor memory device having open bit line structure: A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending... Agent: Mcdermott Will & Emery LLP

20100165692 - Variable memory refresh devices and methods: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D... Agent: Schwegman, Lundberg & Woessner/micron

20100165694 - Memory cell array: Disclosed is a memory cell array including: word lines and first and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and a switching element formed inside a contact hole, the switching element includes first and second conductive layers and a gap in... Agent: Crowell & Moring LLP Intellectual Property Group

20100165695 - Memory cell array: Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a... Agent: Crowell & Moring LLP Intellectual Property Group

20100165696 - Memory cell array: Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a... Agent: Crowell & Moring LLP Intellectual Property Group

20100165697 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting with the first wirings, and a plurality of memory cells respectively arranged at intersections of the first and second wirings; a plurality of drivers that drive the first wirings;... Agent: Knobbe Martens Olson & Bear LLP

20100165698 - Non-volatile one-time - programmable and multiple-time programmable memory configuration circuit: A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate... Agent: Law Office Of J. Nicholas Gross, Prof. Corp.

20100165699 - Antifuse programmable memory array: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Cpa Global

20100165700 - One time programmable memory device and manufacturing method of one time programmable memory device: Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer;... Agent: Sherr & Vaughn, PLLC

20100165701 - Resistive memory: A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and... Agent: Knobbe Martens Olson & Bear LLP

20100165703 - Semiconductor device for supplying stable voltage to control electrode of transistor: A semiconductor device comprises an internal voltage generator circuit which includes a first transistor having a first and a second main electrode and a control electrode, a control circuit controlling a voltage between the second main electrode and the control electrode of the first transistor such that a voltage at... Agent: Sughrue Mion, PLLC

20100165702 - Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165704 - Circuit and method for a high speed memory cell: A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line,... Agent: Slater & Matsil, L.L.P.

20100165705 - Semiconductor integrated circuit: In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 and 21AR2. A second holding circuit 30B is dedicated to a... Agent: Mcdermott Will & Emery LLP

20100165706 - Static memory cell having independent data holding voltage: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage... Agent: Mattingly & Malur, P.C.

20100165708 - Memory controller and decoder: A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a... Agent: J C Patents

20100165707 - Read/write margin improvement in sram design using dual-gate transistors: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from... Agent: Slater & Matsil, L.L.P.

20100165709 - Robust sram memory cell capacitor plate voltage generator: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator... Agent: Stmicroelectronics, Inc.

20100165710 - Random access memory architecture including midpoint reference: A random access memory architecture includes a first series connected pair of memory elements (202, 206, 302, 306, 402, 404) having a first resistance and a second series connected pair of memory elements (204, 208, 304, 308, 406, 408) having a second resistance coupled in parallel with the first series... Agent: Ingrassia Fisher & Lorenz, P.C.

20100165718 - Apparatus and method for sensing multi-level cell data: A multi-level sensing apparatus of the non-volatile memory includes a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output; a reference voltage selector configured to select one of a second reference... Agent: Ip & T Law Firm PLC

20100165726 - Discharge phase change material memory: An information storage array includes a programmable material at a storage location and a capacitor set. A switching network charges the capacitor set to a first voltage and discharges the capacitor set at a second voltage. The second voltage is greater than the first voltage and it or a waveform... Agent: Goodwin Procter LLP Patent Administrator

20100165721 - Internal voltage generating circuit of phase change random access memory device and method thereof: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference... Agent: Ip & T Law Firm PLC

20100165713 - Method for low power accessing a phase change memory device: A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20100165712 - Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory: According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20100165714 - Method of storing an indication of whether a memory location in phase change memory needs programming: A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to... Agent: Seed Intellectual Property Law Group PLLC

20100165729 - Nonvolatile memory device and related methods of operation: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of... Agent: Volentine & Whitt PLLC

20100165716 - Nonvolatile memory with ovonic threshold switches: A memory device including a plurality of memory cells being arranged in a matrix having a plurality of rows and a plurality of columns. Each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The memory... Agent: Seed Intellectual Property Law Group PLLC

20100165728 - Phase change device having two or more substantial amorphous regions in high resistance state: Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100165727 - Phase change material memory having no erase cycle: An information storage array includes a programmable material at one or more storage locations and pulse generation circuitry for generating at least two pulses—in particular, a write pulse that writes a value into the programmable material an erase pulse that erases a value from the programmable material. In general, the... Agent: Goodwin Procter LLP Patent Administrator

20100165722 - Phase change memory: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of... Agent: Quintero Law Office, PC

20100165723 - Phase change memory: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor... Agent: Quintero Law Office, PC

20100165719 - Phase change memory device: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20100165715 - Protection register for a phase-change memory: A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are... Agent: Seed Intellectual Property Law Group PLLC

20100165725 - Reliable set operation for phase-change memory cell: A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell.... Agent: Schwabe, Williamson & Wyatt, P.C.

20100165711 - Set algorithm for phase change memory cell: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100165720 - Verification circuits and methods for phase change memory array: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as... Agent: Quintero Law Office, PC

20100165724 - Word-line driver including pull-up resistor and pull-down transistor: Embodiments include but are not limited to apparatuses and systems including a plurality of memory cells, each memory cell including a selector and a storage element coupled to the selector. A word-line may be coupled to the memory cells and may have a word-line driver including a pull-up resistor coupled... Agent: Schwabe, Williamson & Wyatt, P.C.

20100165717 - Write driver circuit of pram: A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell... Agent: Ip & T Law Firm PLC

20100165731 - Memory device and operating method: A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells... Agent: Volentine & Whitt PLLC

20100165730 - Reading memory cells using multiple thresholds: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read... Agent: Darby & Darby P.C.

20100165732 - Flash memory apparatus and read operation control method therefor: A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each block of the plurality of... Agent: Ladas & Parry LLP

20100165733 - Nand nonvolatile semiconductor memory: A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165737 - Electromechanical memory devices and methods of manufacturing the same: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart... Agent: Mills & Onello LLP

20100165736 - Flash memory device and manufacturing method of the same: A flash memory device and a method for manufacturing the same are provided. The flash memory device can include first and second memory gates on a substrate, an oxide layer on sides of and on the substrate outside of the first and second memory gates, a source poly contact between... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20100165735 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory of an aspect of the present invention comprises a voltage step-down circuit including a first and a second circuit to achieve a voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage, a transfer transistor to transfer the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165734 - System and method for data recovery in a disabled integrated circuit: Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read... Agent: Pitney Bowes Inc.

20100165741 - Dynamic pass voltage: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.... Agent: Brooks, Cameron & Huebsch , PLLC

20100165742 - Methods and circuits for generating a high voltage and related semiconductor memory devices: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage... Agent: Myers Bigel Sibley & Sajovec

20100165738 - Non-volatile memory and method for sensing with pipelined corrections for neighboring perturbations: A page of non-volatile multi-level storage elements on a word line WLn is sensed in parallel while compensating for perturbations from a neighboring page on an adjacent word line WLn+1. First, the programmed thresholds of storage elements on WLn+1 are sensed in the time domain and encoded as time markers.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100165739 - Non-volatile multilevel memory cell programming: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number... Agent: Brooks, Cameron & Huebsch , PLLC

20100165740 - Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line: A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165743 - Non-volatile memory and method with continuous scanning time-domain sensing: A page of non-volatile multi-level memory cells on a word line is sensed in parallel by sense amps via bit lines. A predetermined input sensing voltage as an increasing function of time applied to the word line allows scanning of the entire range of thresholds of the memory cell in... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100165744 - Semiconductor memory device: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165745 - Non-volatile memory device and driving method thereof: A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first... Agent: Sherr & Vaughn, PLLC

20100165747 - Non-volatile memory cell healing: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage,... Agent: Brooks, Cameron & Huebsch , PLLC

20100165746 - Semiconductor memory cell, method for manufacturing the same and method for operating the same: A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a... Agent: Sherr & Vaughn, PLLC

20100165748 - Erase completion recognition: Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively... Agent: Schwabe, Williamson & Wyatt, P.C.

20100165749 - Sense amplifier used in the write operations of sram: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes... Agent: Slater & Matsil, L.L.P.

20100165750 - Data input device of semiconductor memory appartus and control method thereof: A data input device of a semiconductor memory apparatus includes input means configured to input data; precharge means configured to supply a precharge voltage for converting inputted data to a differential signal; enable means configured to enable the input means and the precharge means to operate; and control means configured... Agent: Ip & T Law Firm PLC

20100165751 - Data output device for semiconductor memory apparatus: A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving means and drive an output of data; and adjustment means configured to adjust... Agent: Ip & T Law Firm PLC

20100165752 - Level shifter: A level shifter circuit includes first and second supply inputs for receiving a first supply voltage and a second supply voltage, respectively. The level shifter circuit further comprises a shifting circuit configured to receive an input voltage and output a selected one of the first supply voltage and the second... Agent: Seed Intellectual Property Law Group PLLC

20100165753 - Method and apparatus for reducing leakage in bit lines of a memory device: A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100165754 - Signal synchronization in multi-voltage domains: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp)... Agent: Docket Clerk

20100165755 - Single-ended bit line based storage system: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100165756 - Methods and systems to improve write response times of memory cells: Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while... Agent: Garrett Ip, LLC

20100165757 - Semiconductor memory device: A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165760 - Data strobe signal noise protection apparatus and semiconductor integrated circuit: A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of a data strobe signal in response to a control signal and a controller configured to determine when a burst operation completes and to generate the control signal.... Agent: Ladas & Parry LLP

20100165761 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation... Agent: Ip & T Law Firm PLC

20100165762 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation... Agent: Ip & T Law Firm PLC

20100165758 - Semiconductor memory device and method for operating the same: The semiconductor memory device includes a data input/output unit configured to input data synchronously with a data clock and to output the data to a memory cell in response to an output strobe signal; and an output strobe signal generation unit configured to output the output strobe signal, wherein the... Agent: Ip & T Law Firm PLC

20100165759 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response... Agent: Ip & T Law Firm PLC

20100165763 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory banks each having a plurality of memory cell arrays, a plurality of sense amplification units corresponding to the memory banks, configured to sense data corresponding to a selected memory cell to amplify the sensed data, and a common delay unit configured... Agent: Ip & T Law Firm PLC

20100165764 - Memory device with reduced current leakage: The memory device (for example, a DRAM) includes a matrix of memory cells arranged in a plurality of rows and columns (for example, organized in pairs), which include redundancy rows and columns for replacing defective rows and columns. Each one of a plurality of bit lines is connected to the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20100165765 - Protection register for a non-volatile memory: A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The... Agent: Seed Intellectual Property Law Group PLLC

20100165766 - Semiconductor memory device: A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of... Agent: Ip & T Law Firm PLC

20100165767 - Asymmetric sense amplifier: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB)... Agent: Slater & Matsil, L.L.P.

20100165768 - Bit line precharge circuit and a semiconductor memory apparatus using the same: A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response... Agent: Ip & T Law Firm PLC

20100165769 - Semiconductor memory device having auto-precharge function: To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write... Agent: Mcdermott Will & Emery LLP

20100165770 - Semiconductor memory device: A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100165771 - Semiconductor memory device: A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which... Agent: Knobbe Martens Olson & Bear LLP

20100165772 - Self aligned back-gate for floating body cell memory erase: In some embodiments all cells within a word-line of a floating body cell memory are erased. A back-gate of the floating body cell memory is self-aligned with the word line, and the erasing is performed using a back-gate bias. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Cpa Global

20100165773 - Semiconductor memory device for self refresh and memory system having the same: A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to... Agent: Stanzione & Kim, LLP

20100165775 - Semiconductor device having electrical fuses with less power consumption and interconnection arrangement: In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The... Agent: Mcdermott Will & Emery LLP

20100165774 - Small-sized fuse box and semiconductor integrated circuit having the same: Disclosed are a fuse box and a semiconductor integrated circuit having the same. The semiconductor integrated circuit includes a plurality of banks, column control blocks, and column fuse blocks. The plurality of banks including a plurality of mat rows and mat columns. The banks are arranged in row and column... Agent: Ladas & Parry LLP

20100165777 - Circuit for voltage pump and a semiconductor memory apparatus using the same: A voltage pump circuit includes a pumping unit configured to include a plurality of pumps and perform voltage pumping and a pumping control unit configured to generate control signals for selectively driving the pumps in response to a mode determination signal.... Agent: Ip & T Law Firm PLC

20100165776 - Semiconductor device: A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the... Agent: Mcdermott Will & Emery LLP

20100165779 - Row decoder for a memory device: A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a... Agent: Seed Intellectual Property Law Group PLLC

20100165778 - Word line driver circuit with reduced leakage: A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals... Agent: Ryan, Mason & Lewis, LLP

20100165780 - Dynamic random access memory with shadow writes: Methods and apparatus are disclosed for reducing write-to-read turnaround times using shadow writes in memory controllers and in DRAM. Embodiments of controllers including shadow write control logic may, in response to receiving a write request, issue an external write column address strobe (CAS) to DRAM to latch a valid write... Agent: Lawrence M. Mennemeier

20100165781 - Internal write/read pulse generating circuit of a semiconductor memory apparatus: A control clock generating unit outputs a clock as a control clock when a column address strobe pulse is input and fixes the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled. An internal pulse generating unit outputs an external write... Agent: Venable LLP

20100165782 - Memory system for selectively transmitting command and address signals: A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and... Agent: Muir Patent Consulting, PLLC

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