|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval June invention type 06/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/24/2010 > patent applications in patent subcategories.
20100157641 - Memory device with adaptive capacity: A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on... Agent: Darby & Darby P.C.
20100157644 - Configurable memory interface to provide serial and parallel access to memories: The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access... Agent: Unity Semiconductor Corporation
20100157647 - Memory access circuits and layout of the same for cross-point memory arrays: An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit... Agent: Unity Semiconductor Corporation
20100157645 - Memory module and layout method therefor: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied... Agent: Morrison & Foerster LLP
20100157646 - Methods and apparatus for disabling a memory-array portion: A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.... Agent: Goodwin Procter LLP Patent Administrator
20100157642 - Mitigation of charge sharing in memory devices: One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An... Agent: Texas Instruments Incorporated
20100157643 - Semiconductor memory apparatus: A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first data line and a second data line at a predetermined distance, respectively,... Agent: Venable LLP
20100157648 - Semiconductor integrated circuit device with fuse elements and control method therefore: A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured... Agent: Turocy & Watson, LLP
20100157649 - Transistor bit cell rom architecture: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining... Agent: Cochran Freund & Young LLC Lsi Corporation
20100157650 - Ferroelectric memory: A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control... Agent: Knobbe Martens Olson & Bear LLP
20100157654 - Balancing a signal margin of a resistance based memory circuit: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction... Agent: Qualcomm Incorporated
20100157658 - Conductive metal oxide structures in non-volatile re-writable memory devices: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions... Agent: Unity Semiconductor Corporation
20100157659 - Digital potentiometer using third dimensional memory: A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such... Agent: Unity Semiconductor Corporation
20100157651 - Method of programming a nonvolatile memory device containing a carbon storage material: A nonvolatile memory cell includes a steering element located in series with a storage element, where the storage element comprises a carbon material. A method of programming the cell includes applying a reset pulse to change a resistivity state of the carbon material from a first state to a second... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100157657 - Multi-resistive state memory device with conductive oxide electrodes: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one... Agent: Unity Semiconductor Corporation
20100157652 - Programming a memory cell with a diode in series by applying reverse bias: A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100157653 - Quad memory cell and method of making same: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100157656 - Resistance change memory: A resistance change memory of an aspect of the present invention including memory cells including resistance change memory element, word lines connected to the memory cells, a row decoder which activates the word lines, redundant cells used instead of defective cells, a redundant word line connected to redundant cells, a... Agent: Knobbe Martens Olson & Bear LLP
20100157655 - Resistive memory and data write-in method: An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100157660 - Multiple-valued dram: Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected... Agent: Cantor Colburn, LLP
20100157661 - Semiconductor memory device: A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion,... Agent: Knobbe Martens Olson & Bear LLP
20100157663 - Information storage device and method of operating the same: An information storage device includes a memory region having a magnetic track and a write/read unit, and a control circuit connected to the memory region. First and second switching devices are connected to both ends of the magnetic track, and a third switching device is connected to the write/read unit.... Agent: Harness, Dickey & Pierce, P.L.C
20100157664 - Magnetoresistive memory cell using floating body effect, memory device having the same, and method of operating the memory device: A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be... Agent: Ip & T Law Firm PLC
20100157662 - Mram and method for writing in mram: In one embodiment of the present invention, an MRAM is an MRAM including: a plurality of write word lines; a plurality of bit lines provided so as to intersect with the write word lines; and TMR elements provided at respective intersections of the write word lines and the bit lines.... Agent: Harness, Dickey & Pierce, P.L.C
20100157665 - Memory cell device and programming methods: A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100157666 - Method for reading semiconductor memories and semiconductor memory: A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents may be... Agent: Seed Intellectual Property Law Group PLLC
20100157667 - Capacitorless dram memory cell comprising a partially-depleted mosfet device comprising a gate insulator in two parts: The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a... Agent: Oliff & Berridge, PLC
20100157668 - Memory device and method of operating and fabricating the same: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods... Agent: Harness, Dickey & Pierce, P.L.C
20100157671 - Data refresh for non-volatile storage: Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored... Agent: Vierra Magen/sandisk Corporation
20100157673 - Non-volatile semiconductor memory device and method of reading the same: A non-volatile semiconductor memory device capable of preventing reading failure during the occurrence of the FG-FG coupling effect is disclosed. The non-volatile semiconductor memory device includes a memory cell array, each cell of which stores at least two bits, such as LSB and MSB, using different threshold voltages. In addition,... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100157675 - Programming orders for reducing distortion in arrays of multi-level analog memory cells: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the... Agent: D. Kligler I.p. Services Ltd
20100157674 - Two levels of voltage regulation supplied for logic and data programming voltage of a memory device: Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash... Agent: Fish & Richardson P.C.
20100157672 - Wordline temperature compensation: A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature compensated wordline signal(s) to the nonvolatile memory. The temperature compensated wordline signals change as the temperature dependent read window changes.... Agent: Lemoine Patent Services, PLLC
20100157669 - Floating gate inverter type memory cell and array: A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20100157676 - Nand flash memory: A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100157678 - Non-volatile memory with boost structures: A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost... Agent: Vierra Magen/sandisk Corporation
20100157677 - Non-volatile semiconductor memory: A non-volatile semiconductor memory device is provided so that chip size may not increase and occurrence of misreading induced by capacitance of adjacent global bit lines GBL may be prevented, and includes: a non-volatile memory cell array for recording data by setting a threshold voltage for each memory cell transistor... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100157683 - Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100157684 - Flash memory program inhibit scheme: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100157682 - Method of enhancing charge storage in an e2prom cell: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation
20100157679 - Monitor structure for monitoring a change of a memory content: A monitor structure for monitoring a change of a memory content in a memory field of a non-volatile memory comprising a reference transistor in the memory field and a monitor transistor. The monitor transistor and the reference transistor comprise a common floating gate. Moreover, the memory field is arranged in... Agent: Dickstein Shapiro LLP
20100157681 - Read, verify word line reference voltage to track source level: A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100157680 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100157686 - Method and apparatus for programming nonvolatile memory: A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100157685 - Programming in a memory device: Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the... Agent: Leffert Jay & Polglaze, P.A.
20100157670 - High voltage switching circuitry for a cross-point array: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit... Agent: Unity Semiconductor Corporation
20100157687 - Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a... Agent: Dla Piper LLP (us )
20100157688 - Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors: A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0 v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which... Agent: Lewis And Roca LLP
20100157689 - Semiconductor device: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit... Agent: Miles & Stockbridge PC
20100157690 - Semiconductor memory device of single gate structure: A single gate semiconductor memory device includes a high-potential well on an upper portion of a semiconductor substrate; a first well on an upper portion of the high potential second conductive type well; a second well spaced apart from the first well on the upper portion of the high potential... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100157696 - Semiconductor memory apparatus and a method for reading data stored therein: A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality... Agent: Ip & T Law Firm PLC
20100157691 - Dual port pld embedded memory block to support read-before-write in one clock cycle: A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent... Agent: Martine Penilla & Gencarella, LLP
20100157692 - Distributed vdc for sram memory: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The... Agent: Slater & Matsil, L.L.P.
20100157694 - Low couple effect bit-line voltage generator: A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a... Agent: Volpe And Koenig, P.C.
20100157693 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit... Agent: Turocy & Watson, LLP
20100157697 - Semiconductor device and system: A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode... Agent: Arent Fox LLP
20100157695 - Voltage shifting word-line driver and method therefor: A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected... Agent: Larson Newman & Abel, LLP
20100157698 - Capacitively isolated mismatch compensated sense amplifier: According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce... Agent: Cantor Colburn LLP-ibm Burlington
20100157699 - Write circuitry for hierarchical memory architecture: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality... Agent: Hogan & Hartson LLP
20100157700 - Apparatus and systems for vt invariant ddr3 sdram write leveling: Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial... Agent: Duft Bornsen & Fishman LLP
20100157701 - Delay line and memory control circuit utilizing the delay line: A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition,... Agent: North America Intellectual Property Corporation
20100157702 - Semiconductor memory device adopting improved local input/output line precharging scheme: A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line... Agent: Harness, Dickey & Pierce, P.L.C
20100157703 - Embedded memory repair: A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures... Agent: Ryan, Mason & Lewis, LLP
20100157704 - Semiconductor memory device that can relief defective address: Plural nonvolatile address storing circuits hold address data. A serial transfer circuit sequentially transfers the address data stored in each of the nonvolatile address storing circuits. A serial reception circuit sequentially receives the address data transferred by the serial transfer circuit. An address latch circuit holds the address data received... Agent: Mcginn Intellectual Property Law Group, PLLC
20100157706 - Methods and apparatuses for improving reduced power operations in embedded memory arrays: Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively... Agent: Dorsey & Whitney LLP On Behalf Of Sun Microsystems, Inc.
20100157705 - Register file circuits with p-type evaluation: Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low”... Agent: Intel Corporation C/o Cpa Global
20100157708 - Noise tolerant sense circuit: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value... Agent: Hogan & Hartson LLP
20100157707 - Sense amplifier with redundancy: A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.... Agent: Ryan, Mason & Lewis, LLP
20100157709 - Semiconductor memory device having shared temperature control circuit: A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the... Agent: Mills & Onello LLP
20100157710 - Array operation using a schottky diode as a non-ohmic isolation device: A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single... Agent: Unity Semiconductor Corporation
20100157714 - Apparatus and method for self-refreshing dynamic random access memory cells: A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100157712 - Refresh circuit of semiconductor memory apparatus: A refresh circuit of a semiconductor memory apparatus includes a bank active signal generator configured to selectively enable a plurality of bank active signals in response to a piled signal and disable the plurality of bank active signals in response to a plurality of precharge pulses when a refresh signal... Agent: Venable LLP
20100157711 - Self-refresh based power saving circuit and method: A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.
20100157713 - Semiconductor device with refresh control circuit: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times... Agent: Mcginn Intellectual Property Law Group, PLLC
20100157715 - Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation: A semiconductor device that can implement a method comprising selecting a group of rows of auxiliary cells forming part of an auxiliary memory unit, the auxiliary cells being arranged into rows and columns; driving a plurality of bitlines each connected to a respective column of the auxiliary cells, so as... Agent: Smart & Biggar
20100157716 - Sub word line driving circuit: A sub word line driving circuit includes a FX driver which buffers an inverted FX signal to generate a FX signal in response to a control signal, and a sub word line driver which is supplied with the FX signal and receives a main word line signal to drive a... Agent: Cooper & Dunham, LLP
20100157717 - Semiconductor integrated circuit capable of controlling read command: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a... Agent: Ladas & Parry LLP
20100157718 - Configurable latching for asynchronous memories: A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for... Agent: Trop, Pruner & Hu, P.C.
20100157719 - Circuit for generating read and signal and circuit for generating internal clock using the same: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal... Agent: Cooper & Dunham, LLP06/17/2010 > patent applications in patent subcategories.
20100149849 - Memory array on more than one die: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100149850 - Nonvolatile semiconductor memory device: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having series-connected memory cells; wordlines; and a bitline pair connected to the memory cell blocks, one functioning as a readout bitline, the other one... Agent: Knobbe Martens Olson & Bear LLP
20100149851 - Memory device and manufacturing method the same: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device... Agent: Eric Robinson
20100149852 - Charge retention structures and techniques for implementing charge controlled resistors in memory cells and arrays of memory: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell.... Agent: Kokka & Backus, PC
20100149855 - Integrated circuitry for semiconductor memory: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed... Agent: Trask Britt, P.C./ Micron Technology
20100149854 - Semiconductor device storage cell structure, method of operation, and method of manufacture: A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a... Agent: Haverstock & Owens LLP
20100149853 - Thin film capacitor, and display device and memory cell employing the same, and manufacturing methods of them: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a... Agent: Nixon & Vanderhye, PC
20100149861 - Phase change memory device: A phase change memory device includes a plurality of programming current driving blocks each of which is configured to provide a corresponding phase change memory cell with a programming current corresponding to input data and a programming current adjusting block commonly connected to the plurality of programming current driving blocks... Agent: Ip & T Law Firm PLC
20100149859 - Phase-change memory device: A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of input data and output write control codes with a code update period controlled according to an activation period of one of the write control signal,... Agent: Ip & T Law Firm PLC
20100149860 - Phase-change memory device: A phase-change memory device performs a buffer program operation in response to a buffer program command sequence. The phase-change memory device includes a page buffer unit configured to store a plurality of input data corresponding to a word count value of a buffer program command sequence and selectively output the... Agent: Ip & T Law Firm PLC
20100149858 - Providing a ready-busy signal from a non-volatile memory device to a memory controller: A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that... Agent: Trop, Pruner & Hu, P.C.
20100149857 - Reading threshold switching memory cells: Using the voltage across a threshold switching cell to sense the state of the cell, rather than sensing current through the cell, may result in a faster read. In some embodiments, current consumption during reading of conductive states may be reduced by using a capacitor coupled across the cell.... Agent: Trop, Pruner & Hu, P.C.
20100149856 - Writing memory cells exhibiting threshold switch behavior: A memory cell exhibiting threshold switch behavior, such as a phase change memory, can be programmed in a way that eliminates the need for a separate post-programming verification cycle. In particular, a circuit can be used to apply the programming pulse to a cell in a way that determines whether... Agent: Trop, Pruner & Hu, P.C.
20100149862 - Magnetic random access memory: A magnetic random access memory comprises a magnetic recording layer equipped with a magnetization reversal region having a reversible magnetization and through which a write current is made to flow in the in-plane direction, a magnetization fixed layer having a fixed magnetization, a nonmagnetic layer provided between the magnetization reversal... Agent: Young & Thompson
20100149863 - Magnetic tracks, information storage devices including magnetic tracks, and methods of operating information storage devices: A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality... Agent: Harness, Dickey & Pierce, P.L.C
20100149864 - Memory circuit with quantum well-type carrier storage: Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel,... Agent: Crawford Maunu PLLC
20100149865 - Scr matrix storage device: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the... Agent: Goodwin Procter LLP Patent Administrator
20100149866 - Systems and devices including memory resistant to program disturb and methods of using, making, and operating the same: Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has... Agent: Fletcher Yoder (micron Technology, Inc.)
20100149868 - Access method of non-volatile memory device: Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected... Agent: Harness, Dickey & Pierce, P.L.C
20100149869 - Multi-level cell flash memory device and read method: A method of reading data of a multi-level cell (MLC) flash memory device is disclosed. The method includes reading a least significant bit (LSB) and a most significant bit (MSB) of the data programmed to a plurality of memory cells. Reading each of the LSB and MSB includes; reading a... Agent: Volentine & Whitt PLLC
20100149870 - Non-volatile semiconductor memory, and the method thereof: A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100149872 - Nonvolatile memory device and method for operating the same: Methods for operating a nonvolatile memory device including multi-level cells configured to store at least n logic states, where n is equal to or greater than four are provided. The methods may include selecting at least one read voltage for a read operation based on information set at a portion... Agent: Lee & Morse, P.C.
20100149867 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a nonvolatile memory which includes a block having a plurality of memory cell groups, each of the memory cell groups being electrically connected to a plurality of bit lines and electrically connected to a common word line, each memory cell being recordable of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100149871 - Reading method of nonvolatile semiconductor memory device: Reading methods of a nonvolatile semiconductor memory device are described herein. Methods may include supplying, to a word line, one of a voltage corresponding to a highest reading level or a voltage having a level higher than a first reading level of a read operation to be performed on the... Agent: Lee & Morse, P.C.
20100149874 - Non-volatile memory apparatus and method with deep n-well: An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well... Agent: Raj Abhyanker LLP
20100149873 - Push-pull fpga cell: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having... Agent: Lewis And Roca LLP
20100149875 - Nonvolatile semiconductor memory device: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines,... Agent: The Marbury Law Group, PLLC
20100149876 - Reverse reading in non-volatile memory with compensation for coupling: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where... Agent: Vierra Magen/sandisk Corporation
20100149877 - Flash memory device and read method: A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line... Agent: Volentine & Whitt PLLC
20100149879 - Flash memory array of floating gate-based non-volatile memory cells: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of... Agent: Fogg & Powers LLC/intersil Americas Inc.
20100149878 - Flotox type eeprom: A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on-one correspondence to the plural floating gates 11; a control... Agent: Rabin & Berdo, PC
20100149880 - Window enlargement by selective erase of non-volatile memory cells: A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells.... Agent: Stout, Uxa, Buyan & Mullins LLP
20100149881 - Adaptive erase and soft programming for memory: An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and... Agent: Vierra Magen/sandisk Corporation
20100149882 - Methods of operating embedded flash memory devices: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer... Agent: Slater & Matsil LLP
20100149883 - Semiconductor device: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input... Agent: Miles & Stockbridge PC
20100149884 - Reduction of power consumption in a memory device during sleep mode of operation: The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100149885 - Memory circuit and method of writing data to and reading data from memory circuit: A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data... Agent: Staas & Halsey LLP
20100149886 - Semiconductor memory device and method for operating the same: In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source... Agent: Harness, Dickey & Pierce, P.L.C
20100149887 - Semiconductor memory device and method of controlling power source: A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included... Agent: Sughrue Mion, PLLC
20100149888 - Reduced signal interface memory device, system, and method: A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one.... Agent: Lemoine Patent Services, PLLC
20100149890 - Devices and methods for controlling a slew rate of a signal line: In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to... Agent: Knobbe Martens Olson & Bear LLP
20100149891 - Semiconductor memory device including reset control circuit: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a... Agent: Ip & T Law Firm PLC
20100149889 - System with controller and memory: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... Agent: Sughrue Mion, PLLC
20100149892 - Semiconductor memory device and method for operating the same: A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is... Agent: Ip & T Law Firm PLC
20100149893 - Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.... Agent: Stout, Uxa, Buyan & Mullins LLP
20100149894 - Semiconductor memory device that can relief defective address: To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a... Agent: Mcginn Intellectual Property Law Group, PLLC
20100149895 - High speed carbon nanotube memory: In order to realize high speed carbon nanotube memory, bit line is multi-divided into short lines for reducing parasitic capacitance. For reading, a small local sense amp is composed of a local pre amplifier and a local main amplifier with high gain, and a simple global sense amp is composed... Agent: Juhan Kim
20100149897 - Low current wide vref range input buffer: A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.... Agent: Dickstein Shapiro LLP
20100149896 - Sense amplifier: A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first... Agent: Schwegman, Lundberg & Woessner / Atmel
20100149898 - Antifuses and program circuits having the same: Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary... Agent: Harness, Dickey & Pierce, P.L.C
20100149899 - Table lookup voltage compensation for memory cells: Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100149900 - Semiconductor memory device having selective activation circuit for selectively activating circuit areas: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included... Agent: Sughrue Mion, PLLC
20100149901 - Word line decoder circuit: A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to... Agent: Jianq Chyun Intellectual Property Office06/10/2010 > patent applications in patent subcategories.
20100142241 - Cam cell memory device: A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell configured to output a ground voltage in... Agent: Ip & T Law Firm PLC
20100142242 - Read and match circuit for low-voltage content addressable memory: The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the... Agent: Sinorica, LLC
20100142248 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation
20100142243 - Data storage system with removable memory module having parallel channels of dram memory and flash memory: A data storage system 400 includes a first circuit board 401, a plurality of sockets 402 coupled to the first circuit board 401, an connector 403 coupled to each of the sockets 402 for coupling each of the sockets 402 to external circuitry, and a plurality of memory modules 100,... Agent: Xilinx, Inc Attn: Legal Department
20100142244 - Memory module and data input/output system: A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower... Agent: Ladas & Parry LLP
20100142247 - Memory modules and methods for modifying memory subsystem performance: Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes... Agent: Hartman & Hartman, P.C.
20100142245 - Semiconductor device: A semiconductor device includes: a memory cell array having a plurality of memory cells arranged in arrays; a plurality of bit lines formed correspondingly to a column arrangement of the memory cells; a plurality of word lines formed correspondingly to a row arrangement of the memory cells; a plate line... Agent: Rader Fishman & Grauer PLLC
20100142246 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions... Agent: Mcdermott Will & Emery LLP
20100142251 - Memory devices having programmable elements with accurate operating parameters stored thereon: Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating... Agent: Fletcher Yoder (micron Technology, Inc.)
20100142249 - Nonvolatile memory device using a variable resistive element: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile memory cells, write global bit lines shared by the plurality of memory banks, read global bit lines shared by the plurality of memory banks, and a dummy global bit line arranged between the write... Agent: F. Chau & Associates, LLC
20100142252 - Reconfigurable input/output in hierarchical memory link: A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected... Agent: Mills & Onello LLP
20100142250 - Semiconductor memory and system: A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines when one of the... Agent: Arent Fox LLP
20100142253 - Semiconductor memory device: A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having a threshold voltage which has a certain relationship with... Agent: Knobbe Martens Olson & Bear LLP
20100142256 - Method of programming a nonvolatile memory cell by reverse biasing a diode steering element to set a storage element: A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100142255 - Method to program a memory cell comprising a carbon nanotube fabric element and a steering element: A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the... Agent: Dugan & Dugan, PC
20100142254 - Nonvolatile memory device using variable resistive element: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively.... Agent: F. Chau & Associates, LLC
20100142257 - Semiconductor storage device: In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage... Agent: Brinks Hofer Gilson & Lione
20100142258 - Ten-transistor static random access memory architecture: The present invention discloses a 10T SRAM architecture, wherein two symmetric data access paths are added to a 6T SRAM architecture. Each data access path has two transistors, whereby the read signals are no more driven by the memory unit, wherefore the dimensions of the transistors inside the 10T SRAM... Agent: Sinorica, LLC
20100142260 - Data integrity preservation in spin transfer torque magnetoresistive random access memory: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit... Agent: Qualcomm Incorporated
20100142259 - Nanogaps: methods and devices containing same: Disclosed are methods of fabricating nanogaps and various devices composed of nanogaps. The nanogap devices disclosed herein can be used as in a number of electronic, photonic and quantum mechanical devices, including field-effect transistors and logic circuits.... Agent: Woodcock Washburn LLP
20100142261 - Information recording and reproducing apparatus: An information recording and reproducing apparatus, includes: a stacked structure including an electrode layer and a recording layer; a buffer layer added to the electrode layer; and a voltage application unit configured to apply a voltage to the recording layer, produce a phase change in the recording layer, and record... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100142262 - Information recording and reproducing apparatus: An information recording and reproducing apparatus, includes: a recording layer including a first layer including a first compound, the first compound being a conjugated compound including at least two types of cation elements, at least one selected from the cation elements being a transition element having a d orbit incompletely... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100142263 - Semiconductor switching device: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided... Agent: Timothy M Honeycutt Attorney At Law
20100142264 - Magnetic memory cell, magnetic random access memory, and data read/write method for magnetic random access memory: A magnetic memory cell 1 has a magnetic recording layer 10 and a pinned layer 30 connected to the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 includes a magnetization switching region 13, a first magnetization fixed region 11 and a second magnetization fixed... Agent: Sughrue Mion, PLLC
20100142265 - Magnetic structure with multiple-bit storage capabilities: A magnetic structure (2) comprising a magnetic layer (18) having an upper surface and a lower surface is disclosed. The magnetic layer comprises a plurality of regions, each of which is adapted to be magnetised predominantly along a first or second direction. The magnetic layer further comprises at least one... Agent: Zilka-kotab, PC
20100142266 - Vertical field-effect transistor: A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the... Agent: Brinks Hofer Gilson & Lione/infineon Infineon
20100142268 - Programming method to reduce gate coupling interference for non-volatile memory: A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory... Agent: Leffert Jay & Polglaze, P.A.
20100142269 - Memory employing redundant cell array of multi-bit cells: A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically... Agent: Darby/spansion C/o Darby & Darby P.C.
20100142272 - Method and apparatus for testing the connectivity of a flash memory chip: In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan... Agent: Dla Piper LLP (us )
20100142274 - Multilevel memory cell operation: One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a... Agent: Brooks, Cameron & Huebsch , PLLC
20100142273 - Programming methods for multi-level memory devices: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The... Agent: Knobbe Martens Olson & Bear LLP
20100142270 - Semiconductor memory device and semiconductor memory system storing multilevel data: A first memory cell stores data of k bits in one cell. A second memory cell stores data of h bits (h<k) in one cell. Data of i bits (i<=k) is stored in the first memory cell, and data of h bits (h<i) generated from the i-bit data is stored... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100142271 - Semiconductor memory device capable of preventing a shift of threshold voltage: A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100142275 - Continuous address space in non-volatile-memories (nvm) using efficient management methods for array deficiencies: The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming... Agent: William H. Dippert Eckert Seamans Cherin & Mellott, LLC
20100142276 - Nonvolatile memory: A nonvolatile memory includes a memory cell allay including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value... Agent: Staas & Halsey LLP
20100142278 - Page buffer circuit, nonvolatile device including the same, and method of operating the nonvolatile memory device: A page buffer circuit comprises a sense unit, a latch unit, and a bit line voltage control unit. The sense unit is configured to couple a bit line and a sense node in response to a sense control signal in response to the sense control signal. The latch unit includes... Agent: Ip & T Law Firm PLC
20100142277 - Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is... Agent: Ip & T Law Firm PLC
20100142279 - Nonvolatile semiconductor memory device having assist gate: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line... Agent: Mcdermott Will & Emery LLP
20100142280 - Programming memory devices: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum
20100142282 - Method of programming flash memory device: A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block... Agent: Townsend And Townsend And Crew, LLP
20100142281 - Non-volatile memory device and program method thereof: Disclosed is a program method of a non-volatile memory device which comprises classifying plural memory cells into aggressor cells and victim cells based on program data to be written in the plural memory cells; and programming the aggressor cells by a program manner different from the victim cells.... Agent: Myers Bigel Sibley & Sajovec
20100142283 - Program method with optimized voltage level for flash memory: A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster... Agent: Leffert Jay & Polglaze, P.A.
20100142284 - Deterministic-based programming in memory: Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on... Agent: Turocy & Watson, LLP
20100142267 - Memory cell shift estimation method and apparatus: Memory devices and methods are disclosed, such as those facilitating interpolation methods for reference memory cells based on their reference state and/or location in an array of memory cells. For example, a group of reference cells programmed to a subset of possible data states are utilized to interpolate for data... Agent: Leffert Jay & Polglaze, P.A.
20100142285 - Reducing read failure in a memory device: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain... Agent: Leffert Jay & Polglaze, P.A.
20100142290 - Output circuit for a semiconductor memory device and data output method: An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to... Agent: Young & Thompson
20100142286 - Auto-precharge signal generator: An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set... Agent: Ladas & Parry LLP
20100142287 - System and method for providing temperature data from a memory device having a temperature sensor: A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100142288 - Negative word line voltage generator for semiconductor memory device: A negative word line voltage generator for semiconductor memory device includes a comparison unit configured to compare a reference voltage and a feedback voltage and to output a comparison result as an output signal, a pull-down driving unit configured to pull down a negative word line voltage in response to... Agent: Ip & T Law Firm PLC
20100142289 - Nonvolatile semiconductor memory and method for testing the same: A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that... Agent: Mcginn Intellectual Property Law Group, PLLC
20100142291 - Mobile system on chip (soc) and mobile terminal using the mobile soc, and method for refreshing a memory in the mobile soc: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a... Agent: Lee & Morse, P.C.
20100142292 - Low power memory device: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and... Agent: Mahamedi Paradice Kreisman LLP
20100142293 - Boosting voltage generating circuit, negative voltage generating circuit, step-down voltage generating circuit, and semiconductor device: In a boosting voltage generating circuit, a boosting circuit unit generates boosting voltage according to a value of boosting voltage output by the boosting voltage generating circuit and an auxiliary boosting circuit unit supplies, immediately before electric current is consumed by a load supplied with the boosting voltage, voltage higher... Agent: Mcginn Intellectual Property Law Group, PLLC
20100142294 - Vertical transistor memory cell and array: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body... Agent: Courtney Staniford & Gregory LLP
20100142296 - Semiconductor memory device and delay locked loop control method thereof: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the... Agent: Ip & T Law Firm PLC
20100142295 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes a source signal generator configured to generate a source signal having a predetermined pulse width in response to a command signal, and a column selection signal generator configured to generate a column selection signal by controlling a pulse width of the source signal according to... Agent: Ip & T Law Firm PLC
20100142297 - Data driver: A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The... Agent: Ladas & Parry LLP
20100142299 - Anti-fuse repair control circuit and semiconductor device including dram having the same: In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal... Agent: Ladas & Parry LLP
20100142298 - Memory compiler redundancy: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on... Agent: Stolowitz Ford Cowger LLP
20100142300 - Semiconductor memory device and methods of performing a stress test on the semiconductor memory device: A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to... Agent: Qualcomm Incorporated
20100142301 - Semiconductor memory device and self refresh test method: A semiconductor memory device includes a memory cell array that includes a plurality of memory cells, an SR timer that determines a cycle of self refresh of the memory cell, a refresh counter that generates an internal address signal of the memory cell which is a target of the self... Agent: Sughrue Mion, PLLC
20100142302 - Semiconductor memory device and testing method therefor: A semiconductor memory device includes memory blocks, a redundancy determining circuit that can enter in a parallel test mode in which the both memory blocks are simultaneously accessed, and a verifying circuit that verifies data read from the memory blocks. When accessing normal cell areas of the memory blocks simultaneously,... Agent: Sughrue Mion, PLLC
20100142303 - Digitally-controllable delay for sense amplifier: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a... Agent: Qualcomm Incorporated
20100142304 - Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100142305 - Source control circuit and semiconductor memory device using the same: A source control circuit comprises a control signal generating unit for generating a standby signal which is enabled in a standby condition, and a switching unit connected between a power line for supplying power to an internal circuit and an external power and controlling the supply of the external power... Agent: Cooper & Dunham, LLP
20100142306 - Semiconductor memory, semiconductor device, and system: A semiconductor memory includes: a voltage supply circuit which supplies a first voltage to a word line when an internal circuit is in a standby state, and supplies a second voltage higher than the first voltage to the word line when the internal circuit is in an active state; and... Agent: Arent Fox LLP
20100142307 - Temperature protection for power capacitor: An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability.... Agent: Fsp LLC
20100142308 - Pipe latch circuit and driving method thereof: A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond... Agent: Ip & T Law Firm PLC06/03/2010 > patent applications in patent subcategories.
20100135057 - Multi-port memory device having serial input/output interface: A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged.... Agent: Ip & T Law Firm PLC
20100135056 - Semiconductor memory device: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads... Agent: Sughrue Mion, PLLC
20100135059 - Information storage devices using magnetic domain wall movement and methods of operating the same: Provided are information storage devices using movement of magnetic domain walls and methods of operating information storage devices. An information storage device includes a magnetic track and an operating unit. The magnetic track includes a plurality of magnetic domains separated by magnetic domain walls. The size of the operating unit... Agent: Harness, Dickey & Pierce, P.L.C
20100135058 - Magnetic memory, driving method thereof, and manufacturing method thereof: A magnetic memory, a driving method thereof, and a manufacturing method thereof are provided. The magnetic memory includes a plurality of lead structures, a plurality of first magnetic metal structures, a second magnetic metal structure, and an insulation layer. Each of the first magnetic metal structures is disposed between adjacent... Agent: Jianq Chyun Intellectual Property Office
20100135060 - Memory device and storage apparatus: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin... Agent: Sonnenschein Nath & Rosenthal LLP
20100135061 - Non-volatile memory cell with ferroelectric layer configurations: In some embodiments of the invention a non-volatile memory cell is provided with a first electrode, a second electrode, and one or more side layers of a ferroelectric metal oxide and a ferroelectric material layer between the first and second electrodes. The ferroelectric material layer may be provided between, e.g.,... Agent: Intellectual Property Group Seagate Technology Files
20100135062 - Very high speed fram for replacing sram: For replacing SRAM with very high speed FRAM, new memory architecture is realized such that plurality of FRAM cells is connected to a local bit line pair, a local sense amp is connected to the local bit line pair, a global sense amp is connected to the local sense amp... Agent: Juhan Kim
20100135063 - Semiconductor device including bit line groups: A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group... Agent: Morrison & Foerster LLP
20100135065 - Power-off apparatus, systems, and methods: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to... Agent: Schwegman, Lundberg & Woessner/micron
20100135064 - Switch and method of forming the same: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.... Agent: F. Chau & Associates, LLC
20100135066 - Bit line charge accumulation sensing for resistive changing memory: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region... Agent: Campbell Nelson Whipps, LLC
20100135067 - Non-volatile memory with stray magnetic field compensation: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that... Agent: Campbell Nelson Whipps, LLC
20100135069 - Resistance variable memory device: A resistance variable memory device is provided and includes a resistance variable memory cell that writes data by utilizing a spin transfer effect based on an injection current. The memory device also includes a driving circuit that generates a combined pulse of a plurality of write pulses and an offset... Agent: K&l Gates LLP
20100135068 - Resistance-change memory device: A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a direction of magnetization is switchable and that is formed on a conductive layer, and the stack is included in a resistance-change memory cell performing data writing... Agent: K&l Gates LLP
20100135070 - Adjustable write pulse generator within a chalcogenide memory device: An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory... Agent: Bae Systems
20100135071 - Microelectronic programmable device and methods of forming and programming the same: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the... Agent: Snell & Wilmer L.L.P. (main)
20100135072 - Spin-torque bit cell with unpinned reference layer and unidirectional write current: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100135073 - Organic electronic memory component, memory component arrangement and method for operating an organic electronic memory component: The invention relates to an organic electronic memory component having an electrode and a counterelectrode and an organic layer arrangement formed between said electrode and counterelectrode and in electrical contact herewith. wherein the organic layer arrangement comprises the following organic layers: an electrode-specific charge carrier transport layer and a counterelectrode-specific... Agent: Sutherland Asbill & Brennan LLP
20100135074 - Post-facto correction for cross coupling in a flash memory: A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that... Agent: Mpg, LLP And Sandisk
20100135075 - Reading non-volatile multilevel memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in... Agent: Brooks, Cameron & Huebsch , PLLC
20100135079 - Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data... Agent: Mcdermott Will & Emery LLP
20100135078 - Nonvolatile semiconductor memory: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100135080 - Fabrication method and structure of semiconductor non-volatile memory device: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100135081 - Nonvolatile memory device: A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a... Agent: Volentine & Whitt PLLC
20100135082 - Moving program verify level for programming of memory: Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements... Agent: Turocy & Watson, LLP
20100135076 - Method of performing read operation in flash memory device: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the... Agent: Townsend And Townsend And Crew, LLP
20100135077 - Method of performing read operation in flash memory device: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the... Agent: Townsend And Townsend And Crew, LLP
20100135083 - Nonvolatile memory device: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed. The memory device comprising: a first current detecting circuit comprising a first transistor... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100135084 - Wordline voltage transfer apparatus, systems, and methods: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that... Agent: Schwegman, Lundberg & Woessner/micron
20100135085 - Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell... Agent: Law Office Of Ido Tuchman (yor)
20100135086 - Method of operating non-volatile memory cell and memory device utilizing the method: A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.... Agent: J C Patents
20100135087 - Reading of the state of a non-volatile storage element: A method for reading of the state of a non-volatile memory element including conditioning the frequency of a first oscillator to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100135088 - Operation method of semiconductor device: Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode.... Agent: Harness, Dickey & Pierce, P.L.C
20100135090 - Apparatus and method for trimming static delay of a synchronizing circuit: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100135089 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100135092 - Circuit and method for testing multi-device systems: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system,... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100135091 - Semiconductor memory devices having redundancy arrays: A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells.... Agent: Harness, Dickey & Pierce, P.L.C
20100135093 - Operating voltage tuning method for static random access memory: An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to... Agent: North America Intellectual Property Corporation
20100135094 - High integrated semiconductor memory device: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units... Agent: Ip & T Law Firm PLC
20100135095 - Assistance in reset of data storage array: A system is capable of assisting in reset of a data storage array including data storage array including one or more data storage array nodes. The system includes a control unit coupled to the data storage array configured to produce a control signal to reset the data storage array, and... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100135096 - Antifuse circuit with well bias transistor: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100135098 - Power control circuit and semiconductor memory device using the same: A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto.... Agent: Cooper & Dunham, LLP
20100135099 - Power-on detector, operating method of power-on detector and memory device including the same: A power-on detector supplied with a power supply voltage from an external source and detects a variation of the power supply voltage. The operating method of the power-on detector comprises calculating the slope of the rise of power supply voltage from a first voltage to a second voltage higher than... Agent: F. Chau & Associates, LLC
20100135097 - System and method for supporting standard and voltage optimized dimms: A device includes a dynamic random access memory and a voltage regulator. The dynamic random access memory has a first input terminal connected to a first plurality of dual in-line memory module voltage pins, and a second input terminal. The dynamic random access memory is configured to receive a first... Agent: Larson Newman & Abel, LLP
20100135100 - Adjusting clock error across a circuit interface: A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase... Agent: Marc P. Schuyler / RambusPrevious industry: Electric power conversion systems
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