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Static information storage and retrieval May archived by USPTO category 05/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
05/27/2010 > patent applications in patent subcategories. archived by USPTO category

20100128507 - Circuit providing load isolation and memory domain translation for memory module: A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit... Agent: Knobbe Martens Olson & Bear LLP

20100128506 - Memory: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states... Agent: Mcdermott Will & Emery LLP

20100128508 - Semiconductor memory device: The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100128509 - Three-dimensional semiconductor devices and methods of operating the same: Provided are a three-dimensional semiconductor device and a method of operating the same. The three-dimensional semiconductor device includes: a plurality of word line structures on a substrate; active semiconductor patterns between the plurality of word line structures; and information storage elements between the plurality of word line structures and the... Agent: Myers Bigel Sibley & Sajovec

20100128510 - Magnetic data storage: The present invention can provide a magnetic memory structure comprising a column comprising a plurality of layers of magnetic material, each sized to adopt a single magnetic domain state, and a plurality of layers of non-magnetic material arranged as spacer layers between adjacent ones of the layers of magnetic material,... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100128511 - High density prom: The invention shows how diodes in a modern semiconductor process can be used as a very compact switch element in a Programmable Read Only Memory (PROM) using common integrated circuit fuse elements such as polysilicon and metal. This compact switch element allows very dense PROM arrays to be realized since... Agent: Eugene R. Worley

20100128513 - Semiconductor memory device: A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A bit line reads data stored in the memory cell from the other end of the ferroelectric capacitor. A... Agent: Knobbe Martens Olson & Bear LLP

20100128512 - Semiconductor memory device having cross-point structure: A semiconductor memory device having a cross-point structure comprising a plurality of first electrode wirings extending in the same direction, a plurality of second electrode wirings intersecting with the first electrode wirings, and memory materials for storing data at the intersection points of the first and second electrode wirings has... Agent: Nixon & Vanderhye, PC

20100128515 - Semiconductor memory: A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory... Agent: Arent Fox LLP

20100128514 - Semiconductor memory devices having bit lines: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load... Agent: Harness, Dickey & Pierce, P.L.C

20100128516 - Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control: A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of... Agent: Myers Bigel Sibley & Sajovec

20100128517 - Phase-change memory device with discharge of leakage currents in deselected bitlines and method for discharging leakage currents in deselected bitlines of a phase-change memory device: A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents... Agent: Seed Intellectual Property Law Group PLLC

20100128519 - Non volatile memory having increased sensing margin: A non volatile memory assembly that includes a reference element having: a reference component; and a reference transistor, wherein the reference component is electrically connected to the reference transistor, and the reference transistor controls the passage of current across the reference component; and at least one non volatile memory element... Agent: Campbell Nelson Whipps, LLC

20100128520 - Non volatile memory including stabilizing structures: An apparatus that includes a magnetic structure including a reference layer; and a free layer; an exchange coupling spacer layer; and a stabilizing layer, wherein the exchange coupling spacer layer is between the magnetic structure and the stabilizing layer and exchange couples the free layer of the magnetic structure to... Agent: Campbell Nelson Whipps, LLC

20100128518 - Novel spin momentum transfer mram design: We describe the structure and method of formation of a STT MTJ or GMR MRAM cell element that utilizes transfer of spin torque as a mechanism for changing the magnetization direction of a free layer. The critical current is reduced by constructing the free layer as a lamination comprising two... Agent: Saile Ackerman LLC

20100128521 - Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can... Agent: Himanshu S. Amin Amin, Turocy & Calvin, LLP

20100128525 - All-bit-line erase verify and soft program verify: Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with... Agent: Vierra Magen/sandisk Corporation

20100128528 - Memory cell programming: One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least... Agent: Brooks, Cameron & Huebsch , PLLC

20100128526 - Multi-level nonvolatile semiconductor memory: A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100128523 - Multi-pass programming in a memory device: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to... Agent: Leffert Jay & Polglaze, P.A.

20100128524 - Multi-phase programming of multi-level memory: Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages... Agent: Turocy & Watson, LLP

20100128529 - Nand step voltage switching method: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20100128527 - Nonvolatile memory device: A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the multi level data was written first, and a write time memory... Agent: Volentine & Whitt PLLC

20100128530 - Flash memory device and layout method of the flash memory device: Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second... Agent: Volentine & Whitt PLLC

20100128531 - Nonvolatile nand-type memory devices including charge storage layers connected to insulating layers: A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the... Agent: Myers Bigel Sibley & Sajovec

20100128532 - Nonvolatile memory device and programming method: A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a... Agent: Volentine & Whitt PLLC

20100128533 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device includes a plurality of strings each of which is configured with a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first and second select transistors. A common source line is connected to a source of the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100128534 - Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100128522 - Flash memory device and programming/erasing method of the same: A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell... Agent: Lee & Morse, P.C.

20100128535 - Semiconductor memory and method and system for actuating semiconductor memory: A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage... Agent: Arent Fox LLP

20100128536 - Memory cell, a memory array and a method of programming a memory cell: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100128537 - Method of programming a non-volatile memory: A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when... Agent: Freescale Semiconductor, Inc. Law Department

20100128541 - Integrated circuit having memory with configurable read/write operations and method therefor: An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first... Agent: Freescale Semiconductor, Inc. Law Department

20100128538 - Data receiving circuit: A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the... Agent: Ladas & Parry

20100128539 - Semiconductor memory: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.... Agent: Arent Fox LLP

20100128540 - Semiconductor memory apparatus and test circuit therefor: A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating... Agent: Ip & T Law Firm PLC

20100128542 - Reference clock and command word alignment: A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock... Agent: Silicon Edge Law Group, LLP

20100128543 - Latency circuit using division method related to cas latency and semiconductor memory device: A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The... Agent: Volentine & Whitt PLLC

20100128544 - Bit line bridge detecting method in semiconductor memory device: The method of detecting the bit line bridge in a semiconductor memory device includes enabling a sensing state for an even bit line connected to an even sense amplifier and an odd bit line connected to an odd sense amplifier, where the odd bit line is adjacent to the even... Agent: Harness, Dickey & Pierce, P.L.C

20100128546 - Embedded memory databus architecture: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20100128545 - Sense amplifier and semiconductor memory device using it: A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies... Agent: Harness, Dickey & Pierce, P.L.C

20100128548 - Semiconductor device and method of refreshing the same: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh... Agent: Sughrue Mion, PLLC

20100128547 - Semiconductor memory device and refresh control method of memory system: There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array (10) divided into a plurality of banks (0 to 3) each of which... Agent: Sughrue Mion, PLLC

20100128551 - Adjustable voltage regulator for providing a regulated output voltage: Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator circuit, a driver circuit, an impedance circuit, and a modulation circuit. The comparator circuit generates an output voltage according to a difference between a reference voltage and a... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100128552 - High-voltage sawtooth current driving circuit and memory device including same: A high-voltage sawtooth current driving circuit and a memory device including the same are described. In the high-voltage sawtooth current driving circuit includes a charge pump circuit configured to output a first voltage, a regulating circuit configured to regulate a second voltage using the first voltage output from the charge... Agent: Volentine & Whitt PLLC

20100128550 - Local power domains for memory sections of an array of memory: Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100128549 - Memory circuit having reduced power consumption: A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and... Agent: Ryan, Mason & Lewis, LLP

  
05/20/2010 > patent applications in patent subcategories. archived by USPTO category

20100124088 - Storage at m bits/cell density in n bits/cell analog memory cell devices, m>n: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells.... Agent: D. Kligler I.p. Services Ltd

20100124089 - Single-ended sense amplifier circuit: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense... Agent: Texas Instruments Incorporated

20100124090 - Semiconductor memory device and control method thereof: To provide data lines connected via column switches to a plurality of sense amplifiers and an input/output circuit that, in response to a write request, supplies pre-write data through the data line to selected phase change memory cells and then write data through the data line to the selected phase... Agent: Young & Thompson

20100124091 - Magnetic data storage device and method: A data storage device comprises an array of parallel magnetic nanowires each having a uniaxial anisotropy with an easy axis substantially perpendicular to the longitudinal axis of the nanowire and which is rotated about the longitudinal axis along the length of the nanowire, and a magnetisation state that follows the... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100124094 - Data holding device: A data holding device includes a loop structure portion for holding data by using a plurality of logic gates connected like a loop, and a nonvolatile storage portion for storing data held in the loop structure portion, in a nonvolatile manner by using a hysteresis characteristic of a ferroelectric element.... Agent: Fish & Richardson P.C.

20100124093 - Ferroelectric memory: A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines... Agent: Knobbe Martens Olson & Bear LLP

20100124092 - Ferroelectric memory device: According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line;... Agent: Knobbe Martens Olson & Bear LLP

20100124096 - Electric element, switching element, memory element, switching method and memory method: An electric element includes a pair of electrodes; and a plurality of carbon nanotubes of three-dimensional network structure which are located between the pair of electrodes. The electric element can be applied for a memory element and the like.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124095 - Floating source line architecture for non-volatile memory: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100124097 - Semiconductor storage device: Plural memory cell arrays laminated on the semiconductor substrate each includes a plurality of first wirings and second wirings formed to intersect with each other. The control circuit provides, in a non-selected second memory cell array that shares the first wiring with a selected first memory cell array, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124099 - 8t low leakage sram cell: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively,... Agent: K&l Gates LLPIPDocketing

20100124098 - Sram and forming method and controlling method thereof: An SRAM and a forming method and a controlling method thereof are provided. The above-mentioned SRAM includes a tracking column, a normal column, a cell voltage control circuit and a cell voltage pull-down circuit. Each of the tracking column and the normal column includes a plurality of memory cells. The... Agent: Jianq Chyun Intellectual Property Office

20100124100 - Device for controlling the activity of modules of an array of memory modules: A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20100124104 - Memory device and writing method thereof: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.... Agent: Mcginn Intellectual Property Law Group, PLLC

20100124102 - Phase-change and resistance-change random access memory devices and related methods of performing burst mode operations in such memory devices: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line... Agent: Myers Bigel Sibley & Sajovec

20100124101 - Phase-change random access memory device: Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change... Agent: Volentine & Whitt PLLC

20100124103 - Resistance-change random access memory device: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines... Agent: Lee & Morse, P.C.

20100124105 - Variable resistance memory device and system: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second... Agent: Volentine & Whitt PLLC

20100124106 - Magnetic memory with magnetic tunnel junction cell sets: A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell... Agent: Campbell Nelson Whipps, LLC

20100124111 - Nonvolatile semiconductor memory device and method for operating the same: A nonvolatile semiconductor memory device comprises: a memory cell array including a plurality of memory cell units each including memory cells, a plurality of bit lines, and a common source line; a sense amplifier operative to read data from a selected memory cell; a control circuit operative to control a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124112 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device includes a plurality of cells for storing data on a basis of charges stored nonvolatilly, a write unit for writing and erasing data on the cell by injecting or extracting charges into or from the cell, a comparator for comparing the voltage produced by a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100124108 - Programming methods and memories: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming... Agent: Leffert Jay & Polglaze, P.A.

20100124109 - Semiconductor memory device for storing multi level data: A memory cell array is configured so that a plurality of memory cells which are connected to a word line and a bit line store one value out of n values (n is a natural number of 2 or more) in one memory cell and are arranged in a matrix.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124113 - Semiconductor memory write method: A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124110 - Semiconductor storage device: A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124114 - Semiconductor device and layout method for the semiconductor device: Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality... Agent: Myers Bigel Sibley & Sajovec

20100124116 - Non-volatile semiconductor storage device: Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124117 - Nonvolatile semiconductor memory: A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124115 - Program and sense operations in a non-volatile memory device: Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page... Agent: Leffert Jay & Polglaze, P.A.

20100124118 - Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell nand flash array: A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A... Agent: Saile Ackerman LLC

20100124119 - Nonvolatile memory device and read methods thereof: n

20100124121 - Method of erasing flash memory device: In a method of erasing a flash memory device according to an aspect of this disclosure, an erase operation is performed to lower threshold voltages of memory cells to a voltage level less than a first voltage. A first soft program operation is performed until a threshold voltage of any... Agent: Ip & T Law Firm PLC

20100124122 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.... Agent: Ip & T Law Firm PLC

20100124120 - Nonvolatile memory device: A nonvolatile memory device includes; a memory cell array including a plurality of memory cells arranged in word lines and bit lines, a high-voltage generator generating a program voltage pulse applied to a selected word line among the word lines, and a pass voltage applied to a non-selected word line,... Agent: Volentine & Whitt PLLC

20100124124 - Nonvolatile memory device and method of programming the same: A nonvolatile memory device including a bit line voltage supply unit configured to supply a power source voltage, a second voltage in which a second reference voltage has been subtracted from a third reference voltage, or a third voltage in which a first reference voltage has been subtracted from the... Agent: Ip & T Law Firm PLC

20100124123 - Nonvolatile memory device with incremental step pulse programming: A nonvolatile memory device includes a sense amplifier circuit sensing first data from a memory cell via a bit line and outputting the sensed first data, in response to a read command. A write driver circuit programs the memory cell and stores second data indicating a programming state of the... Agent: F. Chau & Associates, LLC

20100124107 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a first plane and a second plane, an address decoder configured to decode an externally input address and to output a first plane select signal and a second plane select signal for enabling any one of the first and second planes, a controller configured to... Agent: Ip & T Law Firm PLC

20100124125 - Nonvolatile semiconductor memory device: A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator... Agent: Sughrue Mion, PLLC

20100124126 - Erase voltage reduction in a non-volatile memory device: In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification... Agent: Leffert Jay & Polglaze, P.A.

20100124128 - Nand flash memory: A NAND flash memory in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed via a first gate insulating film on a well formed on a semiconductor substrate and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124127 - Systems and methods for erasing a memory: Methods of erasing a memory, methods of operating a memory, memory devices, and systems are disclosed, for example. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing... Agent: Leffert Jay & Polglaze, P.A.

20100124129 - Data writing apparatus and method for semiconductor integrated circuit: A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually different timings, and a data writing unit configured to synchronize the first data and the second data having been transmitted... Agent: Ip & T Law Firm PLC

20100124131 - Delay adjustment device, semiconductor device and delay adjustment method: Provided is a delay adjustment device that contributes to downsizing the circuit that adjusts a flight time. The delay adjustment device is connected to a memory, and adjusts a timing to retrieve data with a data signal and a data strobe signal output from the memory. The delay adjustment device... Agent: Mcginn Intellectual Property Law Group, PLLC

20100124130 - Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface: A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits.... Agent: Coats & Bennett/qimonda

20100124132 - Replacing defective columns of memory cells in response to external addresses: Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells... Agent: Leffert Jay & Polglaze, P.A.

20100124133 - Replacing defective memory blocks in response to external addresses: Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks... Agent: Leffert Jay & Polglaze, P.A.

20100124134 - Semiconductor device: A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and... Agent: Mcginn Intellectual Property Law Group, PLLC

20100124135 - Semiconductor memory devices having hierarchical bit-line structures: The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines.... Agent: Harness, Dickey & Pierce, P.L.C

20100124136 - Temperature compensation circuit and method for sensing memory: A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100124137 - Voltage-controlled oscillator, phase-locked loop, and memory device: A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in response to a control voltage. The plurality of intermediate clock signals... Agent: Volentine & Whitt PLLC

20100124138 - Semiconductor memory device having variable-mode refresh operation: A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array... Agent: Lee & Morse, P.C.

20100124139 - Semiconductor device including an anti-fuse element: A semiconductor device includes a first high potential power supply, a second low potential power supply, a third power supply having a potential higher than the first, a fourth power supply having a potential more negative than the second, and an anti-fuse element having a node at each end, one... Agent: Morrison & Foerster LLP

20100124140 - Power supply circuit and nand-type flash memory: A power supply circuit has a control circuit. The control circuit outputs a control clock signal so as to cause a first booster circuit to compulsorily perform boosting operation with a first boosting capability in response to an output signal of a second comparison amplifier after a lapse of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100124141 - Semiconductor memory device of dual-port type: To provide a plurality of DRAM cells, a plurality of sense amplifiers connected to corresponding bit line pairs, a first column switch and a second column switch assigned to each of the sense amplifiers, data lines connected via the column switches to the sense amplifiers, a first port PORT1 and... Agent: Young & Thompson

  
05/13/2010 > patent applications in patent subcategories. archived by USPTO category

20100118581 - Magnetic memory device: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of... Agent: Mcdermott Will & Emery LLP

20100118579 - Nand based resistive sense memory cell architecture: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118580 - Semiconductor memory device: A semiconductor memory device includes first positive and negative data lines driven with voltage levels contrary to each other in response to first data and second positive and negative data lines driven with voltage levels contrary to each other in response to second data, wherein one of the second positive... Agent: Ip & T Law Firm PLC

20100118582 - Memory module and memory system having the same: A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to... Agent: Volentine & Whitt PLLC

20100118583 - Magetic shift register and data accessing method: A magnetic shift register memory includes at least a magnetic memory track, in which multiple domain walls separate the memory track into multiple magnetic domains to serve as magnetic memory cells. A fixed number of the magnetic memory cells forms a memory unit to store a burst data. A read/write... Agent: Jianq Chyun Intellectual Property Office

20100118584 - Memory device using antifuses: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native... Agent: Mcandrews Held & Malloy, Ltd

20100118585 - High density spin torque three dimensional (3d) memory arrays addressed with microwave current: One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each... Agent: Ipxlaw Group LLP

20100118586 - Ferroelectric memory: A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first... Agent: Knobbe Martens Olson & Bear LLP

20100118590 - Bidirectional non-volatile memory array architecture: A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118594 - Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is... Agent: Dickstein Shapiro LLP

20100118589 - Non-volatile memory cell with multiple resistive sense elements sharing a common switching device: A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118592 - Nonvolatile semiconductor memory device and method of controlling the same: Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device comprises: a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix;... Agent: Nixon & Vanderhye, PC

20100118595 - Resistance variable memory devices and read methods thereof: A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source.... Agent: Volentine & Whitt PLLC

20100118587 - Resistive sense memory array with partial block update capability: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118591 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: an oxide resistance change element, a constant current source circuit supplying a write current to the oxide resistance change element, and a voltage clamper clamping a voltage in a path in which a write current flows. The voltage clamper is arranged in parallel with the... Agent: Mr. Jackson Chen

20100118593 - Variable resistance memory device and system thereof: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit... Agent: Volentine & Whitt PLLC

20100118588 - Voltage reference generation for resistive sense memory cells: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118596 - Embedded dram with bias-independent capacitance: An embedded memory system that includes DRAM cells and logic transistors. The capacitor of the embedded memory responds to a positive bias voltage of ½ Vdd. The wordline driver of a p-channel access transistor applying the positive power supply voltage when the p-channel access FET is not being accessed and... Agent: Mosys Incorporated Patent Counsel

20100118597 - Multiple valued dynamic random access memory cell and thereof array using single electron transistor: Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of... Agent: Demont & Breyer, LLC

20100118598 - Phosphonium ionic liquids, compositions, methods of making and electronic devices formed there from: The invention generally encompasses phosphonium ionic liquids and compositions and their use in many applications, including but not limited to: as electrolytes in electronic devices such as memory devices including static, permanent and dynamic random access memory, as battery electrolytes, as a heat transfer medium, fuel cells and electrochromatic devices,... Agent: Morgan, Lewis & Bockius, LLP. (pa)

20100118599 - Process for forming both split gate and common gate finfet transistors and integrated circuits therefrom: A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at... Agent: Texas Instruments Incorporated

20100118600 - Magnetoresistive element: A magnetoresistive element which records information by supplying spin-polarized electrons to a magnetic material, includes a first pinned layer which is made of a magnetic material and has a first magnetization directed in a direction perpendicular to a film surface, a free layer which is made of a magnetic material... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100118601 - Phase change random access memory device: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current... Agent: Volentine & Whitt PLLC

20100118603 - Device and method of programming a magnetic memory element: The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional... Agent: Haynes And Boone, LLPIPSection

20100118602 - Double source line-based memory array and memory cells thereof: A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions,... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100118604 - Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control: A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100118606 - Methods of programming non-volatile memory devices and memory devices programmed thereby: In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of... Agent: Mills & Onello LLP

20100118607 - Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20100118605 - Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells: A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100118608 - Non-volatile memory device, memory card and system, and method determining read voltage in same: A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a... Agent: Volentine & Whitt PLLC

20100118610 - Nonvolatile semiconductor memory device: A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetrating through the select gate electrodes and the control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100118609 - Nonvolatile semiconductor memory, and method for reading data: A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100118611 - Delayed activation of selected wordlines in memory: Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.... Agent: Schwegman, Lundberg & Woessner/micron

20100118612 - Semiconductor memory device and read access method thereof: The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access.... Agent: Sughrue Mion, PLLC

20100118613 - Method of erasing data in flash memory device: A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory... Agent: Harness, Dickey & Pierce, P.L.C

20100118614 - Semiconductor apparatus, data write circuit of semiconductor apparatus, and method of controlling data write circuit: A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals... Agent: Ladas & Parry LLP

20100118615 - Semiconductor memory device: A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line... Agent: Mills & Onello LLP

20100118616 - Semiconductor memory device: A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a... Agent: Harness, Dickey & Pierce, P.L.C

20100118617 - Memories with improved write current: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric... Agent: Quintero Law Office, PC

20100118619 - Buffer circuit of semiconductor memory apparatus: A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and... Agent: Venable LLP

20100118620 - Semiconductor device: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored... Agent: Cook Alex Ltd

20100118618 - Semiconductor integrated circuit with data bus inversion function: A semiconductor integrated circuit includes a data bus inversion (DBI) flag generating unit to generate DBI flag signals using a plurality of output data sets, a data inverting unit to invert the plurality of output data sets according to the DBI flag signals and transmit the plurality of output data... Agent: Ladas & Parry LLP

20100118621 - Implementing variation tolerant memory array signal timing: A method and signal timing adjustment circuit for implementing variation tolerant memory array signal timing, and a design structure on which the subject circuit resides are provided. A logic circuit generates a first delay signal based upon logic devices forming the logic circuit. A memory cell circuit receives the first... Agent: Ibm Corporation RochesterIPLaw Dept 917

20100118622 - 1-transistor type dram cell, a dram device and manufacturing method therefore, driving circuit for dram, and driving method therefor: The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing... Agent: Ladas & Parry LLP

20100118623 - Method of operating semiconductor devices: A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device.... Agent: Harness, Dickey & Pierce, P.L.C

20100118624 - Read circuit for semiconductor memory device and semiconductor memory device: Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20100118625 - Charge pump circuit and semiconductor memory device including the same: A charge pump circuit includes a first charge pump unit that includes a first capacitor and a second capacitor connected in parallel and generates a first charge pump voltage in the second capacitor by pumping the first capacitor, and a second charge pump unit that includes a third capacitor connected... Agent: Sughrue Mion, PLLC

20100118626 - Delay device for shifting phase of strobe signal: A delay apparatus includes a DLL circuit including a delay element, the DLL circuit generating a first control signal for controlling the delay element in order that the delay element delays a reference clock inputted into the delay element by one cycle, and a strobe delay element having a configuration... Agent: Mcginn Intellectual Property Law Group, PLLC

20100118627 - Strobe-offset control circuit: A strobe offset control circuit is disclosed. The control circuit comprises a strobe signal input to receive a strobe signal and a data receiver to receive a data signal in response to a sample signal derived from the strobe signal. A calibration enable input is provided to receive a calibration... Agent: Mahamedi Paradice Kreisman LLP

20100118629 - Apparatus for controlling i/o strobe signal in semiconductor memory apparatus: A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating... Agent: Ladas & Parry LLP

20100118628 - Memory circuit and tracking circuit thereof: The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100118630 - Method and apparatus for synchronizing data from memory arrays: According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps.... Agent: Jones Day

20100118631 - Semiconductor memory devices with mismatch cells: A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be... Agent: Harness, Dickey & Pierce, P.L.C

20100118632 - Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof: Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100118633 - Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same: A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in... Agent: Marger Johnson & Mccollom, P.C.

20100118634 - Semiconductor apparatuses and methods of operating the same: A method of operating a semiconductor device is provided including applying a constant source voltage to a source line.... Agent: Harness, Dickey & Pierce, P.L.C

20100118635 - Semiconductor memory device and method for operating the same: A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected.... Agent: Ip & T Law Firm PLC

20100118636 - Methods and systems involving electrically reprogrammable fuses: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the... Agent: Cantor Colburn LLP - IBM Fishkill

20100118637 - Circuts and methods for reducing minimum supply for register file cells: A register file employing a shared supply structure to improve the minimum supply voltage.... Agent: Intel Corporation C/o Cpa Global

20100118638 - Semiconductor memory apparatus having decreased leakage current: A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal... Agent: Ladas & Parry LLP

20100118639 - Semiconductor memory apparatus: A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference... Agent: Venable LLP

  
05/06/2010 > patent applications in patent subcategories. archived by USPTO category

20100110744 - Ternary content addressable magnetoresistive random access memory cell: A method for writing a magnetic random access memory-based ternary content addressable memory cell comprising a first magnetic tunnel junction being formed from a storage layer, a sense layer having a magnetization direction adjustable relative to the magnetization of the storage layer, and an insulating layer between the storage and... Agent: Pearne & Gordon LLP

20100110748 - Hybrid volatile and non-volatile memory device: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed... Agent: Mahamedi Paradice Kreisman LLP

20100110746 - Memory cell with alignment structure: A memory cell that includes a memory element configured for switching from a first data state to a second data state by passage of current therethrough. The memory cell includes a top electrode and a bottom electrode for providing the current through the memory cell, and an alignment element positioned... Agent: Campbell Nelson Whipps, LLC

20100110747 - Semiconductor memory device: The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality... Agent: Solaris Intellectual Property Group, PLLC

20100110745 - Switched interface stacked-die memory architecture: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory... Agent: Schwegman, Lundberg & Woessner/micron

20100110749 - Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads: A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad... Agent: Lee & Morse, P.C.

20100110750 - Non-volatile semiconductor memory device: s

20100110751 - Semiconductor storage device: In a configuration having a nonvolatile memory and a volatile memory, when storage information of the nonvolatile memory is changed and an abnormal operation occurs due to temporary blackout, α-ray or others, the abnormal operation is recovered to a normal operation regardless of the presence of the detection of the... Agent: Miles & Stockbridge PC

20100110752 - Method of making a diode read/write memory cell in a programmed state: A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20100110753 - Ferroelectric memory cell arrays and method of operating the same: An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load... Agent: Edell, Shapiro & Finnan, LLC

20100110755 - Ferroelectric random access memory device: A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric... Agent: Knobbe Martens Olson & Bear LLP

20100110754 - Non-destructive read back for ferroelectric data storage device: A data storage device comprising a ferroelectric layer, a perovskite structure, and at least one sensor, where the perovskite structure has a polarity discontinuity configured to generate capacitance voltages in the perovskite structure based on polarization charges of the ferroelectric material, and where the at least one sensor is configured... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.

20100110769 - Controlling a variable resistive memory wordline switch: A method of controlling the voltage of a sub-wordline in a variable resistive memory device includes switchably passing a voltage from a main wordline to the sub-wordline, and substantially blocking forward current flow from the sub-wordline to a variable resistive memory cell of the device.... Agent: F. Chau & Associates, LLC

20100110765 - Non-volatile memory cell with programmable unipolar switching element: A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100110766 - Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus: A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and... Agent: Mcdermott Will & Emery LLP

20100110764 - Programmable metallization cell switch and memory units containing the same: An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer... Agent: Campbell Nelson Whipps, LLC

20100110759 - Programmable resistive memory cell with filament placement structure: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has... Agent: Campbell Nelson Whipps, LLC

20100110767 - Resistance variable memory apparatus: A resistance variable memory apparatus (10) of the present invention comprises a resistance variable element (1) which is switched to a high-resistance state when a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller (4), a voltage restricting... Agent: Mcdermott Will & Emery LLP

20100110768 - Resistance variable memory device and system: Disclosed is a resistance variable memory device including a memory cell connected with a bit line, a sense amplifier circuit sensing a voltage level on the bit line, and a pseudo-replica providing the sense amplifier circuit with a control signal that compensates for a drop in the sensing capacity of... Agent: Volentine & Whitt PLLC

20100110757 - Resistive memory: The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch... Agent: Brooks, Cameron & Huebsch , PLLC

20100110760 - Resistive sense memory calibration for self-reference read method: Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory... Agent: Campbell Nelson Whipps, LLC

20100110761 - Spatial correlation of reference cells in resistive memory array: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory... Agent: Campbell Nelson Whipps, LLC

20100110758 - Structures for resistive random access memory cells: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side... Agent: Campbell Nelson Whipps, LLC

20100110770 - Variable resistance memory devices including arrays of different sizes: A variable resistance memory device may include a first array of first variable resistance memory cells and a second array of second variable resistance memory cells on an integrated circuit chip. Each of the first variable resistance memory cells may be configured to store a first data value by maintaining... Agent: Myers Bigel Sibley & Sajovec

20100110771 - Variable resistive memory: A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of... Agent: F. Chau & Associates, LLC

20100110756 - Variable resistive memory punchthrough access method: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor... Agent: Campbell Nelson Whipps, LLC

20100110763 - Write current compensation using word line boosting circuitry: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device,... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100110762 - Write method with voltage line tuning: A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration... Agent: Campbell Nelson Whipps, LLC

20100110772 - Semiconductor memory device having bit line disturbance preventing unit: A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit... Agent: Harness, Dickey & Pierce, P.L.C

20100110773 - Sram cell without dedicated access transistors: A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least... Agent: Gowling Lafleur Henderson LLP

20100110774 - Sram device: An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a... Agent: Ostrolenk Faber Gerb & Soffen

20100110776 - Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller... Agent: Qualcomm Incorporated

20100110777 - Magnetic random access memory: An MRAM according to the present invention has a magnetoresistance element 1. The magnetoresistance element 1 has: a first magnetic layer 10 including a first region 11 whose magnetization direction is reversible; a second magnetic layer 30 whose magnetization direction is fixed parallel to a magnetization easy axis direction of... Agent: Mr. Jackson Chen

20100110775 - Word line voltage control in stt-mram: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit... Agent: Qualcomm Incorporated

20100110779 - Multilevel phase change memory operation: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change... Agent: Brooks, Cameron & Huebsch , PLLC

20100110782 - Page mode access for non-volatile memory arrays: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry... Agent: Kevin L. Bray Ovonyx, Inc.

20100110781 - Phase change memory device generating program current and method thereof: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of... Agent: Harness, Dickey & Pierce, P.L.C

20100110778 - Phase change memory program method without over-reset: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100110780 - Programmable resistance memory: A minimal-duration current pulse is employed to program a programmable resistance memory to a high-resistance, RESET state. Although the duration and magnitude of RESET programming pulses in accordance with the principles of the present invention may vary depending, for example, upon the composition and structure of a cell, a method... Agent: Ovonyx, Inc

20100110785 - Memory cell with proportional current self-reference sensing: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)

20100110783 - Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling: A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be... Agent: Fletcher Yoder (micron Technology, Inc.)

20100110784 - Stram with self-reference read scheme: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the... Agent: Campbell Nelson Whipps, LLC

20100110788 - Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array: Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100110787 - Memory cell readout using successive approximation: A method for operating a memory (20) includes storing analog values in an array of analog memory cells (22), so that each of the analog memory cells holds an analog value corresponding to at least first and second respective bits. A first indication of the analog value stored in a... Agent: Darby & Darby P.C.

20100110789 - Memory device biasing method and apparatus: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines... Agent: Leffert Jay & Polglaze, P.A.

20100110790 - Semiconductor memory device: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20100110791 - Eeprom memory protected against the effects of breakdown of mos transistors: The disclosure relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines transverse to bit lines, wherein each memory cell may be in a programmed or erased state, the memory comprising memory cell selection circuits configured to memorize and read data bits... Agent: Seed Intellectual Property Law Group PLLC

20100110792 - Pair bit line programming to improve boost voltage clamping: A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming... Agent: Vierra Magen/sandisk Corporation

20100110793 - Flash memory device and memory system including the same: Provided is a flash memory device. The flash memory device includes a memory cell array, and a voltage generator. The memory cell array is connected to a plurality of word lines. The voltage generator generates a program voltage which is supplied to a selected word line of the word lines... Agent: Myers Bigel Sibley & Sajovec

20100110794 - Non-volatile semiconductor memory having multiple external power supplies: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20100110795 - Boosting seed voltage for a memory device: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice.... Agent: Cool Patent, P.C. C/o Cpa Global

20100110797 - Method and apparatus for programming flash memory: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.... Agent: Dickstein Shapiro LLP

20100110796 - Method of performing erase operation in non-volatile memory device: A method of performing an erase operation in a non-volatile memory device includes a multi-erase operation and a post-erase operation. The multi-erase operation includes multi-erasing multiple memory blocks at the same time using a multi-erase voltage. The post-erase operation includes post-erasing one or more failed memory blocks of the multi-erased... Agent: Volentine & Whitt PLLC

20100110786 - Nonvolatile memory device, memory system including the same, and memory test system: Provided are a nonvolatile memory device and a memory test system. The nonvolatile memory device includes a temperature compensator to calculate a trim value for regulating a characteristic of the nonvolatile memory device that varies with temperature in response to a test signal. The memory test system includes a plurality... Agent: Harness, Dickey & Pierce, P.L.C

20100110798 - Program window adjust for memory cell signal line delay: A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal... Agent: Leffert Jay & Polglaze, P.A.

20100110799 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100110800 - Data output circuit and method: A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same... Agent: Ip & T Law Firm PLC

20100110801 - Semiconductor device: A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of... Agent: Ip & T Law Firm PLC

20100110802 - Semiconductor device: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.... Agent: Sughrue Mion, PLLC

20100110803 - Semiconductor memory device that can perform successive accesses: To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includes a write buffer that... Agent: Sughrue Mion, PLLC

20100110804 - Method for reading and writing a block interleaver and the reading circuit thereof: A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20100110805 - Semiconductor memory device: A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a... Agent: Ip & T Law Firm PLC

20100110807 - Bitline leakage detection in memories: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.... Agent: Texas Instruments Incorporated

20100110806 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks, each configured to receive a bank operation control signal and perform predetermined operations in response to the received bank operation control signal, a plurality of bank control blocks, each configured to receive a bank sequential signal and generate the plurality of... Agent: Ip & T Law Firm PLC

20100110808 - Semiconductor memory device and control method thereof: A semiconductor memory device according to the present invention includes: a memory cell array having a normal memory cell and a redundant memory cell that is used to replace the normal memory cell when it is defective; a word driver selecting a predetermined word line within the memory cell array... Agent: Mcginn Intellectual Property Law Group, PLLC

20100110810 - Semiconductor memory device and system: A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals, and a refresh-target selecting circuit configured to successively... Agent: Arent Fox LLP

20100110809 - Semiconductor memory device and system with redundant element: A semiconductor memory device includes a memory cell array, a redundant element, an address specifying circuit configured to select one of a plurality of addresses as a redundancy address in response to a switchover signal, a decoder circuit configured to select the redundant element in response to an externally applied... Agent: Arent Fox LLP

20100110812 - Semiconductor device: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a... Agent: Sughrue Mion, PLLC

20100110811 - Semiconductor memory device: A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second... Agent: Ip & T Law Firm PLC

20100110813 - Precharge control circuits and methods for memory having buffered write commands: Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100110814 - Semiconductor memory device and semiconductor memory device operation method: Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch... Agent: Foley And Lardner LLP Suite 500

20100110815 - Non-volatile memory device having temperature compensator and memory system thereof: Provided is a semiconductor memory device. The semiconductor memory device includes: a voltage generator adjusting a DC voltage supplied into the semiconductor memory device according to a current temperature; and a control logic activating a temperature detection operation of the voltage generator and an adjustment operation of the DC voltage... Agent: Myers Bigel Sibley & Sajovec

20100110818 - Semiconductor device: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a... Agent: Arent Fox LLP

20100110817 - Semiconductor device and refreshing method: A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line selected by a row address that... Agent: Mcginn Intellectual Property Law Group, PLLC

20100110816 - Techniques for block refreshing a semiconductor memory device: Techniques for block refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for block refreshing a semiconductor memory device. The method may comprise arranging a plurality of memory cells in one or more arrays of rows and columns. Each... Agent: Hunton & Williams LLP Intellectual Property Department

20100110819 - Apparatus and method for placement of boosting cell with adaptive booster scheme: A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage... Agent: Darby/spansion C/o Darby & Darby P.C.

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