|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
04/2010 | Recent | 14: Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval April category listing, related patent applications 04/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/29/2010 > patent applications in patent subcategories. category listing, related patent applications
20100103712 - Memory test device and methods thereof: In accordance with a specific embodiment of the present disclosure, a content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches... Agent: Larson Newman & Abel, LLP
20100103713 - Adjustable width strobe interface: A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion... Agent: Rambus Lerner, David, Et Al.
20100103714 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100103715 - Semiconductor storage device and method of operating the same: A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit... Agent: Knobbe Martens Olson & Bear LLP
20100103716 - Non-volatile memory with metal-polymer bi-layer: A resistive memory cell that includes a metal-polymer bi-layer proximate a CMOS gate. The memory cell has a substrate having a source contact connected to a source line and a drain contact connected to a drain line, a CMOS gate proximate the substrate electrically connecting the source contact and the... Agent: Campbell Nelson Whipps, LLC
20100103718 - Semiconductor memory device: A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed... Agent: Knobbe Martens Olson & Bear LLP
20100103717 - Tuning a variable resistance of a resistive sense element: Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100103719 - Two-stage 8t sram cell design: An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to... Agent: Slater & Matsil, L.L.P.
20100103720 - Biosensor and sensing cell array using the same: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel... Agent: Townsend And Townsend And Crew, LLP
20100103721 - Heater and memory cell, memory device and recording head including the heater: A heater includes at least two leads, and a heating element which is formed between the at least two leads, a material of the heating element being different from a material of the at least two leads such that a location of a hot spot in the heater is controllable... Agent: Mcginn Intellectual Property Law Group, PLLC
20100103722 - Method of programming resistivity changing memory: A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing... Agent: Dicke, Billig & Czaja
20100103723 - Nonvolatile memory apparatus: Provided are a plurality of memory cell arrays 136 and 146 each having a plurality of nonvolatile memory elements having a characteristic whose resistance value changes according to electric pulses applied, and control units (102, 104, 108, 110, 114, 128, 130, 152) configured to write data to a memory cell... Agent: Mcdermott Will & Emery LLP
20100103726 - Phase change memory devices and systems, and related programming methods: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether... Agent: Volentine & Whitt PLLC
20100103725 - Resistance variable memory device for protecting coupling noise: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response... Agent: Myers Bigel Sibley & Sajovec
20100103724 - Variable resistance memory device: The variable resistance memory device may include a memory cell array including a plurality of memory blocks, a bit line selection circuit including a plurality of bit lines connected to the plurality of memory blocks, at least one readout Y-pass driver configured to control a connection of the bit line... Agent: Harness, Dickey & Pierce, P.L.C
20100103728 - Spin-transfer torque memory self-reference read and write assist methods: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit... Agent: Campbell Nelson Whipps, LLC
20100103729 - Spin-transfer torque memory self-reference read and write assist methods: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit... Agent: Campbell Nelson Whipps, LLC
20100103727 - St-ram employing a magnetic resonant tunneling diode as a spacer layer: A memory cell that includes a first magnetic layer, the magnetization of which is free to rotate under the influence of spin torque; a tunneling layer comprising a magnetic resonant tunneling diode (MRTD); and a second magnetic layer, wherein the magnetization of the second magnetic layer is pinned, wherein the... Agent: Campbell Nelson Whipps, LLC
20100103730 - Magnetic memory cell: The present invention relates to a magnetic memory cell, which controls the magnetization direction of the free magnetic layer of a Magnetic Tunnel Junction (MTJ) device using a spin torque transfer, and enables the implementation of a magnetic logic circuit, in which memory and logic circuit functions are integrated. The... Agent: Lahive & Cockfield, LLP Floor 30, Suite 3000
20100103732 - Controlling ac disturbance while programming: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate... Agent: Turocy & Watson, LLP
20100103731 - Method analyzing threshold voltage distribution in nonvolatile memory: A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read... Agent: Volentine & Whitt PLLC
20100103735 - Memory device and program method thereof: Provided are a flash memory system and a driving method thereof. A flash memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, and a control logic. The control logic performs control for one-bit information to be stored in... Agent: Harness, Dickey & Pierce, P.L.C
20100103734 - Programming non-volatile memory with high resolution variable initial programming pulse: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a... Agent: Vierra Magen/sandisk Corporation
20100103733 - Programming non-volatile memory with variable initial programming pulse: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse... Agent: Vierra Magen/sandisk Corporation
20100103736 - Nonvolatile semiconductor memory having a word line bent towards a select gate line side: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100103737 - Read compensation circuits and apparatus using same: A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to... Agent: Myers Bigel Sibley & Sajovec
20100103738 - Memory and operating method thereof: A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100103739 - Memory configuration of a composite memory device: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite... Agent: Cooper & Dunham, LLP
20100103740 - Nonvolatile memory device, methods of programming the nonvolatile memory device and memory system including the same: A nonvolatile memory device is provided. A counter counts an amount of data to be program-inhibited among data to be written to memory cells to provide a first count value. The counter also counts an amount of program-inhibited data among data written to the memory cells to provide a second... Agent: F. Chau & Associates, LLC
20100103741 - Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100103742 - Method of operating nonvolatile memory device and memory system: A method of operating a nonvolatile memory device includes; performing a verification operation on memory cells while controlling a verification voltage until the memory cells are verification-passed, controlling a level of a bias voltage to be applied to the memory cells according to a level of the verification voltage when... Agent: Volentine & Whitt PLLC
20100103743 - Flash memory device and method of testing the flash memory device: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers.... Agent: Harness, Dickey & Pierce, P.L.C
20100103744 - Non-volatile memory device and method of driving the same: A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of... Agent: Lee & Morse, P.C.
20100103745 - Nand flash memory with a programming voltage held dynamically in a nand chain channel region: Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100103750 - Antifuse replacement determination circuit and method of semiconductor memory device: An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge... Agent: Sughrue Mion, PLLC
20100103748 - Clock path control circuit and semiconductor memory device using the same: A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in... Agent: Ip & T Law Firm PLC
20100103747 - Memory device and method of operating such a memory device: A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of... Agent: Nixon & Vanderhye P.C.
20100103746 - Multi-phase duty-cycle corrected clock signal generator and memory having same: Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100103749 - Semiconductor memory device: A semiconductor memory device includes a memory cell region including memory cells that store data. An input buffer is disposed on one side of the memory cell region. On the other hand, an output buffer is disposed on another side opposite to the input buffer in the memory cell region.... Agent: Young & Thompson
20100103751 - Circuit with a memory array and a reference level generator circuit: A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100103752 - Semiconductor memory device and method for reading/writing data thereof: A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100103754 - Circuit, system and method for controlling read latency: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100103753 - Data detecting apparatus and methods thereof: A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100103755 - Read assist for memory circuits: A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines... Agent: Qualcomm Incorporated
20100103756 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch... Agent: Sughrue Mion, PLLC
20100103757 - Semiconductor device: A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a... Agent: Foley And Lardner LLP Suite 500
20100103758 - Semiconductor memory device having sense amplifier: To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance... Agent: Mcginn Intellectual Property Law Group, PLLC
20100103759 - Power line decoding method for an memory array: A method for selectively providing power supply voltage to a memory device. The method provides an integrated circuit memory device including a first plurality of memory cells. Each memory cell includes a power terminal and a ground terminal. The method includes selecting a second plurality of memory cells from the... Agent: Townsend And Townsend And Crew, LLP
20100103760 - Memory power management systems and methods: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an... Agent: Texas Instruments Incorporated
20100103761 - Memory devices having redundant arrays for repair: Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data... Agent: Knobbe Martens Olson & Bear LLP
20100103762 - Memory device and method: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.... Agent: Cypress Semiconductor Corporation04/22/2010 > patent applications in patent subcategories. category listing, related patent applications
20100097831 - Iterative serial content addressable memory: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also... Agent: Connolly Bove Lodge & Hutz LLP
20100097832 - Nonvolatile semiconductor memory device: A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100097833 - Phase change memory device: A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block... Agent: Ladas & Parry LLP
20100097834 - Tree-structure memory device: A tree-structure memory device including a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction, a plurality of layers having a plurality of memory cells arranged in a first array, a... Agent: Hitachi C/o Wagner Blecher LLP
20100097835 - 4 f2 memory cell array: An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one... Agent: Edell, Shapiro & Finnan, LLC
20100097836 - Memory bitcell and method of using the same: A memory bitcell comprises first (102) and second (103) transistors and a cantilever module (104) having two states. The first transistor (102) is arranged to communicate a first signal to the input of the cantilever module (104) upon receipt of a second signal. The second transistor (103) is arranged to... Agent: Roland Tso Cavendish Kinetics Patent Dept.
20100097837 - Memory based computation systems and methods of using the same: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be... Agent: Attn: Stephen B. Parker (wpd) Westerman, Hattori, Daniels & Adrian, LLP
20100097838 - Optical sensor element, imaging device, electronic equipment and memory element: An optical sensor element has a gate electrode opposed to a semiconductor layer made of an oxide semiconductor via a gate insulating film, source and drain electrodes being connected to the semiconductor layer, wherein the amount of light received by the semiconductor layer is read out as a drain current... Agent: K&l Gates LLP
20100097840 - Fram including a tunable gain amp as a local sense amp: FRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a ferroelectric capacitor, and gain is adjusted by setting a local amp voltage for reading the... Agent: Juhan Kim
20100097839 - High speed ferroelectric random access memory: For realizing high speed ferroelectric random access memory, bit line is multi-divided for reducing parasitic capacitance, so that the bit line is quickly charged or discharged by a memory cell including a ferroelectric capacitor when reading. Particularly, a non-inverting local sense amp is devised for reducing area, such that the... Agent: Juhan Kim
20100097843 - Extraction of a binary code based on physical parameters of an integrated circuit: An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100097841 - Multi-stage parallel data transfer: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100097842 - Resistance variable memory device programming multi-bit data: A phase change memory device is provided to simultaneously program multi-bit data. The phase change memory device includes a memory cell array in which multi-bit data is stored, a buffer circuit storing a lower bit and an upper bit of the multi-bit data, a write driver applying program current to... Agent: Volentine & Whitt PLLC
20100097844 - Write-assist sram cell: An integrated circuit structure includes a word-line; a column select line; and a latch. The latch includes a first storage node and a second storage node complementary to each other; and an operation voltage node. A control circuit is coupled between the operation voltage node and the latch. The control... Agent: Slater & Matsil, L.L.P.
20100097847 - Information storage element and method of writing/reading information into/from information storage element: An information storage element includes a strip-shaped ferromagnetic material layer; a first electrode disposed at a first end of the ferromagnetic material layer; and a second electrode disposed at a second end of the ferromagnetic material layer, wherein a current-induced domain wall motion is caused by applying a current between... Agent: Rader Fishman & Grauer PLLC
20100097848 - Information storage element and method of writing/reading information into/from information storage element: In a method of writing information into and reading information from an information storage element which includes a strip-shaped ferromagnetic material layer, a first electrode disposed at an end of the ferromagnetic material layer, a second electrode disposed at another end of the ferromagnetic material layer, and an antiferromagnetic region... Agent: Rader Fishman & Grauer PLLC
20100097846 - Magnetoresistive element and magnetic memory: A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an... Agent: Knobbe Martens Olson & Bear LLP
20100097845 - Semiconductor storage device: A semiconductor storage device is provided with a memory array including a plurality of memory cells. The plurality of memory cells includes: first and third memory cells arranged along one of an even-numbered row and an odd-numbered row, and a second memory cell arranged along the other. Each of the... Agent: Mr. Jackson Chen
20100097850 - Apparatus and systems using phase change memories: Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver... Agent: Myers Bigel Sibley & Sajovec
20100097851 - Method for programming a multilevel phase change memory device: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at... Agent: Stout, Uxa, Buyan & Mullins LLP
20100097849 - Variable resistance memory device performing program and verification operation: A variable resistance memory device includes; a memory cell array comprising a plurality of memory cells, a pulse shifter shifting a plurality of program pulses to generate a plurality of shifted program pulses, a write and verification driver receiving the plurality of shifted program pulses to provide a program current... Agent: Volentine & Whitt PLLC
20100097852 - Mram diode array and access method: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel... Agent: Campbell Nelson Whipps, LLC
20100097853 - Jeet memory cell: A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction field effect transistor (602) having a second conductivity type is coupled... Agent: Robert N. Rountree
20100097854 - Flash memory and flash memory array: A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along... Agent: Jianq Chyun Intellectual Property Office
20100097856 - Flash memory and associated methods: In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the... Agent: Schwegman, Lundberg & Woessner/intel
20100097855 - Non-volatilization semiconductor memory and the write-in method thereof: Means for Solving the Problems: In a non-volatile semiconductor memory device, comprising: a non-volatile memory array, which stores multi-valued states by setting a plurality of different threshold voltages to correspond to a plurality of states to each memory cell; and a control circuit, which controls programming to the memory cell... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100097857 - Predictive programming in non-volatile memory: In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100097859 - Nonvolatile memory device: A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting... Agent: Mills & Onello LLP
20100097858 - Three-dimensionally stacked nonvolatile semiconductor memory: A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100097860 - Nand flash memory: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100097862 - Flash memory devices with memory cells strings including dummy transistors with selective threshold voltages: Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and... Agent: Myers Bigel Sibley & Sajovec
20100097861 - Multi-pass programming for memory using word line coupling: A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass... Agent: Vierra Magen/sandisk Corporation
20100097863 - Method of programming non-volatile memory device and non-volatile memory device using the same: A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected... Agent: Harness, Dickey & Pierce, P.L.C
20100097864 - Semiconductor memory system including a plurality of semiconductor memory devices: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100097865 - Data transmission circuit and a semiconductor integrated circuit using the same: A data transmission circuit includes a data input unit configured to latch data in response to a data strobe signal and to output the data as input data, and a data input timing control unit configured to latch the input data in response to the data strobe signal delayed for... Agent: Baker & Mckenzie LLP Patent Department
20100097867 - Internal source voltage generating circuit of semiconductor memory device: An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a... Agent: Volentine & Whitt PLLC
20100097866 - Semiconductor memory device: A semiconductor memory device includes a memory cell array provided with a main memory cell array including a plurality of memory cells, and a dummy column including a plurality of dummy memory cells, a dummy readout current control section configured to control a current value of a dummy readout current... Agent: Turocy & Watson, LLP
20100097868 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line... Agent: Schwegman, Lundberg & Woessner/micron
20100097869 - Memory system having incorrupted strobe signals: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input,... Agent: Mosaid Technologies Incorporated
20100097870 - Semiconductor memory device for controlling operation of delay-locked loop circuit: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked... Agent: F. Chau & Associates, LLC
20100097871 - Redundant memory array for replacing memory sections of main memory: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100097872 - Wafer test trigger signal generating circuit of a semiconductor memory apparatus, and a wafer test circuit using the same: A wafer test trigger signal generating circuit of a semiconductor memory apparatus includes an enable timing control unit configured to generate an enable signal by using a plurality of address signals, and a trigger signal generating unit configured to generate a test trigger signal, which designates a decoding timing of... Agent: Baker & Mckenzie LLP Patent Department
20100097873 - Latch structure and bit line sense amplifier structure including the same: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter.... Agent: Baker & Mckenzie LLP Patent Department
20100097874 - Method and apparatus for performing refreshes: A method of operating a system including a memory device. The method includes, upon receiving a request for an internal hidden refresh for the memory device, latching external command, address, and data information for the memory device. The method further includes placing the memory device in a standby state and... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20100097876 - Apparatus and method for generating wide-range regulated supply voltages for a flash memory: A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage... Agent: Darby/spansion C/o Darby & Darby P.C.
20100097875 - Enhanced power distribution in an integrated circuit: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to... Agent: Ryan, Mason & Lewis, LLP
20100097877 - Semiconductor memory apparatus: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.... Agent: Ip & T Law Firm PLC
20100097878 - User selectable banks for dram: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is... Agent: Leffert Jay & Polglaze, P.A.04/15/2010 > patent applications in patent subcategories. category listing, related patent applications
20100091535 - Adaptive estimation of memory cell read thresholds: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is... Agent: D. Kligler I.p. Services Ltd
20100091538 - Bridge device architecture for connecting discrete memory devices to a system: Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100091536 - Composite memory having a bridging device for connecting discrete memory devices to a system: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory... Agent: Borden Ladner Gervais LLP Anne Kinsman
20100091540 - Memory module decoder: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element... Agent: Knobbe Martens Olson & Bear LLP
20100091537 - Multi-die memory device: An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to... Agent: Mahamedi Paradice Kreisman LLP
20100091539 - Solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same: Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products.... Agent: Harness, Dickey & Pierce, P.L.C
20100091541 - Stacked memory device and method thereof: A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify... Agent: Harness, Dickey & Pierce, P.L.C
20100091544 - Couplings within memory devices: A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum
20100091542 - Memory module having a memory device configurable to different data pin configurations: A memory module includes a memory device having a plurality of data pins and conductive lines electrically connected to the plurality of data pins. The memory device is configurable, using at least one input to the memory device, to a data pin configuration selected from among a plurality of different... Agent: Hewlett-packard Company Intellectual Property Administration
20100091543 - Semiconductor memory apparatus including a coupling control section: A semiconductor memory apparatus is disclosed having a dual open bit line structure In the dual open bit line structure, bit lines or bit line bars are each arranged side by side in adjoining cell mats. The semiconductor memory apparatus includes a coupling control section connected between at least one... Agent: Ladas & Parry LLP
20100091545 - Electically programmable fuse bit: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories,... Agent: Perkins Coie LLP Patent-sea
20100091546 - High density reconfigurable spin torque non-volatile memory: One time programmable memory units include a magnetic tunnel junction cell electrically coupled to a bit line and a word line. The magnetic tunnel junction cell is pre-programmed to a first resistance state, and is configured to switch only from the first resistance state to a second resistance state by... Agent: Campbell Nelson Whipps, LLC
20100091547 - Semiconductor memory device: A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value... Agent: Knobbe Martens Olson & Bear LLP
20100091548 - Non-volatile memory array with resistive sense element block erase and uni-directional write: A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100091549 - Non-volatile memory cell with complementary resistive memory elements: A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100091552 - Nonvolatile memory device using variable resistive element: A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column... Agent: Volentine & Whitt PLLC
20100091553 - Semiconductor device having resistance based memory array and method of operation associated therewith: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion... Agent: Harness, Dickey & Pierce, P.L.C
20100091551 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100091550 - Voltage reference generation with selectable dummy regions: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage with dummy resistive sense element regions. A first resistance distribution is obtained for a first dummy region of resistance sense elements and a second resistance distribution is obtained for a... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100091554 - Semiconductor device and method of operating thereof: A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines and precharges the first and second... Agent: Foley And Lardner LLP Suite 500
20100091557 - Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore,... Agent: Mcdermott Will & Emery LLP
20100091556 - Magneto-resistance effect element and magnetic memory: It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magnetization is pinned to be substantially anti-parallel to the direction of magnetization... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100091555 - Magnetoresistive effect element and magnetic random access memory: A magnetic random access memory has a laminating structure including: a magnetization free layer; an insulating layer; and a magnetization fixed layer. The magnetization free layer includes: a sense layer; a first bonding layer being adjacent to the sense layer; and a storage layer being adjacent to the first bonding... Agent: Mr. Jackson Chen
20100091558 - Dielectric-sandwiched pillar memory device: A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100091560 - Multi-terminal phase change devices: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created... Agent: James M. Wu Jw Law Group
20100091561 - Programmable matrix array with chalcogenide material: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or... Agent: Philip H. Schlazer Energy Conversion Devices, Inc.
20100091559 - Programmable resistance memory with feedback control: A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory... Agent: Ovonyx, Inc
20100091563 - Magnetic memory with phonon glass electron crystal material: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron... Agent: Campbell Nelson Whipps, LLC
20100091564 - Magnetic stack having reduced switching current: A magnetic stack having a ferromagnetic free layer, a ferromagnetic pinned reference layer, a non-magnetic spacer layer between the free layer and the reference layer, and a variable layer proximate the free layer. The variable layer is antiferromagnetic at a first temperature and paramagnetic at a second temperature higher than... Agent: Campbell Nelson Whipps, LLC
20100091562 - Temperature dependent system for reading st-ram: A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the... Agent: Campbell Nelson Whipps, LLC
20100091565 - M+n bit programming and m+l bit read for m bit memory cells: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20100091566 - Nand flash memory: In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100091567 - Test circuit and method for multilevel cell flash memory: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.... Agent: Dla Piper LLP (us )
20100091568 - Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits: A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100091569 - Methods of forming flash device with shared word lines: Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are... Agent: Vierra Magen/sandisk Corporation
20100091570 - Semiconductor memory device capable of increasing writing speed: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100091571 - Nonvolatile memory device with nand cell strings: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating... Agent: Volentine & Whitt PLLC
20100091572 - 2t nor-type non-volatile memoryt cell array and method of processing data of 2t nor-type non-volatile memory: Provided are a 2-transistor (2T) NOR cell array which includes at least a cell, and a cell comprising a selection transistor and a storage transistor including a charge storage floating gate or a charge storage dielectric, and a method of processing data of a 2T NOR flash memory cell which... Agent: Jae Y. Park
20100091573 - Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits: A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100091574 - One-transistor composite-gate memory: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more... Agent: Leffert Jay & Polglaze, P.A.
20100091576 - Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device: A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a... Agent: Mills & Onello LLP
20100091575 - Programming method and initial charging method of nonvolatile memory device: A programming method of a nonvolatile memory device includes precharging bit lines of the nonvolatile memory device based on loaded data, boosting channels corresponding to the respective precharged bit lines, after supplying word lines adjacent to a selected word line of the nonvolatile memory device with an initializing voltage, the... Agent: Volentine & Whitt PLLC
20100091577 - Memory cell storage node length: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage... Agent: Brooks, Cameron & Huebsch , PLLC
20100091578 - Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations... Agent: Myers Bigel Sibley & Sajovec
20100091585 - Static random access memories and access methods thereof: A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100091586 - Techniques for simultaneously driving a plurality of source lines: Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for simultaneously driving a plurality of source lines. The apparatus may include a plurality of source lines coupled to a single source line driver. The apparatus... Agent: Hunton & Williams LLP Intellectual Property Department
20100091580 - Semiconductor memory device: A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality... Agent: Ip & T Law Firm PLC
20100091582 - Architecture and method for memory programming: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a... Agent: Leffert Jay & Polglaze, P.A.
20100091581 - Memory device and method of operating such a memory device: A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the... Agent: Nixon & Vanderhye P.C.
20100091583 - Memory device having latch for charging or discharging data input/output line: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is... Agent: Ip & T Law Firm PLC
20100091584 - Memory device and methods thereof: A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the... Agent: Larson Newman & Abel, LLP
20100091587 - Device selection circuit and method: Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals).... Agent: Intel Corporation C/o Cpa Global
20100091588 - Memory device and memory system comprising a memory device and a memory control device: In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20100091579 - Non-volatile semiconductor memory apparatus: A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control... Agent: Baker & Mckenzie LLP Patent Department
20100091590 - Semiconductor memory apparatus: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM... Agent: Mcginn Intellectual Property Law Group, PLLC
20100091589 - Semiconductor memory device: A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second... Agent: Volentine & Whitt PLLC
20100091591 - Data strobe signal generating device and a semiconductor memory apparatus using the same: A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate... Agent: Baker & Mckenzie LLP Patent Department
20100091592 - Clock buffer and a semiconductor memory apparatus using the same: A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal... Agent: Ip & T Law Firm PLC
20100091593 - Semiconductor memory device including signal controller connected between memory blocks: A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines... Agent: Volentine & Whitt PLLC
20100091594 - Semiconductor memory for disconnecting a bit line from sense amplifier in a standby period and memory system including the semiconductor memory: Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection... Agent: Arent Fox LLP
20100091595 - Integrated circuit with control circuit for performing retention test: An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for... Agent: Dicke, Billig & Czaja
20100091596 - Solid state drive systems and methods of reducing test times of the same: Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same.... Agent: Harness, Dickey & Pierce, P.L.C
20100091597 - Semiconductor device: A semiconductor device includes an internal voltage generating circuit which includes a first voltage generating circuit, a second voltage generating circuit having a higher current supply capability than the first voltage generating circuit, and a control circuit that controls switching between activation and inactivation of the second voltage generating circuit,... Agent: Morrison & Foerster LLP
20100091598 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and... Agent: Ladas & Parry LLP
20100091599 - Semiconductor memory apparatus: A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the... Agent: Baker & Mckenzie LLP Patent Department
20100091600 - Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the... Agent: Volentine & Whitt PLLC
20100091601 - Circuit and methods for eliminating skew between signals in semicoductor integrated circuit: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data... Agent: Volentine & Whitt PLLC
20100091602 - Address counting circuit and semiconductor memory apparatus using the same: An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output converted addresses such that only one address bit... Agent: Ladas & Parry LLP04/08/2010 > patent applications in patent subcategories. category listing, related patent applications
20100085790 - Amplifier circuit and associative memory: An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI1 to VIR), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and... Agent: Foley & Lardner LLP
20100085791 - Driver unit: A driving apparatus (100c) is provided with: a base portion (110); a stage portion (130) on which a driven object (12) is mounted and which can be displaced; an elastic portion (120) which connects the base portion and the stage portion and which has elasticity to displace the stage portion... Agent: Young & Thompson
20100085792 - Semiconductor device: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is... Agent: Cook Alex Ltd
20100085793 - Wall nucleation propagation for racetrack memory: A shift register is provided, the shift register comprising at least one track including a storage region. The storage region comprises a plurality of magnetic domains for storing data. A given first one of the plurality of magnetic domains is adjacent to a given second one of the plurality of... Agent: Ryan, Mason & Lewis, LLP
20100085795 - Asymmetric write current compensation: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100085797 - Dual stage sensing for non-volatile memory: A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100085796 - Enhancing read and write sense margins in a resistive sense element: An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100085799 - Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance... Agent: Volentine & Whitt PLLC
20100085794 - Set and reset detection circuits for reversible resistance switching memory material: Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed,... Agent: Vierra Magen/sandisk Corporation
20100085798 - Silicon-based nanoscale resistive device with adjustable resistance: A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can... Agent: James D. Stevens Reising Ethington P.C.
20100085800 - Semiconductor devices including buried gate electrodes and methods of forming semiconductor devices including buried gate electrodes: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of... Agent: Lee & Morse, P.C.
20100085801 - Methods of forming thin films for molecular based devices: The invention generally encompasses methods of forming thin films molecular based devices, and devices formed therefrom. Some embodiments relate to molecular memory cells, molecular memory arrays, electronic devices including molecular memory, and processing systems and methods for producing molecular memories. More particularly, the present invention encompasses methods and molecular based... Agent: Morgan, Lewis & Bockius, LLP. (pa)
20100085802 - Multi-state latches from n-state reversible inverters: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use... Agent: Diehl Servilla LLC
20100085803 - Electronic devices utilizing spin torque transfer to flip magnetic orientation: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing... Agent: Campbell Nelson Whipps, LLC
20100085804 - Semiconductor memory device and data processing system including the same: In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line... Agent: Sughrue Mion, PLLC
20100085805 - Magnetic random access memory (mram) utilizing magnetic flip-flop structures: Non-volatile magnetic random access memory (MRAM) devices that include magnetic flip-flop structures that include a magnetization controlling structure; a first tunnel barrier structure; and a magnetization controllable structure that includes a first polarizing layer; and a first stabilizing layer, wherein the first tunnel barrier structure is between the magnetization controllable... Agent: Campbell Nelson Whipps, LLC
20100085806 - Techniques for reducing a voltage swing: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one... Agent: Hunton & Williams LLP Intellectual Property Department
20100085809 - Multi-bit flash memory and reading method thereof: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then,... Agent: Rabin & Berdo, PC
20100085808 - Read method for mlc: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A.
20100085807 - Single latch data circuit in a multiple level cell non-volatile memory device: A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20100085810 - Method of controlling memory system: A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100085812 - Nonvolatile memory devices having common bit line structure: Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each... Agent: Myers Bigel Sibley & Sajovec
20100085811 - Scaled down select gates of nand flash memory cell strings and method of forming same: A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100085813 - Method of driving a semiconductor memory device and a semiconductor memory device: This disclosure concerns a driving method of a memory having cells of floating body type which comprises executing, during a write operation, a first cycle of applying a first potential to the bit lines corresponding to the first selected cells and of applying a second potential to the selected word... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100085814 - Semiconductor integrated circuit device: A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (64) which starts an operation... Agent: Frishauf, Holtz, Goodman & Chick, PC
20100085815 - Command generation circuit and semiconductor memory device: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching... Agent: Cooper & Dunham, LLP
20100085816 - Flag signal generation circuit and semiconductor memory device: There is provided a flag signal generation circuit. The flag signal generation circuit includes a status register read (SRR) signal generating unit receiving an idle signal and an SRR command to generate an SRR signal; a pulse signal generating unit receiving an SRR signal to generate a pulse signal; and... Agent: Cooper & Dunham, LLP
20100085817 - Semiconductor memory device to reduce off-current in standby mode: A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal... Agent: Cooper & Dunham, LLP
20100085819 - Burst length control circuit and semiconductor memory device using the same: A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a... Agent: Cooper & Dunham, LLP
20100085818 - Semiconductor memory device: A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a... Agent: Cooper & Dunham, LLP
20100085820 - Semiconductor memory device: There is provided a semiconductor memory device having a plurality of memory cell layers which can be used even if part of the memory cell layers is determined as defective. The semiconductor memory device includes a stacked memory cell array having a laminated plurality of memory cell layers, each of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100085822 - Continuous programming of non-volatile memory: A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control... Agent: Vierra Magen/sandisk Corporation
20100085821 - Operation method of non-volatile memory: Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation.... Agent: Harness, Dickey & Pierce, P.L.C
20100085823 - Optimizing sram performance over extended voltage or process range using self-timed calibration of local clock generator: A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In... Agent: Ibm Corporation (jvm)
20100085824 - Semiconductor device having delay control circuit: A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal... Agent: Mcginn Intellectual Property Law Group, PLLC
20100085825 - Stacked device remapping and repair: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.... Agent: Schwegman, Lundberg & Woessner/micron
20100085826 - Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same: The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a... Agent: Harness, Dickey & Pierce, P.L.C
20100085827 - Coupling methods and architectures for information processing: A structure comprising (i) a first information device, (ii) a second information device, (iii) a first coupling element and (iv) a second coupling element is provided. The first information device has at least a first lobe and a second lobe that are in electrical communication with each other. The second... Agent: Seed Intellectual Property Law Group PLLC
20100085829 - Internal voltage generation circuit: An internal voltage generation circuit includes a temperature detection unit which detects an internal temperature of a semiconductor memory device and generates a temperature signal, a driving control signal generation unit which receives the temperature signal and generates first and second driving control signals, and an internal voltage generation unit... Agent: Cooper & Dunham, LLP
20100085828 - Method for reducing leakage current of a memory and related device: A method for reducing leakage current of a memory device includes supplying a first voltage to a main wordline driver, supplying a second voltage greater than the first voltage to a local wordline driver, and employing a transistor in the local wordline driver with a threshold voltage greater than a... Agent: North America Intellectual Property Corporation
20100085830 - Sequencing decoder circuit: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the... Agent: Goodwin Procter LLP Patent Administrator04/01/2010 > patent applications in patent subcategories. category listing, related patent applications
20100080032 - Semiconductor device: A semiconductor device is provided in which two adjacent cell lines extending in a word line direction are connected by one word line. Additionally, A semiconductor device comprising: word lines; bit lines which are disposed to cross the word lines; a plurality of cell lines extending in a word line... Agent: Young & Thompson
20100080033 - Volatile memory elements with soft error upset immunity: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array... Agent: Treyz Law Group
20100080034 - Magnetic shift register and operation method thereof: A magnetic shift register includes at least a magnetic memory track of which several magnetic walls separate the memory track into multiple magnetic domains to serve as magnetic binary memory cells. The magnetic memory track includes multiple data regions. Each data region has multiple of the magnetic binary memory cells... Agent: Jianq Chyun Intellectual Property Office
20100080035 - Sram based one-time-programmable memory: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of... Agent: Cochran Freund & Young LLC Lsi Corporation
20100080036 - Unidirectional spin torque transfer magnetic memory cell structure: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the... Agent: Fletcher Yoder (micron Technology, Inc.)
20100080042 - Integrating nonvolatile memory capability within sram devices: A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices... Agent: Cantor Colburn LLP-ibm Burlington
20100080040 - Nonvolatile memory device and method of driving the same: A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance... Agent: Harness, Dickey & Pierce, P.L.C
20100080037 - Nonvolatile semiconductor memory device: Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device comprises: a load resistive characteristic variable circuit for each bit line connected commonly with the... Agent: Birch Stewart Kolasch & Birch
20100080039 - Nonvoltile memory device and method of driving the same: A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality... Agent: Harness, Dickey & Pierce, P.L.C
20100080041 - Semiconductor device: A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively... Agent: Mcginn Intellectual Property Law Group, PLLC
20100080038 - Semiconductor memory device: An inexpensive nonvolatile memory having high performance which makes random write and readout possible an unlimited number of times is provided. A unit memory cell is formed of a MISFET having a channel body that is electrically isolated from a semiconductor substrate and a resistance change element having a two-terminal... Agent: Nixon & Vanderhye, PC
20100080043 - Apparatus for the dynamic detection, selection and deselection of leaking decoupling capacitors: Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20100080044 - Semiconductor memory device having balancing capacitors: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell... Agent: Volentine & Whitt PLLC
20100080045 - Robust 8t sram cell: This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a... Agent: K&l Gates LLPIPDocketing
20100080046 - Semiconductor device: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.... Agent: Miles & Stockbridge PC
20100080047 - Spin current generator for stt-mram or other spintronics applications: Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin... Agent: Fletcher Yoder (micron Technology, Inc.)
20100080048 - Stt-mram cell structure incorporating piezoelectric stress material: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used... Agent: Fletcher Yoder (micron Technology, Inc.)
20100080050 - Magnetoresistive effect device and magnetic memory: A magnetic memory includes a magnetoresistive effect device comprising: a first ferromagnetic layer that has magnetic anisotropy in a direction perpendicular to a film plane thereof; a first nonmagnetic layer that is provided on the first ferromagnetic layer; a first reference layer that is provided on the first nonmagnetic layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080049 - Thermally assisted multi-bit mram: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.... Agent: Campbell Nelson Whipps, LLC
20100080051 - Bit-erasing architecture for seek-scan probe (ssp) memory storage: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer... Agent: Intel Corporation C/o Cpa Global
20100080052 - Arrangement and method for controlling a micromechanical element: The invention concerns an arrangement for controlling a non-volatile memory arrangement for a circuit comprising: a micromechanical element coupled to a substrate; the micromechanical element being responsive to deflection means arranged on the substrate to control the movement of the micromechanical element between one or more stable states. In addition,... Agent: Patterson & Sheridan, L.L.P.
20100080054 - Non-volatile semiconductor memory device and its reading method: A reading method includes: selecting the memory cell; performing a read operation on the selected memory cell to supply the read voltage, amplifying a first voltage read out from the selected memory element, outputting a second voltage obtained by amplifying the first voltage, and storing the second voltage as a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080053 - Static source plane in stram: The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state... Agent: Campbell Nelson Whipps, LLC
20100080055 - Semiconductor memory device: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory... Agent: Studebaker & Brackett PC
20100080056 - Semiconductor memory system: A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080057 - Providing a capacitor-based power supply to enable backup copying of data from volatile storage to persistent storage: A system includes a volatile storage, a persistent storage, a capacitor-based power supply, and a controller coupled to the capacitor-based power supply. The controller detects interruption of main power, and in response to detecting the interruption of main power, begins backup copying of data from the volatile storage to the... Agent: Hewlett-packard Company Intellectual Property Administration
20100080058 - Semiconductor device: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of... Agent: Mattingly & Malur, P.C.
20100080060 - Determining memory page status: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.... Agent: Brooks, Cameron & Huebsch , PLLC
20100080059 - Page buffer used in a nand flash memory and programming method thereof: A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch... Agent: Wpat, PC Intellectual Property Attorneys
20100080061 - Nonvolatile semiconductor memory system: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080063 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell group, transfer transistor, and switching circuit. The memory cell group has a plurality of memory cells each including a floating gate and control gate, and the current paths of the plurality of memory cells are connected in series. The transfer transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080062 - Nonvolatile semiconductor memory device and method for driving same: A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080064 - Bit line bias for programming a memory device: Bit line bias for programming a memory device is generally described. In one example, circuitry for bit line bias programming comprises a word line, one or more bit lines coupled with the word line, and one or more cells to be programmed to a target threshold voltage coupled with the... Agent: Cool Patent, P.C. C/o Cpa Global
20100080065 - Nonvolatile semiconductor memory device and method for driving the same: A nonvolatile semiconductor memory device includes a memory cell and a driving unit. The a memory cell has a semiconductor layer having, a channel, and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; a charge retention... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080066 - Memory, memory operating method, and memory system: A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first... Agent: Arent Fox LLP
20100080067 - Memory and reading method thereof: A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100080068 - Memory cell, and method for storing data: The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential... Agent: Brooks Kushman P.C.
20100080069 - Semiconductor memory device: A NAND type flash memory for erasing data every block including plural memory cell transistors that are provided every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100080070 - Method for reducing power consumption in a volatile memory and related device: A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline... Agent: North America Intellectual Property Corporation
20100080071 - Data storage using read-mask-write operation: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100080072 - Methods and systems to write to soft error upset tolerant latches: Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one... Agent: Garrett Ip, LLC
20100080073 - Semiconductor memory: A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy... Agent: Arent Fox LLP
20100080074 - Semiconductor memory device: Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant... Agent: Eric Robinson
20100080075 - Memory device refresh method and apparatus: In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address... Agent: Coats & Bennett/qimonda
20100080076 - Common memory device for variable device width and scalable pre-fetch and page size: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example,... Agent: Intel Corporation C/o Cpa GlobalPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140710:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.38699 seconds