|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval March listing by industry category 03/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/25/2010 > patent applications in patent subcategories.
20100073981 - Switched current memory cell: A switched current memory cell includes: a current source 100 having one end connected to an operation power source (Vdd) stage, a current memory circuit unit 200 that stores an input current; which is inputted in a sampling mode according to current from the current source 100, during a hold... Agent: Lowe Hauptman Ham & Berner, LLP
20100073983 - Nonvolatile semiconductor memory device and writing method of the same: A nonvolatile semiconductor memory device comprises a memory cell array composed of a plurality of memory cells each including a variable resistance element in which a resistance characteristic is changed by applying a voltage to the both ends, and information related to the resistance characteristic can be stored; a load... Agent: Nixon & Vanderhye, PC
20100073982 - Semiconductor device and method for designing the same: Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners... Agent: Mcginn Intellectual Property Law Group, PLLC
20100073984 - Magnetic shift register as counter and data storage device: A register having a track with a first electrode is at the first end to supply a current to the track in a first direction and a second electrode at the second end to supply a current to the track in a second direction, the second direction being opposite to... Agent: Campbell Nelson Whipps, LLC
20100073985 - Method for operating one-time programmable read-only memory: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the... Agent: J C Patents
20100073989 - Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed... Agent: Ip & T Law Firm PLC
20100073988 - Nonvolatile semiconductor storage device: n
20100073986 - Semiconductor memory device: A semiconductor memory device includes a plurality of cell blocks each of which is configured by serially connecting a plurality of memory cells each of which comprises a ferroelectric capacitor and a cell transistor connected in parallel; a plurality of word lines connected to gates of the cell transistors; a... Agent: Knobbe Martens Olson & Bear LLP
20100073987 - Semiconductor memory device and driving method of semiconductor memory device: A memory includes a memory cell array comprising memory cells; word lines connected to gates of the cell transistors; bit lines connected to one ends of the memory cells on the cell transistor side; plate lines connected to the other ends of the memory cells on the ferroelectric capacitor side;... Agent: Knobbe Martens Olson & Bear LLP
20100073990 - Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays: Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of... Agent: Unity Semiconductor Corporation
20100073993 - Multi-resistive integrated circuit memory: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum... Agent: Schwegman, Lundberg & Woessner/micron
20100073992 - Semiconductor memory device: A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to... Agent: Knobbe Martens Olson & Bear LLP
20100073991 - Storage apparatus: According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having a third state and a fourth state, wherein the first storage element is brought into the first state... Agent: Turocy & Watson, LLP
20100073994 - Leakage compensation circuit for dynamic random access memory (dram) cells: A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100073995 - Nano -electronic array: A nano device includes an array of cells disposed in rows and columns and constructed over a substrate, and an optical circuit disposed over the substrate, wherein the optical circuit is formed by nano elements in a self-assembled process.... Agent: Tran & Associates
20100073996 - Semiconductor device: In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100073997 - Piezo-driven non-volatile memory cell with hysteretic resistance: A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low resistance state and high resistance state through applied pressure cycling thereto; a piezoelectric material mechanically coupled to the PHRM such that an applied voltage across the piezoelectric... Agent: Cantor Colburn LLP-ibm Yorktown
20100073998 - Data writing method for magnetoresistive effect element and magnetic memory: A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100074000 - Analog access circuit for validating chalcogenide memory cells: An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an... Agent: Bae Systems
20100074001 - Information recording/reproducing device: The information recording/reproducing device includes a stacked structure which is comprised of an electrode layer and a recording layer, a buffer layer which contacts with the recording layer and a recording circuit which records data to the recording layer by generating a phase change in the recording layer. The recording... Agent: Charles N.j. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
20100073999 - Semiconductor integrated circuit: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are... Agent: Miles & Stockbridge PC
20100074002 - Tri-state memory device and method: A non-volatile tri-state random access memory device, including a permanent magnetic bit; a write module in functional communication with the permanent magnetic bit and configured to selectably alter the permanent magnetic bit between three magnetic states, a write module including a write coil disposed about the permanent magnetic bit and... Agent: Advantia Law Group
20100074003 - Single conductor magnetoresistance random access memory cell: The single conductor magnetoresistance random access memory consists of memory cells which are made up of a flat thin film conductor, covered on both flat surfaces with thin magnetic films. Their coercive forces have different values. A current flowing through the conductor produces a magnetic field which circles the conductor.... Agent: Klaus Schroder
20100074006 - Dynamic erase state in flash device: Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory... Agent: Turocy & Watson, LLP
20100074005 - Eeprom emulation in flash device: Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a... Agent: Turocy & Watson, LLP
20100074007 - Flash mirror bit architecture using single program and erase entity as logical cell: Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping... Agent: Turocy & Watson, LLP
20100074004 - High vt state used as erase condition in trap based nor flash cell design: Flash memory systems and methodologies are provided herein for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program... Agent: Turocy & Watson, LLP
20100074012 - Least significant bit page recovery method used in multi-level cell flash memory device: A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device is provided. The method includes setting first through nth LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages... Agent: Staas & Halsey LLP
20100074010 - Memory device reference cell programming method and apparatus: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference... Agent: Leffert Jay & Polglaze, P.A.
20100074011 - Non-volatile memory device and page buffer circuit thereof: A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify... Agent: Mills & Onello LLP
20100074009 - Quad+bit storage in trap based flash design using single program and erase entity as logical cell: Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase... Agent: Turocy & Watson, LLP
20100074008 - Sector configure registers for a flash device generating multiple virtual ground decoding schemes: Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes... Agent: Turocy & Watson, LLP
20100074013 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming sacrificial spacers on lateral surfaces of the sacrificial vertical structure;... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20100074020 - Charge pump operation in a non-volatile memory device: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify... Agent: Leffert Jay & Polglaze, P.A.
20100074016 - Data retention of last word line of non-volatile memory arrays: Techniques are disclosed herein for operating non-volatile storage. The techniques compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and... Agent: Vierra Magen/sandisk Corporation
20100074014 - Data state-based temperature compensation during sensing in non-volatile memory: Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current is provided for each data state, so that a common temperature coefficient is realized for storage elements with different data states.... Agent: Vierra Magen/sandisk Corporation
20100074019 - Memory card, semiconductor device, and method of controlling memory card: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100074017 - Method for programming nand type flash memory: Disclosed is a method for programming a flash memory device capable of preventing a threshold voltage distribution of a memory cell from being moved due to a pass disturbance of the memory cell programmed initially at a program operation performed on a page-unit basis. The method for programming a NAND... Agent: Marshall, Gerstein & Borun LLP
20100074021 - Nand flash memory programming: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.... Agent: Leffert Jay & Polglaze, P.A.
20100074018 - Read operation for non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20100074015 - Sensing for memory read and program verify operations in a non-volatile memory device: Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage... Agent: Leffert Jay & Polglaze, P.A.
20100074022 - Memory and method for programming the same: A method for programming a memory is provided. The memory includes multiple rows of memory cells each including two half cells. The method includes the following steps. Whether the two half cells of a to-be-programmed memory cell of the nth row memory cells are both needed to be programmed or... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100074023 - Semiconductor device having non-volatile memory and method of fabricating the same: A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell transistor gates of first and second memory... Agent: Mills & Onello LLP
20100074025 - Nonvolatile memory devices having erased-state verify capability and methods of operating same: A program method of a nonvolatile memory device includes applying a program voltage to program cells for changing data; verifying the program cells, based on the changed data; and verifying program inhibit cells for maintaining stored data even when the program voltage is applied to the program inhibit cells, based... Agent: Myers Bigel Sibley & Sajovec
20100074024 - Programming a memory device to increase data reliability: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group... Agent: Leffert Jay & Polglaze, P.A.
20100074026 - Flash memory device and systems and reading methods thereof: A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a plurality of coupling compensation parameters;... Agent: Harness, Dickey & Pierce, P.L.C
20100074027 - High second bit operation window method for virtual ground array with two-bit memory cells: A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable... Agent: J C Patents
20100074028 - Memory architecture having two independently controlled voltage pumps: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum... Agent: Cypress Semiconductor Corporation
20100074029 - Nonvolatile semiconductor memory device and operation method thereof: A p-type well region is formed at a main surface of a semiconductor substrate. An n-type impurity region is located under the p-type well region. A first insulating layer (6) is formed on the main surface of the semiconductor substrate and on the p-type well region. A charge-storage insulating layer... Agent: Mcdermott Will & Emery LLP
20100074030 - Adaptive regulator for idle state in a charge pump circuit of a memory device: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of... Agent: Schwegman, Lundberg & Woessner / Atmel
20100074031 - Test mode signal generator for semiconductor memory and method of generating test mode signals: A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a... Agent: Ladas & Parry LLP
20100074032 - Memory having self-timed bit line boost circuit and method therefor: A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair... Agent: Freescale Semiconductor, Inc. Law Department
20100074033 - Bandgap voltage and temperature coefficient trimming algorithm: A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100074034 - Voltage regulator with reduced sensitivity of output voltage to change in load current: A voltage regulator is disclosed. The voltage regulator has a voltage generation circuit that outputs a regulated voltage and a load current. The voltage regulation circuit has a sensing circuit that senses a peak magnitude of the load current and stores a peak signal that is based on the peak... Agent: Vierra Magen/sandisk Corporation
20100074035 - Semiconductor memory device: A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100074036 - Current mode memory apparatus, systems, and methods: Some embodiments include a first circuit to drive signals at first circuit output nodes, and a second circuit to generate output signals at second circuit output nodes. The second circuit includes a first transistor coupled between a supply node and a first node of the second circuit output nodes and... Agent: Schwegman, Lundberg & Woessner/micron
20100074037 - Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay: Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100074038 - Memory dies for flexible use and method for configuring memory dies: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer... Agent: Slater & Matsil, L.L.P.
20100074039 - Semiconductor memory device and method for testing the same: A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/output circuit includes a main amplifier that amplifies data written into... Agent: Young & Thompson
20100074040 - Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment: The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment,... Agent: Ibm Corporation (swp)
20100074041 - Semiconductor device including asymmetric sense amplifier: A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a first sense amplification unit having a first sense amplifier and a second... Agent: Volentine & Whitt PLLC
20100074042 - Semiconductor memory device: A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100074043 - Semiconductor device: A semiconductor device includes an internal circuit configured to receive a first power supply voltage applied via a first power input terminal through a first power supply path and receive an internal power supply voltage to perform a predetermined circuit operation and an internal power supply voltage generator configured to... Agent: Ip & T Law Firm PLC03/18/2010 > patent applications in patent subcategories.
20100067277 - Content-addressable memory: A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first... Agent: The Webb Law Firm, P.C.
20100067278 - Mass data storage system with non-volatile memory modules: A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to... Agent: Smart & Biggar
20100067279 - Semiconductor memory device using variable resistor: Example embodiments relate to a variable resistance semiconductor memory device including: a plurality of memory blocks belonging to different memory sectors and alternately arranged in a memory bank including the memory sectors so as to be adjacent to each other; and a line selecting unit simultaneously selecting word lines of... Agent: F. Chau & Associates, LLC
20100067282 - Memory array with read reference voltage cells: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage... Agent: Campbell Nelson Whipps, LLC
20100067283 - Sense amplifier: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100067281 - Variable write and read methods for resistive random access memory: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the... Agent: Campbell Nelson Whipps, LLC
20100067284 - Semiconductor memory device: A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line,... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20100067288 - Memory device structures including phase-change storage cells: A conductive write line of a memory device includes a resistive heating portion for setting and resetting a phase-change material (PCM) storage cell of the device. A dielectric interface extends between the resistive heating portion of the write line and a side of the storage cell, and provides electrical insulation... Agent: Intellectual Property Group Seagate Technology Files
20100067286 - Memory sensing devices, methods, and systems: The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and... Agent: Brooks, Cameron & Huebsch , PLLC
20100067291 - Method for programming phase-change memory and method for reading date from the same: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold... Agent: Sughrue Mion, PLLC
20100067290 - Method of programming of phase-change memory and associated devices and materials: A method of programming a phase-change memory (PCM) device to the high resistance reset state by means of pressure-induced amorphization. A train of few short pulses is applied to the PCM device produces high pressure on phase-change alloy (PCA). PCM device contains a PCA with easily deformed atomic structure by... Agent: Semyon D. Savransky
20100067285 - Novel sensing circuit for pcram applications: A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100067289 - Semiconductor device: A semiconductor device includes first and second phase-change memory elements (GST1 and GST2), each being programmed by a current supplied from a power supply (Vdd). A set voltage and a reset voltage supplied to a pair of complementary write bit lines (WBT and WBB) are applied respectively to gates of... Agent: Sughrue Mion, PLLC
20100067287 - Temperature compensation in memory devices and systems: The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current... Agent: Brooks, Cameron & Huebsch , PLLC
20100067293 - Programmable and redundant circuitry based on magnetic tunnel junction (mtj): Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and... Agent: Fish & Richardson, PC
20100067292 - Semiconductor integrated circuit: A semiconductor integrated circuit is provided that can prevent an internal voltage from the voltage generating circuit from varying during a long term. The semiconductor integrated circuit of the present invention includes a voltage generating circuit configured to generate a reference voltage; a function circuit configured to operate by using... Agent: Mcginn Intellectual Property Law Group, PLLC
20100067294 - Semiconductor memory device: A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage;... Agent: Ip & T Law Firm PLC
20100067295 - Refresh method for a non-volatile memory: A refresh method for a non-volatile memory for preventing disturb phenomenon includes reading data of a memory unit of the non-volatile memory at a first time point within a predefined period and storing the data in a buffer, determining whether data of the memory unit and data of the buffer... Agent: North America Intellectual Property Corporation
20100067296 - Compensating for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation
20100067297 - Bias circuits and methods for enhanced reliability of flash memory device: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in... Agent: Muir Patent Consulting, PLLC
20100067298 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100067299 - Non-volatile semiconductor memory device: A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100067300 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100067301 - Columnar non-volatile memory devices with auxiliary transistors and methods of operating the same: A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at... Agent: Myers Bigel Sibley & Sajovec
20100067303 - Flash memory device capable of reduced programming time: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored... Agent: Volentine & Whitt PLLC
20100067302 - Nand-type flash memory and nand-type flash memory controlling method: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100067304 - Write once read only memory employing charge trapping in insulators: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain... Agent: Schwegman, Lundberg & Woessner/micron
20100067307 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled... Agent: Leffert Jay & Polglaze, P.A.
20100067305 - Nonvolatile memory device and program method with improved pass voltage window: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a... Agent: Volentine & Whitt PLLC
20100067306 - Nonvolatile memory device, operating method thereof, and memory system including the same: A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number... Agent: Volentine & Whitt PLLC
20100067308 - Sub volt flash memory system: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other... Agent: Dla Piper LLP (us )
20100067309 - Efficient erase algorithm for sonos-type nand flash: A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100067310 - Mos transistor with a settable threshold: A MOS transistor comprising a conductive extension of its source region, insulated from its substrate, and partially extending under its channel.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100067313 - Memory device: A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100067311 - Non-volatile memory device having high speed serial interface: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data... Agent: Dla Piper LLP (us )
20100067312 - Semiconductor memory device and system including the same: A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is... Agent: Volentine & Whitt PLLC
20100067314 - Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the... Agent: Silicon Edge Law Group, LLP
20100067315 - Semiconductor integrated circuit and method thereof: A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses, and a column strobe signal generating block providing a plurality of column strobe signals to selectively activate... Agent: Baker & Mckenzie LLP Patent Department
20100067317 - Semiconductor memory device and method of controlling sense amplifier of semiconductor memory device: A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense... Agent: Volentine & Whitt PLLC
20100067318 - Sense amplifier and semiconductor memory device having sense amplifier: A sense amplifier comprises: a differential amplifier circuit configured to generate an amplified signal depending on a difference in voltage between bit lines; an output circuit receiving the amplified signal; and a load. The differential amplifier circuit comprises: a first output node supplying the amplified signal to the output circuit;... Agent: Young & Thompson
20100067319 - Implementing precise resistance measurement for 2d array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor: A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected... Agent: Ibm Corporation RochesterIPLaw Dept 91703/11/2010 > patent applications in patent subcategories.
20100061131 - Circuit arrangement comprising a memory cell field and method for operation thereof: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell... Agent: Cohen, Pontani, Lieberman & Pavane LLP
20100061132 - Semiconductor storage device: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric... Agent: Miles & Stockbridge PC
20100061134 - Memory device interface methods, apparatus, and systems: Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may include an interface chip having a via to accommodate connection of the memory device to the substrate. Other apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron
20100061133 - Memory module and method of performing the same: A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to... Agent: Kirton And Mcconkie
20100061135 - Magnetic wire unit and storage device: A magnetic wire unit for storing information thereon includes a magnetic wire containing a material having an axis of easy magnetization, and extending in a first direction, the axis being switchable between the first direction and the second direction perpendicular to the first direction, the magnetic wire being capable of... Agent: Greer, Burns & Crain
20100061136 - Semiconductor memory device and semiconductor device: An anti-fuse memory device includes a plurality of word lines, a plurality of bit lines, and a memory cell provided with respect to an intersecting portion of any of the plurality of word lines and any of the plurality of bit lines. Memory cell includes a PIN diode and an... Agent: Cook Alex Ltd
20100061137 - One-time programmable read only memory: For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as... Agent: Juhan Kim
20100061138 - Photonic memory device, data storing method using the photonic memory device and photonic sensor device: Provided are a photonic memory device, a method of storing data using the photonic memory device, and a photonic sensor device. The photonic memory device comprises a signal line through which a photon is input; a ring resonator receiving a photon through an input gap that is adjacent to the... Agent: Lee, Hong, Degerman, Kang & Waimey
20100061139 - Random access memory circuit: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100061140 - Integrated circuit including doped semiconductor line having conductive cladding: An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.... Agent: Dicke, Billig & Czaja
20100061142 - Memory element and memory apparatus: Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing... Agent: Mcdermott Will & Emery LLP
20100061141 - Non-volatile memory device and storage system including the same: A non-volatile memory device may include a plurality of data cells, each data cell of the plurality of data cells programmed to have a first resistance variation among a plurality of first resistance variations; and a plurality of reference cells, each reference cell of the plurality of reference cells programmed... Agent: Harness, Dickey & Pierce, P.L.C
20100061143 - Assembling and applying nano-electro-mechanical systems: A method of constructing devices using semiconductor manufacturing processes includes fabricating a device having a movable portion and a fixed portion. The movable portion is connected to the fixed portion only through at least one sacrificial layer. The sacrificial layer is removed in the presence of a force of sufficient... Agent: Jones Day
20100061144 - Memory device for resistance-based memory applications: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first... Agent: Qualcomm Incorporated
20100061146 - Nonvolatile memory devices including variable resistive elements: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of... Agent: Myers Bigel Sibley & Sajovec
20100061145 - Phase change memory cell with mosfet driven bipolar access device: Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor.... Agent: Slater & Matsil, L.L.P.
20100061147 - Reducing effects of program disturb in a memory device: The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive Vpass voltage. The selected word lines are biased with a programming voltage. In one embodiment, the programming voltage is preceded by... Agent: Leffert Jay & Polglaze, P.A.
20100061149 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20100061148 - Semiconductor memory device and data write method thereof: A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100061150 - Logged-based flash memory system and logged-based method for recovering a flash memory system: A flash memory system includes a path selector to determine to write to a non-volatile memory, a volatile memory or both the non-volatile memory and the volatile memory when the flash memory system is to write data. A record is stored in the non-volatile memory which is updated the status... Agent: Rosenberg, Klein & Lee
20100061151 - Multi-pass programming for memory with reduced data storage requirement: Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse... Agent: Vierra Magen/sandisk Corporation
20100061152 - Method and system to access memory: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in... Agent: Schwegman, Lundberg & Woessner / Atmel
20100061153 - Refresh method for a non-volatile memory: A refresh method for a non-volatile memory for preventing disturb phenomenon includes dividing a plurality of sectors of a block of the non-volatile memory into a plurality of groups, determining a first group of the plurality of groups according to a first value when a first sector of the plurality... Agent: North America Intellectual Property Corporation
20100061154 - Non-volatile dual memory die for data storage devices: OTP Data storage die and device consisting of novel OTP (One-Time-Programming) NVM (Non-Volatile-Memory) die is disclosed. The OTP Data storage device can be used in typical host applications with standard interface protocols and file system. The novel OTP memory is a dual memory with both RAM (random access memory) capability... Agent: William H. Dippert Eckert Seamans Cherin & Mellott, LLC
20100061155 - Memory array segmentation and methods: An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of... Agent: Leffert Jay & Polglaze, P.A.
20100061157 - Data output circuit: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and... Agent: Ip & T Law Firm PLC
20100061158 - Low voltage sense amplifier and sensing method: Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier.... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100061156 - Method of controlling memory and memory system thereof: The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address... Agent: International Business Machines Corporation Dept. 18g
20100061160 - Die thermal sensor suitable for auto self refresh, integrated circuit with the same and method for on die thermal sensor suitable for auto self refresh: A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of... Agent: Ip & T Law Firm PLC
20100061159 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each... Agent: Ip & T Law Firm PLC
20100061161 - Self reset clock buffer in memory devices: A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the... Agent: Qualcomm Incorporated
20100061163 - Apparatus for generating pumping voltage: An apparatus for generating pumping voltage of a multiple Chip Select (CS) mode semiconductor memory apparatus includes a high speed pumping control unit configured to produce a pumping enable signal regardless of the level of a pumping voltage to actuate the pumping unit when a plurality of banks of the... Agent: Baker & Mckenzie LLP Patent Department
20100061162 - Circuit and method for optimizing memory sense amplifier timing: A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The... Agent: Freescale Semiconductor, Inc. Law Department
20100061164 - Fail-safe high speed level shifter for wide supply voltage range: The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20100061165 - Circuitry and methods for improving differential signals that cross power domains: Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occurs at an odd numbered stage in one differential output path and... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.
20100061167 - Data output circuit: A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate... Agent: Baker & Mckenzie LLP Patent Department
20100061166 - Dynamic real-time delay characterization and configuration: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays.... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera
20100061168 - Fuses for memory repair: Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the... Agent: Klein, O'neill & Singh, LLP
20100061169 - Semiconductor integrated circuit device: A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the... Agent: Miles & Stockbridge PC
20100061170 - Sense amplifier circuit and semiconductor memory device: A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second... Agent: Mcginn Intellectual Property Law Group, PLLC
20100061171 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary... Agent: F. Chau & Associates, LLC
20100061172 - Temperature detector in an integrated circuit: A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of... Agent: Guerin & Rodriguez, LLP
20100061173 - Auto-refresh control circuit and a semiconductor memory device using the same: An auto-refresh control circuit includes a control signal generating section configured to simultaneously or individually enable first and second control signals in response to an information combination signal having refresh information and operation mode information and first and second chip selection signals, and an auto-refresh signal generating section configured to... Agent: Baker & Mckenzie LLP Patent Department
20100061175 - Circuit and method for driving word line: A method for activating a word line inactivated with a negative voltage includes applying an intermediate voltage to the word line; and applying an activation voltage to the word line, wherein the intermediate voltage has a voltage level between the activation voltage and the negative voltage. A circuit and a... Agent: Ip & T Law Firm PLC
20100061176 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines that cross the word lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a... Agent: F. Chau & Associates, LLC
20100061174 - Y-decoder and decoding method thereof: AY-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100061177 - Semiconductor memory device and word line driving method thereof: A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal... Agent: Ip & T Law Firm PLC03/04/2010 > patent applications in patent subcategories.
20100054012 - Content addresable memory having programmable interconnect structure: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match... Agent: Mahamedi Paradice Kreisman LLP
20100054013 - Content addresable memory having selectively interconnected counter circuits: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit... Agent: Mahamedi Paradice Kreisman LLP
20100054011 - High speed sram: High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves... Agent: Juhan Kim
20100054014 - High density resistance based semiconductor device: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100054015 - Non-volatile memory device and method of operating the same: Provided is a non-volatile memory device that may include a plurality of variable resistors, each of the variable resistors having first and second terminals, the plurality of variable resistors arranged as a first layer of a plurality of layers and having data storage capability, at least one common bit plane... Agent: Harness, Dickey & Pierce, P.L.C
20100054019 - Resistance change memory device: A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100054017 - Semiconductor memory device: A semiconductor memory device comprising: a plurality of cell arrays having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between said first wirings and said second wirings, each containing a variable resistive element that is electrically rewritable and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100054020 - Semiconductor memory device: A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the... Agent: Knobbe Martens Olson & Bear LLP
20100054018 - Semiconductor memory device and information processing system: A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is divided into a plurality of areas capable... Agent: Sughrue Mion, PLLC
20100054016 - Semiconductor memory device having floating body type nmos transistor: A semiconductor memory device comprises a memory cell array and a sense amplifier circuit. The memory cell array includes a first NMOS transistor which has a gate electrode connected to a word line and has one source/drain region connected to a bit line. The sense amplifier circuit includes a second... Agent: Mcginn Intellectual Property Law Group, PLLC
20100054023 - Charge storage circuit, voltage stabilizer circuit, method for storing charge using the same: A charge storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a corresponding word line among the word lines and connected to a corresponding bit line among the bit lines. Each of the memory cells includes a transistor... Agent: Ip & T Law Firm PLC
20100054024 - Circuit for reading a charge retention element for a time measurement: A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100054021 - Memory device with multiple capacitor types: An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the... Agent: Coats & Bennett/qimonda
20100054022 - Method and apparatus for reducing charge trapping in high-k dielectric material: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether... Agent: Coats & Bennett/qimonda
20100054025 - Semiconductor integrated memory circuit and trimming method thereof: A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100054026 - Memory with separate read and write paths: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the... Agent: Campbell Nelson Whipps, LLC
20100054028 - Stt-mram bit cell having a rectangular bottom electrode plate and improved bottom electrode plate width and interconnect metal widths: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the... Agent: Qualcomm Incorporated
20100054027 - Symmetric stt-mram bit cell design: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are... Agent: Qualcomm Incorporated
20100054031 - Column decoder for non-volatile memory devices, in particular of the phase-change type: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates... Agent: Seed Intellectual Property Law Group PLLC
20100054029 - Concentric phase change memory element: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change... Agent: Scully, Scott, Murphy & Presser, P.C.
20100054030 - Programmable resistance memory: A memory includes a programmable resistance array and unipolar MOS peripheral circuitry. The peripheral circuitry includes address decoding circuitry. Because unipolar MOS circuitry is employed, the number of mask steps and, concomitantly, the cost of the programmable resistance memory may be minimized.... Agent: Ovonyx, Inc
20100054032 - Row decoder for non-volatile memory devices, in particular of the phase-change type: A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a... Agent: Seed Intellectual Property Law Group PLLC
20100054033 - Magnetic thin line and memory device: A magnetic thin line includes a first magnetic film having in-plane magnetic anisotropy and a second magnetic film that is magnetically coupled to the first magnetic film and has perpendicular magnetic anisotropy. With the coupling of the first magnetic film and the second magnetic film, magnetic wall width of the... Agent: Greer, Burns & Crain
20100054034 - Read circuit and read method: In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP
20100054035 - Semiconductor memory device: A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having... Agent: Sughrue Mion, PLLC
20100054037 - Flash memory device with multi level cell and burst access method therein: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words... Agent: Stanzione & Kim, LLP
20100054036 - Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby: Embodiments are directed to a method of programming a semiconductor memory device, the memory device including: a plurality of memory cell transistors arranged in a plurality of transistor strings; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the transistor strings;... Agent: Mills & Onello LLP
20100054038 - Programming of a charge retention circuit for a time measurement: A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second capacitive element, the dielectric of which has a higher capacitance than the first, the two elements having a common... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100054039 - High speed flash memory: For realizing high speed flash memory, bit line is multi-divided for reducing parasitic capacitance, so that local bit line is quickly discharged when reading a memory cell and multi-stage sense amps are used, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense... Agent: Juhan Kim
20100054040 - Method of programming and sensing memory cells using transverse channels and devices employing same: A first channel in the substrate underlying a trap gate is biased to cause trapping of holes or electrons in the trap gate and thereby program the memory device to a programmed state. A second channel in the substrate underlying the trap gate and transverse to the first channel is... Agent: Myers Bigel Sibley & Sajovec
20100054041 - Adjusting programming or erase voltage pulses in response to a rate of programming or erasing: Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A rate at which programming or erasing is proceeding is determined. The programming voltage pulse or the erase... Agent: Leffert Jay & Polglaze, P.A.
20100054042 - Semiconductor memory device and method of inspecting the same: A semiconductor memory device comprises a sense amplifier circuit having a first and a second input terminal, the sense amplifier configured to compare current flowing in the first input terminal with current flowing in the second input terminal, and the sense amplifier configured to provide the result to external; a... Agent: Turocy & Watson, LLP
20100054043 - Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in... Agent: Dla Piper LLP (us )
20100054044 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes setting an initial cell current level, performing program and erase operations for each word line of a memory block, storing the cycling number of the program and erase operations, comparing the cycling number with a critical cycling number of the program... Agent: Ip & T Law Firm PLC
20100054053 - Integrated circuit memory devices including mode registers set using a data input/output bus: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data... Agent: Myers Bigel Sibley & Sajovec
20100054046 - Data input circuit and semiconductor memory device including the same: A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for... Agent: Ip & T Law Firm PLC
20100054045 - Memory and reading method thereof: A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100054047 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal... Agent: Baker & Mckenzie LLP Patent Department
20100054048 - Method and apparatus for programming auto shut-off: A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A... Agent: Perkins Coie LLP Patent-sea
20100054049 - Semiconductor device: The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for... Agent: Miles & Stockbridge PC
20100054050 - Apparatus and method for providing power in semiconductor memory device: An apparatus for applying power in a semiconductor memory device includes a first power pin for receiving a first power at a first voltage from an external device, a second power pin for receiving a second power at the first voltage, a memory array block connected to the first power... Agent: Ip & T Law Firm PLC
20100054051 - Memory device and method thereof: The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes... Agent: Larson Newman & Abel, LLP
20100054052 - Semiconductor memory: A semiconductor memory is provided which includes a word line coupled to a transistor of a memory cell; a word driver configured to activate the word line; a first resistance portion configured to couple the word line to a low-level voltage line in accordance with an activation of the word... Agent: Arent Fox LLP
20100054054 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a plurality of word lines and a plurality of pairs of bit lines and complementary bit lines that cross the plurality of word lines. A plurality of memory cells is disposed at regions where the word lines and the pairs of bit lines and complementary... Agent: F. Chau & Associates, LLC
20100054055 - Data input/output circuit: A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission line unit having a clock tree structure for transmitting the internal clock to the output unit, a... Agent: Ip & T Law Firm PLC
20100054056 - Memory access strobe configuration system and process: A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by... Agent: Hewlett-packard Company Intellectual Property Administration
20100054060 - Delay locked loop and semiconductor memory device with the same: A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking... Agent: Ip & T Law Firm PLC
20100054057 - Memory sensing method and apparatus: Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the... Agent: Ryan, Mason & Lewis, LLP
20100054059 - Semiconductor memory device: A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of... Agent: Ip & T Law Firm PLC
20100054058 - Systems and methods for issuing address and data signals to a memory array: Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100054061 - Semiconductor memory device having bit test circuit with ignore function: A semiconductor memory device including a bit test circuit with an ignore function is provided. The semiconductor memory device includes a memory cell array and a bit test circuit. The memory cell array includes a plurality of memory cells. The bit test circuit is configured to perform a parallel bit... Agent: Harness, Dickey & Pierce, P.L.C
20100054063 - Semiconductor memory device, test method thereof and semiconductor device: A semiconductor memory device comprises a memory cell array having memory cells including a plurality of memory cells, and also comprises a first bit line, a first sense amplifier circuit and a control circuit. A signal is read out from a selected memory cell of the memory cell array through... Agent: Sughrue Mion, PLLC
20100054062 - Static random access memory (sram) and test method of the sram having precharge circuit to precharge bit line: An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply... Agent: Mcginn Intellectual Property Law Group, PLLC
20100054064 - Semiconductor memory device: A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first... Agent: Knobbe Martens Olson & Bear LLP
20100054065 - Sense amplifier circuit and semiconductor memory device: A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response... Agent: Mcginn Intellectual Property Law Group, PLLC
20100054066 - Memory device, semiconductor memory device and control method thereof: A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit... Agent: Mcginn Intellectual Property Law Group, PLLC
20100054067 - Methods and apparatuses for controlling fully-buffered dual inline memory modules: Methods and apparatuses are presented for controlling a fully buffered dual inline memory module. In one embodiment, the memory module may include at least two memory chips, a buffer coupled to the at least two memory chips (the buffer serially receiving data to be stored in the at least two... Agent: Dorsey & Whitney LLP On Behalf Of Sun Microsystems, Inc.
20100054068 - Temperature compensation of memory signals using digital signals: A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature.... Agent: Leffert Jay & Polglaze, P.A.
20100054069 - Memory system: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data... Agent: Miles & Stockbridge PC
20100054070 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100054071 - Semiconductor memory device: A semiconductor memory device is provided which has a memory cell region in which a plurality of memory cells are arranged in a matrix. The memory cell region is divided into a plurality of sectors each including a predetermined number of rows. Main bit lines extending in a column direction... Agent: Mcdermott Will & Emery LLP
20100054072 - Distributed block ram: Memory blocks, such as the embedded memory blocks in a reconfigurable device, are connected together using shared global busses and interface circuits. The interface circuits allow the memory blocks to be selectively connected together to form depth and width expanded memory blocks, and also allow the blocks to be used... Agent: Mcdermott Will & Emery LLP
20100054073 - Semiconductor memory device: A semiconductor memory device includes a clock inputting unit configured to receive a system clock and a data clock, a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock and determining a phase of the data division clock according to a... Agent: Ip & T Law Firm PLC
20100054074 - Voltage generation circuit and nonvolatile memory device including the same: A high voltage generation circuit includes a clock logic unit configured to generate a switch clock signal and a pump clock signal, that has a varying frequency, in response to an input signal, a high voltage unit configured to generate a high voltage in response to the pump clock signal,... Agent: Ip & T Law Firm PLCPrevious industry: Electric power conversion systems
Next industry: Agitating
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