|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
02/2010 | Recent | 14: | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval February patent applications/inventions, industry category 02/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/25/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100046265 - Separate cam core power supply for power saving: A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to... Agent: Mahamedi Paradice Kreisman LLP
20100046266 - High speed memory architecture: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a... Agent: Slater & Matsil, L.L.P.
20100046267 - Memory system with sectional data lines: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage... Agent: Vierra Magen/sandisk Corporation
20100046268 - Magnetic racetrack with current-controlled motion of domain walls within an undulating energy landscape: A method for use with a magnetic racetrack device includes placing domain walls having a first structure and domain walls having a second, different structure along the racetrack at stable positions corresponding to different regions within the device. The domain walls having the first structure and the domain walls having... Agent: Daniel E. Johnson IBM Corporation, Almaden Research Center
20100046269 - Programmable read only memory: An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the... Agent: Intel Corporation C/o Cpa Global
20100046270 - Resistance variable memory apparatus: A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a... Agent: Mcdermott Will & Emery LLP
20100046271 - Semiconductor memory device, method of manufacturing semiconductor memory device and method of writing data into semiconductor memory device: A method of manufacturing a semiconductor memory device including a ferroelectric random access memory serving as a ROM, the method comprising: writing data into the ferroelectric random access memory, the data having a polarity opposite to that of ROM data; performing bake processing for a predetermined time period; and writing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100046275 - Nonvolatile semiconductor storage apparatus and data programming method thereof: The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100046274 - Resistance change memory: A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a... Agent: Knobbe Martens Olson & Bear LLP
20100046273 - Resistance change nonvolatile memory device: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction,... Agent: Mcdermott Will & Emery LLP
20100046272 - Semiconductor memory device: A semiconductor memory device comprising a memory cell array of cross-point type having memory cells each composed of a variable resistive element for storing information in the form of variation of the electrical resistance. The operating current in the programming operation is reduced. Main data lines (GDL0 to GDL7) for... Agent: Nixon & Vanderhye, PC
20100046277 - Implementing local evaluation of domino read sram with enhanced sram cell stability: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100046278 - Implementing local evaluation of domino read sram with enhanced sram cell stability and enhanced area usage: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100046279 - Semiconductor memory device and trimming method thereof: When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100046276 - Systems and methods for handling negative bias temperature instability stress in memory bitcells: A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one... Agent: Qualcomm Incorporated
20100046281 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs.... Agent: Sughrue Mion, PLLC
20100046280 - Sram yield enhancement by read margin improvement: A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line... Agent: Qualcomm Incorporated
20100046282 - Cross-point magnetoresistive memory: A ferromagnetic thin-film based digital memory system having memory cells interconnected in a grid that are selected through voltage values supplied coincidently on interconnections made thereto for changing states thereof and determining present states thereof through suitable biasing of grid interconnections.... Agent: Kinney & Lange, P.A.
20100046283 - Magnetic random access memory and operation method of the same: A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at... Agent: Sughrue Mion, PLLC
20100046284 - Mram: An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells.... Agent: Mr. Jackson Chen
20100046285 - Multiple phase change materials in an integrated circuit for system on a chip application: Integrated circuits are described along with methods for manufacturing. An integrated circuit as described herein includes a plurality of memory cells on a substrate. The plurality of memory cells comprise a first set of memory cells comprising a first memory material, and a second set of memory cells comprising a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100046286 - Resistive memory devices using assymetrical bitline charging and discharging: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a... Agent: Myers Bigel Sibley & Sajovec
20100046287 - Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating... Agent: Law Office Of Alan W. Cannon
20100046288 - Magnetic random access memory and method of manufacturing the same: An MRAM according to the present invention has a pinned layer 60 and a magnetic recording layer 40 connected to the pinned layer 60 through a tunnel barrier layer 50. The magnetic recording layer 40 has a first free layer 10, a second free layer 30 being in contact with... Agent: Mr. Jackson Chen
20100046291 - Process and temperature tolerant non-volatile memory: A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory... Agent: Ip Legal Services
20100046292 - Non-volatile memory device and bad block remapping method: A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad... Agent: Lee & Morse, P.C.
20100046293 - Memory cell block of nonvolatile memory device and method of managing supplementary information: A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information... Agent: Ip & T Law Firm PLC
20100046295 - Fast data access mode in a memory device: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access... Agent: Leffert Jay & Polglaze, P.A.
20100046294 - Non-volatile memory device and method of operating the same: A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes... Agent: Volentine & Whitt PLLC
20100046296 - Method for reading and programming a memory: A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100046297 - Non-volatile memory and method for ramp-down programming: A ramp-down programming voltage is used to program a group of nonvolatile memory cells in parallel, step by step from a highest step to a lowest step. Overall programming time is improved when a conventional setup for program inhibit together with a verify after each program step are avoided. A... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100046298 - Non-volatile semiconductor memory circuit: Provided is a non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof by connecting a constant current circuit (1) and a non-volatile memory cell (2) in series, and setting a connection point therebetween to be an output, to thereby enable writing, in a reading... Agent: Bruce L. Adams, Esq Adams & Wilks
20100046299 - Programming rate identification and control in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement... Agent: Leffert Jay & Polglaze, P.A.
20100046301 - Intelligent control of program pulse for non-volatile storage: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of... Agent: Vierra Magen/sandisk Corporation
20100046300 - Reduction of quick charge loss effect in a memory device: Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20100046290 - Flash memory device and memory system: A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first... Agent: Volentine & Whitt PLLC
20100046289 - Method of reading nonvolatile memory device and method of operating nonvolatile memory device: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are... Agent: Ip & T Law Firm PLC
20100046302 - Complementary reference method for high reliability trap-type non-volatile memory: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.... Agent: Saile Ackerman LLC
20100046303 - Program-verify method: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one... Agent: Fletcher Yoder (micron Technology, Inc.)
20100046305 - Erase operation in a flash drive memory: A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The... Agent: Leffert Jay & Polglaze, P.a Attn: Kenneth W. Bolvin
20100046304 - Non-volatile memory device and erase method: Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The... Agent: Volentine & Whitt PLLC
20100046308 - One-transistor type dram: A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column... Agent: Ip & T Law Firm PLC
20100046307 - Semiconductor memory and system: A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line... Agent: Arent Fox LLP
20100046306 - Semiconductor storage device: It has been conventionally difficult to make circuits operate faster. The present invention is a semiconductor storage device including a reference voltage circuit that supplies a reference voltage, and first and second memory circuits, that performs a read/write operation when one of the first and second memory circuits is selected,... Agent: Foley And Lardner LLP Suite 500
20100046309 - Reset circuit for termination of tracking circuits in self timed compiler memories: A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one embodiment, a method of timing the precharging of BLs in a self timed compiler memory array includes initiating an internal clock during the start of... Agent: Krishnan S. Rengarajan
20100046310 - Semiconductor memory device including memory cell array having dynamic memory cell, and sense amplifier thereof: A semiconductor memory device and a sense amplifier thereof are provided. The semiconductor memory device includes a memory cell array and a plurality of sense amplifiers. The memory cell array includes a memory cell array block having a plurality of memory cells. Each of the plurality of sense amplifiers is... Agent: Harness, Dickey & Pierce, P.L.C
20100046311 - On-chip temperature sensor: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level... Agent: Leffert Jay & Polglaze, P.A.
20100046312 - Dynamic and non-volatile random access memories with an increased stability of the mos memory cells: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number... Agent: Glenn Patent Group
20100046313 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a... Agent: Ip & T Law Firm PLC
20100046314 - Memory device having a read pipeline and a delay locked loop: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal.... Agent: Morgan Lewis & Bockius LLP/rambus Inc.02/18/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100039845 - Integrated circuit with bit lines positioned in different planes: An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is... Agent: Dicke, Billig & Czaja
20100039846 - Method and apparatus for non-volatile multi-bit memory: A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100039847 - Method of manufacturing a single chip semiconductor integrated circuit device including a mask rom in a short time: In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit... Agent: Frishauf, Holtz, Goodman & Chick, PC
20100039848 - Non-volatile programmable optical element employing f-centers: A non-volatile programmable electro-optical element alters absorption characteristics of an optical medium that comprises a doped transition metal oxide material including F-centers. The F-centers are electrostatically moved into or out of the regions containing a wavefunction of an optical beam. A specific F-center profile in the transition metal oxide material... Agent: Scully, Scott, Murphy & Presser, P.C.
20100039849 - Read/write elements for a three-dimensional magnetic memory: Read/write elements for three-dimensional magnetic memories are disclosed. One embodiment describes an array of integrated read/write elements. The array includes read conductors formed proximate to one of the layers (i.e., storage stacks) of the three-dimensional magnetic memory. The array also includes flux caps formed proximate to the read conductors, and... Agent: Duft Bornsen & Fishman, LLP
20100039851 - Semiconductor memory: A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100039850 - Semiconductor memory device with ferroelectric memory: A semiconductor memory device includes plural word lines, plural first bit lines, plural plate lines formed corresponding to the word lines, plural second bit lines formed corresponding to the first bit lines, plural first ferroelectric capacitors each including a ferroelectric film between two electrodes, plural cell transistor formed corresponding to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100039852 - Dynamic memory cell methods: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater... Agent: Ryan, Mason & Lewis, LLP
20100039853 - Design structure, structure and method of using asymmetric junction engineered sram pass gates: A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain;... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C
20100039854 - Structure, structure and method of using asymmetric junction engineered sram pass gates: A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The structure includes an SRAM cell having asymmetric junction-engineered SRAM pass gates with a high leakage junction and a low leakage junction. The asymmetric junction-engineered SRAM pass gates are connected... Agent: Greenblum & Bernstein, P.L.C
20100039855 - Exchange-assisted spin transfer torque switching: In general, the invention is directed to techniques for reducing the amount of switching current that is utilized within a magnetic storage (e.g., MRAM) device. An example apparatus includes a fixed magnetic layer that provides a fixed direction of magnetization, an exchange-coupled magnetic multi-layer structure, and a non-magnetic layer placed... Agent: Shumaker & Sieffert, P. A.
20100039856 - Programmable phase-change memory and method therefor: A non-volatile memory is disclosed. A contiguous layer of phase change material (21; 31; 61; 71; 81) is provided. Proximate the contiguous layer of phase change material (21; 31; 61; 71; 81) is provided a first pair of contacts (22; 32; 62; 72; 82) for providing an electrical current therebetween,... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100039857 - Write circuit for providing distinctive write currents to a chalcogenide memory cell: A write circuit for providing distinctive write currents to a chalcogenide memory cell is disclosed. The write circuit includes a current amplitude trim module, a current amplification and distribution module, and a write current shaping module. The current amplitude trim module provides a well-compensated current across a predetermined range of... Agent: Bae Systems
20100039858 - Fast programming memory device: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line,... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP
20100039859 - System and method for programming cells in non-volatile integrated memory devices: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20100039860 - Memory devices and methods of storing data on a memory device: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original... Agent: Knobbe Martens Olson & Bear LLP
20100039861 - Nonvolatile memory device and read method: Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile... Agent: Volentine & Whitt PLLC
20100039862 - Read operation for nand memory: Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential... Agent: Leffert Jay & Polglaze, P.A.
20100039863 - Mitigation of runaway programming of a memory device: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by... Agent: Leffert Jay & Polglaze, P.A.
20100039864 - Methods of erase verification for a flash memory device: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase... Agent: Knobbe Martens Olson & Bear LLP
20100039865 - Non-volatile semiconductor memory device and method of making the same: A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100039866 - Sensing of memory cells in a solid state memory device by fixed discharge of a bit line: In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit... Agent: Leffert Jay & Polglaze, P.A.
20100039867 - Electrically isolated gated diode nonvolatile memory: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells,... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100039868 - Low voltage, low power single poly eeprom: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell (FIGS. 1-2) is disclosed. The memory cell includes a sense transistor (152) having a source (110), a drain (108), and a control gate layer (156). The memory cell includes a first lightly doped region (160) having a first conductivity type... Agent: Texas Instruments Incorporated
20100039869 - Multi-state memory cell with asymmetric charge trapping: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the... Agent: Leffert Jay & Polglaze, P.A.
20100039870 - Memory control circuit and semiconductor integrated circuit incorporating the same: A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a significant state of a data strobe... Agent: Taft, Stettinius & Hollister LLP
20100039871 - Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line,... Agent: Mcginn Intellectual Property Law Group, PLLC
20100039872 - Dual power scheme in memory circuit: A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals. Write drivers receive low level data input signals and... Agent: Qualcomm Incorporated
20100039873 - Sense amplifier driving control circuit and method: A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a... Agent: Ip & T Law Firm PLC
20100039874 - Memory with shared read/write circuit: A memory includes memory cells arranged as a matrix of rows and columns between word lines and bit lines, and a set of differential read/write amplifiers for reading and writing of the memory cells and for communicating with local bit lines common to at least some of the memory cells.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100039875 - Strobe acquisition and tracking: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable... Agent: Morgan Lewis & Bockius LLP/rambus Inc.
20100039876 - Functional float mode screen to test for leakage defects on sram bitlines: A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge... Agent: Ibm Corporation
20100039877 - External clock tracking pipelined latch scheme: A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second... Agent: Schwegman, Lundberg & Woessner/micron
20100039878 - Circuit and method for generating data output control signal for semiconductor integrated circuit: The data output control signal generating circuit include sa delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock, and latches the delayed signal to generate a plurality of output enable signals. A column address strobe latency... Agent: Venable LLP02/11/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100034004 - Semiconductor memory device of open bit line type: There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word... Agent: Sughrue Mion, PLLC
20100034005 - Semiconductor memory apparatus for controlling pads and multi-chip package having the same: A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding... Agent: Baker & Mckenzie LLP Patent Department
20100034006 - Semiconductor memory device: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier... Agent: Young & Thompson
20100034007 - Quantum optical data storage: The present invention provides a quantum optical data storage protocol, whose storage time is lengthened by spin population decay time from several minutes to several hours. The quantum data storage includes a first ground state and a second ground state which are closely spaced each other in energy level or... Agent: Vierra Magen Marcus & Deniro LLP
20100034008 - Magnetic field assisted stram cells: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a... Agent: Campbell Nelson Whipps, LLC
20100034009 - Asymmetric write current compensation using gate overdrive for resistive sense memory cells: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, PC (seagate Technology LLC)
20100034010 - Memory devices with concentrated electrical fields: Designs of resistance memory and phase change memory devices with memory cells having metallic inclusion at least in the area of electrode/medium layer interfaces. Such metallic inclusion is used to concentrate electric fields during writing. Consequently, resistance switching for the devices primarily occurs in the area of the metallic inclusion.... Agent: Intellectual Property Group Seagate Technology Files
20100034011 - Multi-terminal resistance device: Embodiments of the invention provide a multi-terminal resistance device with first and second electrodes, a shared third electrode, and a resistance layer providing first and second current paths between the shared third electrode and the first and second electrodes, respectively. A current state of the device may be programmed by... Agent: Intellectual Property Group Seagate Technology Files
20100034012 - Semiconductor memory device: A nonvolatile semiconductor memory device having a plurality of unit cell arrays having memory cells each containing a first wiring and a second wiring intersecting each other, and a variable resistive element arranged at each intersection of said first wiring and said second wiring and electrically rewritable to nonvolatilely store... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100034013 - Optical refreshing of loadless for transistor sram cells: Loadless 4 transistor SRAM cell operation can be substantially improved yielding area saving and more stable operation by use of optical-light load. Parasitic photocurrents in PMOS anodes-substrate junctions act as load currents. Light can be introduced by either ambient light through transparent window on top of the chip or by... Agent: Goran Krilic
20100034014 - Magnetoresistive element, magnetic memory cell and magnetic random access memory using the same: Provided is a high-speed and ultra-low-power-consumption nonvolatile memory having a high temperature stability at a zero magnetic field. In a tunnel magnetoresistive film constituting a nonvolatile magnetic memory that employs a writing method using a spin-transfer torque, an insulating layer and a nonmagnetic conductive layer are stacked above a ferromagnetic... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100034015 - Semiconductor device: The invention provides a semiconductor device having a lower probability of erroneous inversion of data signal. The MRAM disclosed herein comprises (m+1)×(n+1) memory cells arranged in (m+1) rows and (n+1) columns, digit lines respectively provided in the rows, and bit lines respectively provided in the columns. A magnetizing current Im... Agent: Mcdermott Will & Emery LLP
20100034016 - Phase change memory structures and methods: Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various... Agent: Brooks, Cameron & Huebsch , PLLC
20100034017 - Oscillating current assisted spin torque magnetic memory: A memory unit having a spin torque memory cell with a ferromagnetic free layer, a ferromagnetic pinned layer and a spacer layer therebetween, with the free layer having a switchable magnetization orientation with a switching threshold. A DC current source is electrically connected to the spin torque memory cell to... Agent: Campbell Nelson Whipps, LLC
20100034020 - Semiconductor memory device including charge storage layer and control gate: A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100034019 - Systems and methods for performing a program-verify process on a nonvolatile memory by selectively pre-charging bit lines associated with memory cells during the verify operations: A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.... Agent: Myers Bigel Sibley & Sajovec
20100034021 - Method of controlling operation of flash memory device: According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to... Agent: Ip & T Law Firm PLC
20100034022 - Compensating for coupling during read operations in non-volatile storage: Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on... Agent: Vierra Magen/sandisk Corporation
20100034024 - Control method for nonvolatile memory and semiconductor device: In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time access to the nonvolatile memory is performed, the controller determines... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100034025 - Non-volatile semiconductor storage system: There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile memory comprises a status output section configured to output status information indicating a status of read operation, write operation or erase operation in the non-volatile memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100034023 - Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100034018 - Accessing memory using fractional reference voltages: Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus... Agent: Kraguljac & Kalnay, LLC - Marvell
20100034026 - Erase method and non-volatile semiconductor memory: An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags,... Agent: Volentine & Whitt PLLC
20100034027 - Method for programming a nonvolatile memory: A method for programming a nonvolatile memory is provided. The method includes applying at least a voltage to a source or a drain, so as to inject carriers of the source or drain into a substrate; applying a third voltage to a gate or the substrate, so that the carriers... Agent: Juan Carlos A. Marquez C/o Stites & Harbison PLLC
20100034028 - Method for driving nonvolatile semiconductor memory device: In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100034029 - Static random access memory (sram) of self-tracking data in a read operation, and method thereof: The self-tracking data selection SRAM, comprising: a plurality of memory cell arrays, comprising: a plurality of memory cells each generating a first signal and outputting a first read data; a plurality of first buffers each receiving the first signal outputting a second signal; a first multiplexer receiving the plurality of... Agent: Patterson & Sheridan, L.L.P.
20100034030 - Double edge triggered flip-flop circuit: In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either... Agent: Mcdermott Will & Emery LLP
20100034031 - Semiconductor memory device: A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having... Agent: Lee & Morse, P.C.
20100034032 - Data output circuit in a semiconductor memory apparatus: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when... Agent: Ip & T Law Firm PLC
20100034034 - Methods, circuits, and systems to select memory regions: Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100034033 - Receiver of semiconductor memory apparatus: A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the... Agent: Venable LLP
20100034035 - Address latch circuit and semiconductor memory apparatus using the same: An address latch circuit of a semiconductor memory apparatus includes a control signal generating section configured to generate a control signal in response to an external command signal and a RAS idle signal, a clock control section configured to output a clock signal as a control clock signal when the... Agent: Baker & Mckenzie LLP Patent Department
20100034036 - Semiconductor integrated circuit device for controlling a sense amplifier: A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the... Agent: Baker & Mckenzie LLP Patent Department
20100034038 - Integrated circuit including selectable address and data multiplexing mode: An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory... Agent: Dicke, Billig & Czaja
20100034037 - Semiconductor testing device and method of testing semiconductor memory: The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of... Agent: Birch Stewart Kolasch & Birch
20100034039 - Semiconductor integrated circuit: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of... Agent: Foley And Lardner LLP Suite 500
20100034040 - Semiconductor integrated circuit: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data... Agent: Young & Thompson
20100034041 - Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a... Agent: Law Office Of Alan W. Cannon
20100034042 - Power consumption-oriented management of a storage system: A method of managing operation of a plurality of devices that includes receiving operational information that pertains to each of a plurality of device and managing operation of at least one of the plurality of devices. Each of the plurality of devices is configured to perform operations, the operations including... Agent: Beyer Law Group LLP/ Sandisk
20100034044 - Semiconductor device: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this... Agent: Miles & Stockbridge PC
20100034043 - Semiconductor ic device having power-sharing and method of power-sharing thereof: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to... Agent: Baker & Mckenzie LLP Patent Department
20100034045 - Semiconductor memory and memory system: A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups... Agent: Fujitsu Patent Center C/o Cpa Global02/04/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100027307 - Memory detecting circuit: A memory detecting circuit includes five switch elements and two indication devices. A first switch element is connected to a standby power, and also connected to memory sockets of a first channel to receive a first memory detecting signal. A second switch element is connected to the first switch element... Agent: PCe Industry, Inc. Att. Steven Reiss
20100027308 - Semiconductor storage device: A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100027309 - Semiconductor memory device including plurality of memory chips: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a... Agent: Volentine & Whitt PLLC
20100027310 - Apparatus and methods for optically-coupled memory systems: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein,... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100027311 - Integrated circuit and method of forming an integrated circuit: An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of... Agent: Dicke, Billig & Czaja
20100027312 - Compact virtual ground diffusion programmable rom array architecture, system and method: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared... Agent: Shreen K. Danamraj The Danamraj Law Group , P.C.
20100027313 - F-sram before package solid data write: A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same... Agent: Texas Instruments Incorporated
20100027316 - Non-volatile memory device and method of operating the same: A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to... Agent: F. Chau & Associates, LLC
20100027318 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100027314 - Preservation circuit and methods to maintain values representing data in one or more layers of memory: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power.... Agent: Unity Semiconductor Corporation
20100027319 - Resistance change element, method for manufacturing the same, and semiconductor memory: A resistance change element including a first electrode; a second electrode; and an oxide film, including an oxide of the first electrode, formed at sides of the first electrode and sandwiched between the first electrode and the second electrode in a plurality of regions, wherein at least one of the... Agent: Fujitsu Patent Center C/o Cpa Global
20100027320 - Resistance variable element, resistance variable memory apparatus, and resistance variable apparatus: A resistance variable element (10), a resistance variable memory apparatus, and a resistance variable apparatus, comprise a first electrode (2), a second electrode (4), and a resistance variable layer (3) which is disposed between the first electrode (2) and the second electrode (4) and is electrically connected to the first... Agent: Mcdermott Will & Emery LLP
20100027315 - Resistive memory device and writing method thereof: A resistive memory device operates to sequentially activate bit lines, which are divided into plural groups, after precharging all of word and bit lines in a writing operation. The device is able to write a large amount of data therein at a high frequency, with a reduced the chip size.... Agent: Harness, Dickey & Pierce, P.L.C
20100027317 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100027321 - Non-volatile single-event upset tolerant latch circuit: A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first... Agent: Bae Systems
20100027322 - Semiconductor integrated circuit and manufacturing method therefor: In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and... Agent: Miles & Stockbridge PC
20100027323 - Magnetic recording element: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic... Agent: Rossi, Kimms & Mcdowell LLP.
20100027324 - Variable integrated analog resistor: The invention relates to the use of chalcogenide devices exhibiting negative differential resistance in integrated circuits as programmable variable resistor components. The present invention is a continuously variable integrated analog resistor made of a chalcogenide material, such as a GeSeAg alloy. Continuously variable resistor states are obtained in the material... Agent: Pedersen & Company, PLLC
20100027325 - Integrated circuit including an array of memory cells and method: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line... Agent: Dicke, Billig & Czaja
20100027326 - Memory device, memory system having the same, and programming method of a memory cell: A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of... Agent: Lee & Morse, P.C.
20100027328 - Multilevel variable resistance memory cell utilizing crystalline programming states: A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values... Agent: Ovonyx, Inc
20100027327 - Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same: Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an... Agent: Myers Bigel Sibley & Sajovec
20100027329 - Synchronous page-mode phase-change memory with ecc and ram cache: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode... Agent: Stuart T Auvinen
20100027330 - Magnetic memory device and method for reading magnetic memory cell using spin hall effect: A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic... Agent: Renner Otto Boisselle & Sklar, LLP
20100027331 - Memory and reading method thereof: A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100027332 - Flash memory programming: A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and... Agent: F. Chau & Associates, LLC
20100027333 - Nonvolatile semiconductor memory device: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20100027334 - Eeprom charge retention circuit for time measurement: An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100027335 - Memory device and wear leveling method: The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased,... Agent: Harness, Dickey & Pierce, P.L.C
20100027336 - Non-volatile memory device and associated programming method using error checking and correction (ecc): A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the... Agent: Lee & Morse, P.C.
20100027337 - Nonvolatile memory device extracting parameters and nonvolatile memory system including the same: The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one... Agent: Harness, Dickey & Pierce, P.L.C
20100027338 - Semiconductor device and a manufacturing method thereof: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100027339 - Page buffer and method of programming and reading a memory: A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100027341 - Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system: A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100027340 - Pattern dependent string resistance compensation: Pattern dependent string resistance compensation of a memory device is generally described. In one example, an electronic device includes a first string of memory cells and a first bit line coupled with the first string of memory cells wherein a memory cell of the first string of memory cells is... Agent: Cool Patent, P.C. C/o Cpa Global
20100027346 - Asymmetric single poly nmos non-volatile memory cell: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20100027345 - Erasable non-volatile memory device using hole trapping in high-k dielectrics: A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K.... Agent: Schwegman, Lundberg & Woessner/micron
20100027342 - Memory device and memory data determination method: A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may... Agent: Harness, Dickey & Pierce, P.L.C
20100027343 - Non-volatile memory monitor: The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular characteristics, and returning to the normal operating state. Alternative... Agent: Michael T. Konczal, Patent Attorney
20100027344 - Semiconductor memory device: A drain voltage generator circuit includes a first switching element coupled between a first power supply voltage and an output end of the drain voltage generator circuit, a second switching element coupled in parallel to the first switching element and having a smaller current capability than that of the first... Agent: Mcdermott Will & Emery LLP
20100027347 - Three-terminal single poly nmos non-volatile memory cell: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20100027348 - Program method of flash memory device: A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory... Agent: Ip & T Law Firm PLC
20100027349 - current sensing scheme for non-volatile memory: A current sensing scheme for non-volatile memory is disclosed comprising an apparatus for determining one or more memory cell states in a non-volatile memory device. The apparatus having a first memory cell coupled to a first bitline and a first sensing element coupled to the first bitline, the first sensing... Agent: Cool Patent, P.C. C/o Cpa Global
20100027350 - Flash memory programming and verification with reduced leakage current: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100027351 - Memory device and memory programming method: A memory device and a memory programming method are provided. The memory device may program data in a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. The memory device may include a memory cell array, a programming unit and a program level stabilization unit. The memory cell array... Agent: Harness, Dickey & Pierce, P.L.C
20100027352 - Non-volatile semiconductor memory device: In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality... Agent: Mcdermott Will & Emery LLP
20100027353 - Erase method of flash device: In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate... Agent: Ip & T Law Firm PLC
20100027355 - Planar double gate transistor storage cell: A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor... Agent: Fsi C/o Jackson Walker, L.L.P.
20100027354 - Semiconductor memory device and method for testing same: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The... Agent: Sughrue Mion, PLLC
20100027356 - Dynamic on-die termination of address and command signals: A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of... Agent: Morgan Lewis & Bockius LLP/rambus Inc.
20100027357 - Memory system having distributed read access delays: A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on... Agent: Law Offices Of Mark L. Berrier
20100027358 - Semiconductor memory device capable of read out mode register information through dq pads: A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a... Agent: Cooper & Dunham, LLP
20100027359 - Memory test circuit which tests address access time of clock synchronized memory: A circuit for testing an access time of a clock synchronization type memory, includes a delay circuit, a sampling circuit and a coincidence detection circuit. The delay circuit generates a delayed clock obtained by delaying, by a time acceptable for a memory performance, a clock inputted to a memory. The... Agent: Mcginn Intellectual Property Law Group, PLLC
20100027361 - Information handling system with sram precharge power conservation: An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20100027360 - Integrated circuit having an array supply voltage control circuit: An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line... Agent: Freescale Semiconductor, Inc. Law Department
20100027362 - Semiconductor memory device for low voltage: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device... Agent: Ip & T Law Firm PLC
20100027364 - Multi-port memory device having self-refresh mode: The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100027363 - Refresh controller and refresh controlling method for embedded dram: The present invention provides a refresh controller for embedded DRAM, configured to receive an external access signal and generate refresh enabling signal REFN, refresh address signal CRA and confliction signal, said embedded DRAM comprising a plurality of memory groups, said controller comprising: a status controlling module that generates refresh enabling... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20100027365 - Non-volatile memory device capable of supplying power: A non-volatile memory device capable of supplying power is provided. The non-volatile memory device includes an electrical storage device for supplying a stored power, a charging control circuit coupled to the electrical storage device, a non-volatile memory, an input/output (I/O) interface, and a power control circuit. The I/O interface connects... Agent: J C Patents
20100027366 - Semiconductor memory device: In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The... Agent: Mcdermott Will & Emery LLP
20100027367 - Row mask addressing: Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron
20100027368 - Read command triggered synchronization circuitry: A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting... Agent: Ropes & Gray LLP
20100027369 - Semiconductor integrated circuit device: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit... Agent: Miles & Stockbridge PCPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20141002:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.49309 seconds