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Static information storage and retrieval January recently filed with US Patent Office 01/10

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/28/2010 > patent applications in patent subcategories. recently filed with US Patent Office

20100020583 - Stacked memory module and system: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system.... Agent: Law Office Of Monica H Choi

20100020584 - High speed memory module: A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three positions for connecting memory modules. A plurality of memory chips may be mounted on the circuit board.... Agent: SocalIPLaw Group LLP

20100020585 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: Fish & Richardson P.C.

20100020586 - Fb dram memory with state memory: A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory... Agent: Slater & Matsil, L.L.P.

20100020587 - Semiconductor memory device: A ferroelectric memory is provided with a voltage generating circuit configured to generate prescribed driving potential, a driving interconnection to which the driving potential is applied, a plurality of memory cells connected to the driving interconnections and an internal voltage comparison circuit configured to compare inputted potential and to output... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020588 - Semiconductor memory device: A semiconductor memory device includes cell blocks configured to have a plurality of memory cells connected in series, each memory cell comprising a ferroelectric capacitor and a cell transistor connected in parallel with each other; word lines connected to gates of a plurality of the cell transistors; block selectors connected... Agent: Knobbe Martens Olson & Bear LLP

20100020589 - Semiconductor memory device: The sense amplifier detects and amplifies a signal read via bit lines from the ferroelectric capacitor of the memory cell. The dummy capacitor provides a reference voltage to bit lines. The dummy capacitor includes a first dummy capacitor and a second dummy capacitor. The first dummy capacitor is provided with... Agent: Knobbe Martens Olson & Bear LLP

20100020591 - Adaptive voltage control for sram: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array,... Agent: Texas Instruments Incorporated

20100020590 - Sram with improved read/write stability: A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source,... Agent: K&l Gates LLPIPDocketing

20100020592 - Magnetic random access memory and write method of the same: A first magnetic layer has a magnetization fixed along one direction. A first nonmagnetic layer on the first magnetic layer functions as a first tunnel barrier. A second magnetic layer on the first nonmagnetic layer has a magnetization whose direction can be reversed by spin transfer current injection. A second... Agent: Knobbe Martens Olson & Bear LLP

20100020595 - Accessing a phase change memory: A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying... Agent: Kevin L. Bray Energy Conversion Devices, Inc.

20100020594 - Device for programming a pcm cell with discharge of capacitance and method for programming a pcm cell: A device for programming PCM cells includes a pulse-generator circuit for supplying programming current pulses. The pulse-generator circuit includes: at least one first capacitive element; a charging circuit, connectable to the first capacitive element in a first operating condition, for bringing a reference voltage on the first capacitive element to... Agent: Seed Intellectual Property Law Group PLLC

20100020593 - Vertical string phase change random access memory device: A phase change random access memory device is disclosed including a first electrode, a second electrode, a phase change material layer between the first and second electrode, a plurality of gate layers formed along the phase change material layer, an insulating film between the phase change material layer and the... Agent: Harness, Dickey & Pierce, P.L.C

20100020596 - Non-volatile magnetic memory device: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second... Agent: Morgan Lewis & Bockius LLP

20100020597 - Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions... Agent: Neil Steinberg

20100020601 - Multi-bit flash memory devices and methods of programming and erasing the same: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further... Agent: Myers Bigel Sibley & Sajovec

20100020599 - Multi-level flash memory: A multi-level flash memory comprises a semiconductor substrate, a gate structure having a lower block positioned in the semiconductor substrate and an upper block positioned on the semiconductor substrate, and a plurality of storage structures separated by the gate structure. The upper block connects to the lower block of the... Agent: Wpat, PC Intellectual Property Attorneys

20100020602 - Non-volatile memory devices and programming methods for the same: The non-volatile memory device includes a plurality of memory cells. Each of the memory cells is configured to achieve one of a plurality of states, and each of the states represents different multi-bit data. In one embodiment, the method of programming includes simultaneously programming (1) a first memory cell from... Agent: Harness, Dickey & Pierce, P.L.C

20100020605 - Non-volatile multilevel memory cell programming: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell... Agent: Brooks, Cameron & Huebsch , PLLC

20100020603 - Nonvolatile semiconductor memory and data writing method for nonvolatile semiconductor memory: A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data across drain-source terminals of... Agent: Volentine & Whitt PLLC

20100020600 - Programming method of non-volatile memory device: A programming method of a non-volatile memory device having a drain select transistor, a source select transistor, and a plurality of memory cells connected between the drain select transistor and the source select transistor includes applying a program voltage, which increases stepwise according to a repetition of a program cycle,... Agent: Ip & T Law Firm PLC

20100020604 - Shifting reference values to account for voltage sag: A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is... Agent: Fish & Richardson P.C.

20100020606 - Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same: A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100020608 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes:... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020609 - Flash memory device with redundant columns: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality... Agent: Knobbe Martens Olson & Bear LLP

20100020611 - Flash memory systems and operating methods using adaptive read voltage levels: Some embodiments of the present invention provide methods of operating nonvolatile memory devices. Reference data is stored in a plurality of memory cells. The reference data is read, and a threshold voltage distribution of the plurality of memory cells is determined responsive to reading the reference data. A read voltage... Agent: Myers Bigel Sibley & Sajovec

20100020610 - Integrated circuits having a controller to control a read operation and methods for operating the same: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and... Agent: Slater & Matsil, L.L.P.

20100020612 - Non-volatile semiconductor memory device: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020613 - Starting program voltage shift with cycling of non-volatile memory: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period... Agent: Vierra Magen/sandisk Corporation

20100020614 - Non-volatile memory with linear estimation of initial programming voltage: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100020615 - Clock synchronized non-volatile memory device: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs... Agent: Brundidge & Stanger, P.C.

20100020616 - Soft errors handling in eeprom devices: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100020598 - Semiconductor device and control method of the same: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100020618 - Non-volatile memory device and memory system: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory... Agent: Volentine & Whitt PLLC

20100020617 - Nonvolatile semiconductor device and memory system including the same: A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines.... Agent: F. Chau & Associates, LLC

20100020619 - Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus: A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020620 - Memory device and method of programming thereof: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first... Agent: Harness, Dickey & Pierce, P.L.C

20100020607 - Method and apparatus for adaptive memory cell overerase compensation: A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100020621 - Memory device bit line sensing system and method that compensates for bit line resistance variations: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100020623 - Circuit and method of generating voltage of semiconductor memory apparatus: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and... Agent: Venable LLP

20100020622 - One-transistor type dram: A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a... Agent: Ip & T Law Firm PLC

20100020624 - Read enhancement for memory: An electronic circuitry is provided for reading out a memory element (ME). The electronic circuitry comprises a first electronic path (IP) being coupled to the memory element (ME), a second electronic path (RP) having predetermined electrical properties, and a basic detection element (BDE) being coupled to the first and second... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100020625 - Electronic circuit device: The electronic circuit device includes: a burst detecting circuit 7 for detecting, from an input and output terminal 4, a prescribed write activation burst having a length that is larger than or equal to a prescribed time; a signal-pattern detecting circuit 9 for putting a serial interface 8 into an... Agent: Kratz, Quintos & Hanson, LLP

20100020626 - Input/output line sense amplifier and semiconductor memory device using the same: An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O... Agent: Cooper & Dunham, LLP

20100020627 - Semiconductor memory device: A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection between a first voltage source and a first determination node be in a conductive or a non-conductive state based on a logic value of the information data; second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020628 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100020629 - Word line driver circuit: A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The... Agent: Jianq Chyun Intellectual Property Office

  
01/21/2010 > patent applications in patent subcategories. recently filed with US Patent Office

20100014339 - Semiconductor memory device and memory access method: A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input... Agent: Mcginn Intellectual Property Law Group, PLLC

20100014340 - Quad sram based one time programmable memory: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100014341 - Semiconductor memory device: A memory includes word lines; plate lines; first to eighth bit lines; cell transistors; ferroelectric capacitor connected in parallel with cell transistors; sense amplifiers, wherein cell transistors and ferroelectric capacitors configure cells, the cells are connected in series to configure first to eighth cell blocks, the cell blocks are connected... Agent: Knobbe Martens Olson & Bear LLP

20100014342 - Semiconductor storage device: A memory includes a cell block comprises memory cells connected in series; block select transistors connected to one ends of the cell blocks; bit lines; plate lines; a sense amplifier comprises an N-type sensor and a P-type sensor, the N-type sensor applying a low-level potential to the bit line, and... Agent: Knobbe Martens Olson & Bear LLP

20100014343 - Nonvolatile memory apparatus and nonvolatile data storage medium: [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to... Agent: Mcdermott Will & Emery LLP

20100014344 - Switchable two terminal multi-layer perovskite thin film resistive device and methods thereof: A switchable resistive device has a multi-layer thin film structure interposed between an upper conductive electrode and a lower conductive electrode. The multi-layer thin film structure comprises a perovskite layer with one buffer layer on one side of the perovskite layer, or a perovskite layer with buffer layers on both... Agent: Gardere Wynne-houston

20100014345 - Nonvolatile memory device with temperature controlled column selection signal levels: A nonvolatile memory device includes a memory cell array with a matrix of nonvolatile memory cells. The nonvolatile memory cells may store data using variable resistive elements. A plurality of bitlines are coupled to a plurality of nonvolatile memory cell arrays in the memory cell array. A column selection circuit... Agent: Myers Bigel Sibley & Sajovec

20100014347 - Diode assisted switching spin-transfer torque memory unit: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel... Agent: Campbell Nelson Whipps, LLC

20100014346 - Unipolar spin-transfer switching memory unit: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction... Agent: Campbell Nelson Whipps, LLC

20100014350 - Nand flash memory: A NAND flash memory according to examples of the invention includes a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction and first and second transfer transistor blocks disposed in order in the first direction at one end in a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100014352 - Non-volatile memory cell read failure reduction: The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method... Agent: Brooks, Cameron & Huebsch , PLLC

20100014349 - Programming non-volatile storage using binary and multi-state programming processes: A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block... Agent: Vierra Magen/sandisk Corporation

20100014351 - Semiconductor memory having electrically erasable and programmable semiconductor memory cells: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100014353 - Flash memory device with switching input/output structure: In a flash memory device with switching I/O structure for applying in flash memory products, depending on actual need for input and/or output pins, other pins may be flexibly switched to input, output, or bi-directional pins through software and/or hardware and/or CAM access. Therefore, data input and/or output rate may... Agent: Schmeiser, Olsen & Watts

20100014355 - Nonvolatile semiconductor memory device: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the... Agent: Mcdermott Will & Emery LLP

20100014354 - Use of recovery transistors during write operations to prevent disturbance of unselected cells: A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array (100); has a plurality of memory cells (148, 150,152, 154), each of which is coupled to a... Agent: Schwegman, Lundberg & Woessner / Atmel

20100014348 - Circuit, system, and method for programming a floating gate: The invention provides circuits, systems, and methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.... Agent: Michael T. Konczal, Patent Attorney

20100014356 - Sense amplifier used in electrically erasable programmable read-only memory and the implementing method thereof: The present invention discloses a sense amplifier used in an Electrically Erasable Programmable Read-only Memory; the sense amplifier includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the sense amplifier further includes... Agent: Sinorica, LLC

20100014357 - Flash-based fpga with secure reprogramming: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory... Agent: Lewis And Roca LLP

20100014358 - Nonvolatile memory cell, nonvolatile memory device, and method of programming the nonvolatile memory device: A method of programming a nonvolatile memory device. The method may include pre-programming one memory cell among a plurality of memory cells by storing data in a first data storage layer using a first program voltage applied to one word line corresponding to the one memory cell among the plurality... Agent: Muir Patent Consulting, PLLC

20100014359 - Operating method of non-volatile memory: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region.... Agent: Jianq Chyun Intellectual Property Office

20100014360 - Semiconductor device and control method thereof: Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differential amplification; and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20100014361 - Semiconductor memory device and method for driving the same: A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory... Agent: Ip & T Law Firm PLC

20100014362 - Data readout circuit and semiconductor memory device: A data readout circuit comprises: a 1st PMOS transistor configured to operate in a saturation region and including a source connected to a power supply, a drain connected to an input terminal connected to a memory cell of a data readout object, and a gate to which a 1st bias... Agent: Volentine & Whitt PLLC

20100014363 - Selfcalibration method and circuit of nonvolatile memory and nonvolatile memory circuit: The present invention discloses a selfcalibration method of a reading circuit of a nonvolatile memory, by which trimming data having recorded a reference current are stored in a bit-pair form into the memory and regulate a sense amplifier, and a value of the reference current is obtained according to the... Agent: Sinorica, LLC

20100014365 - Data input circuit and nonvolatile memory device including the same: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to... Agent: Ip & T Law Firm PLC

20100014364 - Memory system and method using stacked memory device dice, and system using the memory system: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100014366 - Semiconductor memory devices having signal delay controller and methods performed therein: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell.... Agent: Harness, Dickey & Pierce, P.L.C

20100014367 - Memory repair circuit and repairable pseudo-dual port static random access memory: The present invention relates to a memory repair circuit and a repairable pseudo-dual port static random access memory (pseudo-dual port SRAM). The memory repair circuit uses fewer redundant column blocks and stores a few failed block addresses to reduce the required complexity of decoding the redundant column blocks. Thus, the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100014369 - Method for testing a static random access memory: A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100014368 - System that increases data eye widths: One embodiment provides a system including an integrated circuit configured to receive a signal and invert first read data bits based on the signal. The integrated circuit provides inverted first read data bits that increase data eye widths of second read data bits adjacent the inverted first read data bits.... Agent: Dicke, Billig & Czaja

20100014370 - Precharge and evaluation phase circuits for sense amplifiers: A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor,... Agent: Schwegman, Lundberg & Woessner / Atmel

20100014371 - Circuit and method for controlling a clock synchronizing circuit for low power refresh operation: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100014372 - Semiconductor device, an electronic device and a method for operating the same: A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a... Agent: Edell, Shapiro & Finnan, LLC

20100014374 - Fuse element reading circuit: A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown state or an unblown state, a reference voltage output circuit unit that outputs a reference voltage that differs in accordance with a normal... Agent: Arent Fox LLP

20100014373 - Regulating electrical fuse programming current: An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of... Agent: Cantor Colburn LLP-ibm Burlington

20100014375 - Semiconductor memory device: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100014376 - Decoding circuit withstanding high voltage via low-voltage mos transistor and the implementing method thereof: The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source... Agent: Sinorica, LLC

20100014377 - Method and apparatus for reducing oscillation in synchronous circuits: Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and... Agent: Trask Britt, P.C./ Micron Technology

  
01/14/2010 > patent applications in patent subcategories. recently filed with US Patent Office

20100008120 - Semiconductor memory: Dummy memory cells are disposed on an outside of real memory cells positioned on a peripheral part of a matrix. First contacts coupling between two wiring layers laminated on a semiconductor substrate are disposed around each of the real and dummy memory cells, and are shared by an adjacent real... Agent: Arent Fox LLP

20100008121 - Method for driving ferroelectric memory device, ferroelectric memory device, and electronic equipment: A method for driving a ferroelectric memory device having a plurality of memory cells that store data and a memory cell for flag is provided. The method includes, upon writing to the plurality of memory cells, the steps of: reading data from the plurality of memory cells and the memory... Agent: Harness, Dickey & Pierce, P.L.C

20100008124 - Cross point memory cell with distributed diodes and method of making same: A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode,... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20100008122 - Memory device and method for making same: An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.... Agent: Infineon Technologies Ag Patent Department

20100008123 - Multiple series passive element matrix cell for three-dimensional arrays: A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20100008127 - Resistance variable element and resistance variable memory apparatus: A resistance variable element of the present invention and a resistance variable memory apparatus using the resistance variable element are a resistance variable element (10) including a first electrode, a second electrode, and a resistance variable layer (3) provided between the first electrode (2) and the second electrode (4) to... Agent: Mcdermott Will & Emery LLP

20100008128 - Resistive nonvolatile memory element, and production method of the same: The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm... Agent: Mcdermott Will & Emery LLP

20100008125 - Semiconductor memory device and redundancy method therefor: A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100008126 - Three-dimensional memory device: A three-dimensional memory device includes: a plurality of mats laminated therein, each having memory cells arranged in a two-dimensional manner; and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats. Laminated mats are divided into three or more groups. When... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100008129 - Semiconductor memory device and method of controlling the same: A semiconductor memory device includes first and second bit lines complementary to each other, sense amplifiers, memory cells, first and second switches, an equalizer circuit, and a potential generation unit. The potential generation unit supplies a first potential to at least a selected one of the plurality of first and... Agent: Morrison & Foerster LLP

20100008131 - Magnetoresistance effect element and mram: A magnetoresistance effect element according to the present invention comprises a magnetization tree layer 1 and a magnetization fixed layer 3 connected to the magnetization free layer 1 through a nonmagnetic layer 2. The magnetization free layer 1 includes a magnetization switching region 13, a first magnetization fixed region 11... Agent: Mr. Jackson Chen

20100008130 - Method of operating magnetic random access memory device: Provided is a method of operating a magnetic random access memory device comprising a switch structure and a magnetoresistance structure. According to the method, current variation depending on the direction of the current can be reduced by controlling a gate voltage of the switch structure when supplying current to write... Agent: Harness, Dickey & Pierce, P.L.C

20100008133 - Phase change memory devices and systems, and related programming methods: A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is... Agent: Volentine & Whitt PLLC

20100008132 - Resistance memory element, phase change memory element, resistance random access memory device, information reading method thereof, phase change random access memory device, and information reading method thereof: A resistance memory element, a phase change memory element, a resistance random access memory device, an information reading method thereof, a phase change random access memory device, and an information reading method thereof are provided. The resistance random access memory device includes an array of resistance memory element arranged in... Agent: Sherr & Vaughn, PLLC

20100008135 - Information storage devices using magnetic domain wall movement and methods of operating the same: An information storage device includes a storage node, a write unit configured to write information to a first magnetic domain region of the storage node, and a read unit configured to read information from a second magnetic domain region of the storage node. The information storage device further includes a... Agent: Harness, Dickey & Pierce, P.L.C

20100008134 - Transmission gate-based spin-transfer torque memory unit: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line... Agent: Campbell Nelson Whipps, LLC

20100008139 - Memory devices having volatile and non-volatile memory characteristics and methods of operating the same: Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and... Agent: Harness, Dickey & Pierce, P.L.C

20100008138 - Method of programming nonvolatile memory device: According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltage, which is applied at a time... Agent: Ip & T Law Firm PLC

20100008140 - Nonvolatile memory devices supporting memory cells having different bit storage levels and methods of operating the same: Nonvolatile memory devices include a memory cell array including a first memory cell and an adjacent second memory cell and a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not... Agent: Myers Bigel Sibley & Sajovec

20100008141 - Strap-contact scheme for compact array of memory cells: A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the... Agent: Slater & Matsil, L.L.P.

20100008142 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth page buffer blocks comprises m page buffers, divided... Agent: Ip & T Law Firm PLC

20100008143 - Nonvolatile semiconductor memory device and control method thereof: A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100008144 - System and memory for sequential multi-plane page memory operations: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100008146 - Memory device and method of programming thereof: The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse... Agent: Harness, Dickey & Pierce, P.L.C

20100008145 - Method of programming nonvolatile memory device: A method of programming nonvolatile memory devices. According to one programming method program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then... Agent: Ip & T Law Firm PLC

20100008136 - Methods of operating memory devices: Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying... Agent: Harness, Dickey & Pierce, P.L.C

20100008137 - Nonvolatile memory device and program or erase method using the same: A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result... Agent: Ip & T Law Firm PLC

20100008148 - Low noise sense amplifier array and method for nonvolatile memory: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20100008147 - Sensing circuit for flash memory device operating at low power supply voltage: A sensing circuit that operates even at a low power supply voltage and reduces stress on a memory cell in a flash memory device without lowering a reading speed at the low power supply voltage is provided. The sensing circuit includes a first load element, a first inverting circuit, a... Agent: Mills & Onello LLP

20100008149 - Flash memory device and programming method thereof: A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among... Agent: Stanzione & Kim, LLP

20100008151 - Methods of detecting a shift in the threshold voltage for a nonvolatile memory cell: A nonvolatile memory device is operated by programming sample data in the memory device for verification using verify voltage levels derived from an ideal verify voltage Vv associated with a particular temperature range, performing read verify operations on the sample data using the verify voltage Vv associated with the temperature... Agent: Myers Bigel Sibley & Sajovec

20100008150 - Nonvolatile semiconductor storage device and method of erase verifying the same: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100008152 - Semiconductor device including driving transistors: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the... Agent: Mills & Onello LLP

20100008153 - Method for operating nonvolatitle memory array: A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot... Agent: J C Patents

20100008164 - Memory: A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current,... Agent: Schwabe, Williamson & Wyatt, P.C.

20100008163 - Memory architecture and cell design employing two access transistors: An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20100008154 - Interconnecting bit lines in memory devices for multiplexing: An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs.... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20100008155 - Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems: A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level... Agent: Martine Penilla & Gencarella, LLP

20100008156 - Semiconductor memory device and method for operating the same: A semiconductor device includes a plurality of input units configured to receive a plurality of data, a plurality of latching units configured to latch output signals of the plurality of input units in response to a plurality of synchronization clock signals, and a synchronization clock generating unit configured to delay... Agent: Ip & T Law Firm PLC

20100008157 - Semiconductor memory device capable of detecting write completion at high speed: A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100008159 - Differential sense amplifier: A differential sense amplifier can perform data sensing using a very low supply voltage.... Agent: Fish & Richardson P.C.

20100008158 - Read leveling of memory units designed to receive access requests in a sequential chained topology: Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay... Agent: Nvidia C/o Murabito, Hao & Barnes LLP

20100008161 - Semiconductor memory device: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor... Agent: Ip & T Law Firm PLC

20100008160 - Temperature sensor capable of reducing test mode time: A temperature sensor includes a temperature sensing unit for producing a sensing level by sensing an internal temperature in a semiconductor memory device, a reference level generating unit for setting up a reference level by selecting one of a plurality of reference voltages, which are set up according to the... Agent: Cooper & Dunham, LLP

20100008162 - Semiconductor memory device and method for generating bit line equalizing signal: A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes... Agent: Ip & T Law Firm PLC

20100008165 - Memory cell sensing using negative voltage: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the... Agent: Brooks, Cameron & Huebsch , PLLC

20100008166 - Circuit and method for controlling loading of write data in semiconductor memory device: A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing... Agent: Ip & T Law Firm PLC

20100008169 - Latency control circuit and method thereof and an auto-precharge control circuit and method thereof: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the... Agent: Harness, Dickey & Pierce, P.L.C

20100008168 - Programmable control block for dual port sram application: A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that... Agent: Townsend And Townsend And Crew LLP/ 015114

20100008167 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a delay locked loop to generate a delay control signal corresponding to a detected phase difference between reference and feedback clock signals, a delay locked loop (DLL) clock signal, and the feedback clock signal. The memory device further includes a delay time measurement device to... Agent: Ip & T Law Firm PLC

20100008170 - Semiconductor tester and testing method of semiconductor memory: The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a test pattern; a waveform shaper shaping the test pattern and outputting a test signal based on the shaped test pattern to the... Agent: Birch Stewart Kolasch & Birch

20100008172 - Dynamic type semiconductor memory device and operation method of the same: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to... Agent: Young & Thompson

20100008171 - Read assist circuit of sram with low standby current: A SRAM memory with a read assist circuit is presented. The read assist circuit uses bitline voltage level switches, which are connected to a low power supply and a high power supply. The bitline voltage level switches have a write operation state, a read operation state, and a standby operation... Agent: Martine Penilla & Gencarella, LLP

20100008173 - Semiconductor memory device: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor... Agent: Ip & T Law Firm PLC

20100008174 - Adaptive training and adjustment to changing capacitor values based upon age and usage behavior: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.... Agent: Fsp LLC

20100008175 - Battery-less cache memory module with integrated backup: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt... Agent: Loza & Loza

20100008176 - Write leveling of memory units designed to receive access requests in a sequential chained topology: A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the... Agent: Nvidia C/o Murabito, Hao & Barnes LLP

20100008177 - Semiconductor memory device: A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical... Agent: Ip & T Law Firm PLC

  
01/07/2010 > patent applications in patent subcategories. recently filed with US Patent Office

20100002484 - Content addressable memory array with an invalidate feature: A disclosed embodiment is a CAM (content addressable memory) array with an invalidate feature, the CAM array includes a plurality of words, where each of the plurality of words includes a respective invalidate circuit. Each respective invalidate circuit is configured to invalidate stored data in each corresponding plurality of words... Agent: Farjami & Farjami LLP

20100002481 - Content addressable memory using phase change devices: Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element... Agent: Law Office Of Ido Tuchman (yor)

20100002482 - Memory device and method: A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation,... Agent: Larson Newman & Abel, LLP

20100002483 - Range checking content addressable memory array: A disclosed embodiment is a range checking CAM array comprising a plurality of words, where each of the plurality of words comprises a plurality of bound check cells. Each of the plurality of bound check cells outputs a corresponding plurality of match signals and a corresponding plurality of bound check... Agent: Farjami & Farjami LLP

20100002485 - Configurable inputs and outputs for memory stacking system and method: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal,... Agent: Fletcher Yoder (micron Technology, Inc.)

20100002486 - Magnetic shift register memory device: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from... Agent: Wall & Tong, LLP IBM Corporation

20100002487 - Three-dimensional magnetic memory: Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. Bits may be written to a data storage layer in the form of magnetic domains. The bits can then be transferred between the stacked... Agent: Duft Bornsen & Fishman, LLP

20100002488 - F-sram margin screen: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing... Agent: Texas Instruments Incorporated

20100002489 - Passive matrix-addressable memory apparatus: Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other;... Agent: The Belles Group, P.C.

20100002490 - Electric element, memory device, and semiconductor integrated circuit: An electric element includes: a first electrode; a second electrode; and a variable-resistance film connected between the first electrode and the second electrode. The variable-resistance film includes Fe3O4 as a constituent element and has a crystal grain size of 5 nm to 150 nm.... Agent: Mcdermott Will & Emery LLP

20100002492 - Resistance change memory: A resistance change type memory includes a first device region and first and second bit lines provided above the first device region and along a first direction. First and second resistance change elements are connected to the first and second bit lines, respectively. A first transistor is serially connected to... Agent: Knobbe Martens Olson & Bear LLP

20100002491 - Resistance ram having oxide layer and solid electrolyte layer, and method for operating the same: A resistance RAM that is provided with an oxide layer and a solid electrolyte layer, and a method for operating the same are provided. The resistance RAM comprises a first electrode, an oxide layer that is formed on the first electrode, a solid electrolyte layer that is disposed on the... Agent: Ampacc Law Group

20100002494 - Memory device with memory cell including mugfet and fin capacitor: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with... Agent: Texas Instruments Incorporated

20100002493 - Semiconductor storage device: A precharge circuit precharges a bit line paired with the bit line to which the selected one of the memory cells is connected, by applying to the former bit line an external reference voltage for comparison with a voltage in the bit line caused by selection of the memory cell.... Agent: Knobbe Martens Olson & Bear LLP

20100002495 - Column selectable self-biasing virtual voltages for sram write assist: A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit... Agent: Ibm Corporation

20100002496 - Semiconductor memory device: The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100002497 - Space and process efficient mram: Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20100002498 - Integrated circuit for programming a memory cell: An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The... Agent: Dicke, Billig & Czaja

20100002499 - Phase change memory programming method without reset over-write: A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a... Agent: Law Office Of Ido Tuchman (yor)

20100002500 - Read reference circuit for a sense amplifier within a chalcogenide memory device: A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical “0” state and a logical “1” state within a chalcogenide memory cell. In conjunction with a precharge... Agent: Bae Systems

20100002501 - Mram device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations: A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating... Agent: Slater & Matsil, L.L.P.

20100002502 - Memory device and method of refreshing: A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation,... Agent: Larson Newman & Abel, LLP

20100002508 - Flash memory device controlling common source line voltage, program-verify method, and memory system: Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one... Agent: Volentine & Whitt PLLC

20100002507 - Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same: A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be... Agent: F. Chau & Associates, LLC

20100002503 - Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the... Agent: Slater & Matsil, L.L.P.

20100002509 - Integrated flash memory systems and methods for load compensation: Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage.... Agent: Dla Piper LLP (us )

20100002506 - Memory device and memory programming method: Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from... Agent: Harness, Dickey & Pierce, P.L.C

20100002504 - Mulitple-bit per cell (mbc) non-volatile memory apparatus and system having polarity control and method of programming same: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize... Agent: Mosaid Technologies Incorporated

20100002510 - Nand type flash memory and write method of the same: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100002505 - Reading method for mlc memory and reading circuit using the same: A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100002511 - secure non-volatile memory device and method of protecting data therein: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100002512 - Disabling faulty flash memory dies: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling... Agent: Fish & Richardson P.C.

20100002514 - Correcting for over programming non-volatile storage: A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line).... Agent: Vierra Magen/sandisk Corporation

20100002516 - Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same: Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string... Agent: Myers Bigel Sibley & Sajovec

20100002515 - Programming and selectively erasing non-volatile storage: A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.... Agent: Vierra Magen/sandisk Corporation

20100002513 - Selective erase operation for non-volatile storage: A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other... Agent: Vierra Magen/sandisk Corporation

20100002518 - Flash memory device and programming method thereof: The flash memory device includes a memory cell array having a plurality of memory cells, a high voltage generator configured to generate a plurality of pass voltages, with a first pass voltage of the plurality of pass voltages supplied to the memory cell array during a programming operation; and a... Agent: Harness, Dickey & Pierce, P.L.C

20100002519 - Flash memory device and programming method thereof: A flash memory device including a controller to determine higher, M, and lower, N, word-line address bits based on an input word-line address, to determine a selected area of a memory array based on the higher and lower word-line address bits, and an unselected area of the memory array based... Agent: Harness, Dickey & Pierce, P.L.C

20100002520 - Method for programming a flash memory device: A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass... Agent: Townsend And Townsend And Crew, LLP

20100002517 - Semiconductor device and method for controlling: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that is provided on a semiconductor substrate and a plurality of word lines that are provided on the... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100002521 - Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of... Agent: Trop, Pruner & Hu, P.C.

20100002523 - Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower... Agent: Myers Bigel Sibley & Sajovec

20100002522 - Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device: A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected... Agent: F. Chau & Associates, LLC

20100002524 - Flotox-type eeprom: In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b), two tunnel windows (33a, 33b) a shared source (27),... Agent: Rabin & Berdo, PC

20100002525 - Array data input latch and data clocking scheme: A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the... Agent: International Business Machines Corporation Richard Lau

20100002526 - Latch-based random access memory: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.... Agent: Ip Legal Services

20100002527 - Power up detection system for a memory device: A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is... Agent: Borden Ladner Gervais LLP Anne Kinsman

20100002528 - Semiconductor device: A sense amplifier section comprises two stages of latch-type sense amplifier circuits, i.e., a primary-stage latch-type sense amplifier and a secondary-stage latch-type sense amplifier, wherein stress exerted on the primary-stage latch-type sense amplifier is reduced significantly to ensure high accuracy in amplification. In the above configuration including the secondary-stage latch-type... Agent: Mattingly & Malur, P.C.

20100002529 - Circuit and method for controlling slew rate of data output circuit in semiconductor memory device: A data output circuit of a semiconductor memory device includes at least two data output pads disposed adjacent to each other, a driver unit configured to output a first data by driving a first pad among the data output pads, and a control unit configured to determine whether a phase... Agent: Ip & T Law Firm PLC

20100002530 - Memory address repair without enable fuses: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a... Agent: Jones Day

20100002531 - Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations: An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The... Agent: Myers Bigel Sibley & Sajovec

20100002532 - Ultra-low power hybrid sub-threshold circuits: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation... Agent: Jeng-jye Shau

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