|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All |
12/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval December patent applications/inventions, industry category 12/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/31/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090323383 - Comparing data representations to stored patterns: A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at least one of the plurality of data patterns to select one of the plurality of representations of... Agent: Marshall, Gerstein & Borun, LLP (marvell)
20090323384 - High density content addressable memory using phase change devices: A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is... Agent: Ibm - Yor Shimokaji & Associates, P.C.
20090323385 - Method for fabricating high density pillar structures by double patterning using positive photoresist: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090323386 - Methods and systems for reducing heat flux in memory systems: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus.... Agent: Morgan, Lewis & Bockius, LLP. (pa)
20090323387 - One-time programmable memory and operating method thereof: A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090323388 - Buried bit line anti-fuse one-time-programmable nonvolatile memory: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator... Agent: Stout, Uxa, Buyan & Mullins LLP
20090323389 - Masked memory cells: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value... Agent: Dickstein Shapiro LLP
20090323390 - Semiconductor memory device: A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting... Agent: Knobbe Martens Olson & Bear LLP
20090323393 - Capacitive discharge method for writing to non-volatile memory: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide... Agent: Vierra Magen/sandisk Corporation
20090323397 - Nonvolatile semiconductor memory device and reading method of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell including a resistance memory element which memorizes a high resistance state or a low resistance state, switches the high resistance state and the low resistance state by voltage application, one end of the resistance memory element being coupled to a bit... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090323394 - Pulse reset for non-volatile storage: A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse... Agent: Vierra Magen/sandisk Corporation
20090323391 - Reverse set with current limit for non-volatile storage: A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.... Agent: Vierra Magen/sandisk Corporation
20090323396 - Semiconductor memory device: A semiconductor memory according to an aspect of the invention including first and second bit lines, a word line, a resistive memory element which has one end and the other end, the one end being connected with the first bit line, a selective switch element which has a current path... Agent: Knobbe Martens Olson & Bear LLP
20090323398 - Semiconductor memory device comprising a plurality of static memory cells: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power... Agent: Mcdermott Will & Emery LLP
20090323395 - Semiconductor storage device: A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090323392 - Smart detection circuit for writing to non-volatile storage: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.... Agent: Vierra Magen/sandisk Corporation
20090323399 - Semiconductor memory device: A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned... Agent: Sughrue Mion, PLLC
20090323400 - Semiconductor device: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix,... Agent: Mattingly & Malur, P.C.
20090323401 - 8t low leakage sram cell: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a... Agent: K & L Gates LLPIPDocketing
20090323405 - Controlled value reference signal of resistance based memory circuit: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively... Agent: Qualcomm Incorporated
20090323406 - Magnetic memory element, and method of manufacturing memory element: A magnetic memory element includes an impurity element, and magnetic thin lines to which the impurity element is added to adjust the movement of a magnetic domain wall in a magnetic field. Applying a voltage to the magnetic thin lines controls a position of the magnetic domain wall to invert... Agent: Greer, Burns & Crain
20090323403 - Spin-transfer torque memory non-destructive self-reference read method: A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read... Agent: Campbell Nelson Whipps, LLC
20090323402 - Spin-transfer torque memory self-reference read method: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a... Agent: Campbell Nelson Whipps, LLC
20090323404 - Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size: Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in... Agent: Qualcomm Incorporated
20090323407 - Memory device, an information storage process, a process, and a structured material: A memory device, including a plurality of nanoscale memory cells (1510, 1512) created by applying pressure to and removing pressure from one or more regions (1510, 1512) of a substance (1502) to change the electrical conductivity of those regions (1510, 1512). An electrically conductive read probe (1514) determines the conductivities... Agent: Knobbe Martens Olson & Bear LLP
20090323408 - Methods for determining resistance of phase change memory elements: Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of... Agent: Fletcher Yoder (micron Technology, Inc.)
20090323409 - Methods for high speed reading operation of phase change memory and device employing same: Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090323410 - System and method to fabricate magnetic random access memory: A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction in a region in which a substrate resides during a deposition... Agent: Qualcomm Incorporated
20090323411 - Method including selective treatment of storage layer: Method including selective treatment of storage layer. One embodiment includes the formation of a material layer on a topology with protruding portions, which may be assigned to active areas, and with recessed portions, which may be assigned to isolation structures. A mask material is deposited that grows selectively above the... Agent: Dicke, Billig & Czaja
20090323412 - Read disturb mitigation in non-volatile memory: Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for... Agent: Vierra Magen/sandisk Corporation
20090323415 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper LLP (us )
20090323414 - Method and device for storing data: In one aspect a method of storing data in an integrated circuit may include identifying a group of storage sites from a plurality of storage sites; selecting a plurality of storage levels, each storage level being assignable to a storage site in the group of storage sites; and assigning a... Agent: Slater & Matsil, L.L.P.
20090323416 - Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20090323417 - Semiconductor memory repairing a defective bit and semiconductor memory system: A semiconductor memory has a plurality of blocks, and each of the blocks comprises a plurality of pages, and further, each of the pages has a plurality of memory cells. A block having defective bits less than N (N is an integer number more than 0) in all pages of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090323418 - Use of alternative value in cell detection: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible... Agent: Fish & Richardson P.C.
20090323419 - Read-time wear-leveling method in storage system using flash memory device: Disclosed is a read-time wear-leveling method in a storage system using a flash memory device, in which the abrasion of the flash memory device generated by repeated read operations is dispersed over the entire region so that the abrasion of memory blocks can be equalized to prolong the life of... Agent: Mcdermott Will & Emery LLP
20090323421 - Memory device with power noise minimization during sensing: Accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage... Agent: Vierra Magen/sandisk Corporation
20090323420 - Minimizing power noise during sensing in memory device: In a sensing method, accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing... Agent: Vierra Magen/sandisk Corporation
20090323422 - Gain control for read operations in flash memory: A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach,... Agent: Vierra Magen/sandisk Corporation
20090323428 - Method for improving memory device cycling endurance by providing additional pulses: A method for programming and erasing a PHINES memory device is comprising providing one or more additional pulses that are associated with a program or erase pulse, wherein the additional pulses are of similar polarity, but of lesser magnitude than the program or erase pulses. For an erase pulse on... Agent: Baker & Mckenzie LLP Patent Department
20090323423 - Methods, circuits and systems for reading non-volatile memory cells: The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region... Agent: Eitan Mehulal Law Group
20090323426 - Semiconductor memory device: A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090323427 - Semiconductor memory device: A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in... Agent: Mcdermott Will & Emery LLP
20090323424 - Semiconductor memory device and method for driving semiconductor memory device: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090323425 - Systems and methods for improved floating-gate transistor programming: The present invention describes systems and methods for improving the programming of floating-gate transistors. An exemplary embodiment of the present invention provides a floating-gate transistor programming system including an array of floating-gate transistors and a measuring circuit comprising a logarithmic transimpedance amplifier and an analog-to-digital converter. Furthermore, the floating-gate transistor... Agent: Troutman Sanders LLP Bank Of America Plaza
20090323430 - Program acceleration of a memory device: Selective program acceleration of a memory device is generally described. In one example, a method includes applying a first bias voltage to one or more bit lines coupled with a plurality of cells to be programmed, applying one or more program pulses to the plurality of cells, verifying the plurality... Agent: Cool Patent, P.C. C/o Cpa Global
20090323429 - Programming algorithm to reduce disturb with minimal extra time penalty: Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast... Agent: Vierra Magen/sandisk Corporation
20090323413 - Voltage reference generator for flash memory: There is disclosed example embodiments of flash memory including reference generators using big flash memory cells to generate flash array wordline voltages, wherein the reference voltage values can be trimmed by changing the threshold voltage of the flash cells. In addition, the inventive subject matter provides for using the matching... Agent: Schwegman, Lundberg & Woessner, P.A.
20090323431 - Non-volatile memory device and program method thereof: A method of programming a non-volatile memory device employing program loops. Each program loop comprises a programming operation and a subsequent plurality of verifying operations. The method includes preventing the next program loop based on the results of performing the plurality of verifying operations of a current program loop each... Agent: F. Chau & Associates, LLC
20090323432 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090323439 - Memory for storing a binary state: A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value.... Agent: Dickstein Shapiro LLP
20090323435 - Time reduction of address setup/hold time for semiconductor memory: In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input.... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090323437 - Method and apparatus for data inversion in memory device: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.
20090323436 - Refresh signal generating circuit: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal... Agent: Cooper & Dunham, LLP
20090323438 - Circuit and method for generating word line off voltage: A circuit and method for generating a word line off voltage which can minimize a leakage current by actively adjusting a level of the word line off voltage. The circuit includes a current information provider for providing information about an amount of current flowing through a cell transistor, and a... Agent: Ip & T Law Firm PLC
20090323440 - Data processing device and method of reading trimming data: A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random... Agent: Mcginn Intellectual Property Law Group, PLLC
20090323441 - Write latency tracking using a delay lock loop in a synchronous dram: A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.
20090323434 - Combination memory device and semiconductor device: A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent... Agent: Greenblum & Bernstein, P.L.C
20090323433 - Data sensing method for dynamic random access memory: A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data... Agent: Wpat, PC Intellectual Property Attorneys
20090323442 - Semiconductor memory device and reset control circuit of the same: The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the... Agent: Ladas & Parry LLP
20090323443 - Semiconductor memory device: A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection... Agent: Ip & T Law Firm PLC
20090323444 - Semiconductor memory device and operating method thereof: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes... Agent: Ip & T Law Firm PLC
20090323447 - Apparatus for measuring data setup/hold time: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response... Agent: Cooper & Dunham, LLP
20090323445 - High performance read bypass test for sram circuits: A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of... Agent: Ibm Corporation
20090323446 - Memory operation testing: Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide... Agent: Freescale Semiconductor, Inc. Law Department
20090323448 - Bias sensing in dram sense amplifiers through voltage-coupling/decoupling device: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time... Agent: Ropes & Gray LLP
20090323449 - Circuit and method for controlling self-refresh cycle: The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor... Agent: Ladas & Parry LLP
20090323450 - Non-volatile programmable memory cell and memory array: A non-volatile one time programmable memory cell couples in series a two terminal fuse and a three terminal antifuse. The non-volatile one time programmable memory cell includes a memory cell write enable node and a memory cell output node. The non-volatile one time programmable memory cell includes fuse having a... Agent: Daly, Crowley, Mofford & Durkee, LLP
20090323451 - Semiconductor memory device: A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply... Agent: Ip & T Law Firm PLC
20090323452 - Dual mode memory system for reducing power requirements during memory backup transition: A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090323453 - Dynamic power saving memory architecture: A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to... Agent: Qualcomm Incorporated
20090323454 - Semiconductor memory device: A semiconductor memory device is capable of easily checking whether banks are overlappingly activated. The semiconductor memory device includes a bank active signal generating unit and an overlap detecting unit. The bank active signal generating unit generates bank active signals for respective different banks in response to an active signal... Agent: Ip & T Law Firm PLC
20090323455 - Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver: A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving... Agent: Ip & T Law Firm PLC
20090323456 - Multiple device apparatus, systems, and methods: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron
20090323457 - System and method for synchronizing asynchronous signals without external clock: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The... Agent: Fletcher Yoder (micron Technology, Inc.)12/24/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090316460 - Method and apparatus for memory redundancy in a microprocessor: An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A redundant array includes a CAM array that includes a plurality of memory cells. The CAM array is addressed by the address of a... Agent: Osha Liang L.L.P./sun
20090316461 - Method and apparatus for performing variable word width searches in a content addressable memory: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search... Agent: Sadler, Breen, Morasch & Colby, Ps
20090316462 - Magnetic tracks with domain wall storage anchors: Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other... Agent: Campbell Nelson Whipps, LLC
20090316465 - Efficient word lines, bit line and precharge tracking in self-timed memory device: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The... Agent: Freescale Semiconductor, Inc. Law Department
20090316464 - Low power read scheme for read only memory (rom): A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a... Agent: Freescale Semiconductor, Inc. Law Department
20090316463 - Semiconductor device and method for making same: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the... Agent: Slater & Matsil LLP
20090316466 - Method, apparatus and system, providing a one-time programmable memory device: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.... Agent: Dickstein Shapiro LLP
20090316468 - Large array of upward pointing p-i-n diodes having large and uniform current: A first memory level includes a first plurality of memory cells that includes every memory cell in the first memory level. Each memory cell includes a vertically oriented p-i-n diode in the form of a pillar that includes a bottom heavily doped p-type region, a middle intrinsic or lightly doped... Agent: Dugan & Dugan, PC
20090316467 - Memory device constructions, memory cell forming methods, and semiconductor construction forming methods: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to... Agent: Wells St. John P.s.
20090316469 - Ferroelectric memory brake for screening and repairing bits: A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data to the first capacitor, and (304) baking the first capacitor for a first specified period of time at a first selected temperature. A same state read... Agent: Texas Instruments Incorporated
20090316470 - Semiconductor storage device: According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control... Agent: Knobbe Martens Olson & Bear LLP
20090316471 - Resistance change memory: A resistance change memory includes first and second memory cell arrays which are adjacent to each other in a first direction, first and second reference cell arrays paired with the first and second memory cell arrays, a first sense amplifier shared by the first and second memory cell arrays and... Agent: Knobbe Martens Olson & Bear LLP
20090316472 - Magnetic random access memory: A magnetic random access memory (MRAM) including multiple memory cells for forming an array is provided. Each memory cell has a magnetic free stack layer and a pinned stack layer. A magnetization of the pinned stack layer is set toward a predetermined direction. The magnetic free stack layer has a... Agent: Jianq Chyun Intellectual Property Office
20090316473 - Integrated circuit including vertical diode: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive... Agent: Dicke, Billig & Czaja
20090316474 - Phase change memory: The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at... Agent: Harness, Dickey & Pierce, P.L.C
20090316475 - Information storage devices and methods of operating the same: Provided are an information storage device and a method of operating the same. The information storage device includes: a magnetic layer having a plurality of magnetic domain regions and a magnetic domain wall interposed between the magnetic domain regions; a first unit disposed on a first region which is one... Agent: Harness, Dickey & Pierce, P.L.C
20090316476 - Shared line magnetic random access memory cells: A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department
20090316477 - Nonvolatile semiconductor memory circuit utilizing a mis transistor as a memory cell: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a... Agent: Ipusa, P.l.l.c
20090316482 - Method of programming a multi-level memory device: Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C.
20090316480 - Methods of storing multiple data-bits in a non-volatile memory cell: Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel insulator layer. The composite trapping layer contains a plurality of band engineered sub-layers providing a plurality of charge trapping layers.... Agent: Leffert Jay & Polglaze, P.A.
20090316481 - Reading electronic memory utilizing relationships between cell state distributions: Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell.... Agent: Turocy & Watson, LLP
20090316478 - Semiconductor memory device: A semiconductor memory device includes first to third memory cell units each including a first select transistor, a second select transistor and a plurality of memory cell transistors which are connected in series in a first direction between the first select transistor and the second select transistor, the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090316479 - Semiconductor memory device capable of lowering a write voltage: A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090316483 - Flash memory device and system including the same: The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to... Agent: Harness, Dickey & Pierce, P.L.C
20090316484 - Semiconductor memory device, method of driving the same and method of manufacturing the same: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating... Agent: Young & Thompson
20090316485 - Memory card using multi-level signaling and memory system having the same: A memory card including a memory controller, a memory system and a method to control a memory are provided. The memory card includes a flash memory, a memory interface outputting a writing data signal to be written into the flash memory, and a multi-level converter transforming the writing data signal... Agent: Sughrue Mion, PLLC
20090316486 - Program and read trim setting: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.... Agent: Leffert Jay & Polglaze, P.A.
20090316487 - Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array: An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder... Agent: Saile Ackerman LLC
20090316488 - Memory self-test circuit, semiconductor device and ic card including the same, and memory self-test method: In a semiconductor device, a self-test circuit includes a write part for writing data in a given address of a special region of a nonvolatile memory; a read part for reading the written data from the given address; a verify part for determining whether or not the written data accords... Agent: Mcdermott Will & Emery LLP
20090316489 - Dynamic pass voltage: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.... Agent: Brooks, Cameron & Huebsch , PLLC
20090316490 - Method of writing data into semiconductor memory and memory controller: A method of writing data into a semiconductor memory (11) in which nonvolatile memory cells (MC) each having a gate connected to a word line (WL) are connected in series, the method comprising selecting (S13) a scrambling method for the data according to a word line address for memory cells... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090316491 - Non-volatile memory devices and methods of erasing non-volatile memory devices: In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transistor during an erase operation.... Agent: Harness, Dickey & Pierce, P.L.C
20090316499 - Semiconductor memory device operational processing device and storage system: A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.... Agent: Buchanan, Ingersoll & Rooney PC
20090316496 - Input-output line sense amplifier having adjustable output drive capability: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090316495 - Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same: A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode,... Agent: Young & Thompson
20090316493 - Semiconductor integrated circuit for generating clock signals: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write... Agent: Baker & Mckenzie LLP Patent Department
20090316494 - Semiconductor memory device having plurality of types of memories integrated on one chip: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090316497 - Semiconductor device including nonvolatile memory: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by... Agent: Arent Fox LLP
20090316498 - Circuit and method for vdd-tracking cvdd voltage supply: Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage... Agent: Slater & Matsil, L.L.P.
20090316500 - Memory cell employing reduced voltage: A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory... Agent: Texas Instruments Incorporated
20090316501 - Memory malfunction prediction system and method: A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090316492 - Memory cells, memory cell arrays, methods of using and methods of making: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second... Agent: Law Office Of Alan W. Cannon
20090316502 - Semiconductor memory device and operation method thereof: There is provided a semiconductor memory device including: a source strobe signal generating unit configured to generate a source strobe signal having a first or a second activation width corresponding to a normal mode and a bank grouping mode; a final strobe signal generating unit configured to, in the normal... Agent: Ip & T Law Firm PLC
20090316503 - Clock driver device and semiconductor memory apparatus having the same: A clock driver device includes a driving controller configured to generate a clock output enable signal enabled in response to an internal read pulse signal and disabled in response to a data output enable signal and an internal clock signal, and a clock driver configured to generate a driving clock... Agent: Baker & Mckenzie LLP Patent Department
20090316504 - Semiconductor integrated circuit for generating row main signal and controlling method thereof: A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test... Agent: Baker & Mckenzie LLP Patent Department
20090316505 - Soft error robust static random access memory cell storage configuration: A Static Random Access Memory (SRAM) cell storage configuration is provided with an improved robustness to radiation induced soft errors. The SRAM cell storage configuration comprises the following elements. First and second storage nodes are configured to store complementary voltages. Drive transistors are configured to selectively couple one of the... Agent: Gowling Lafleur Henderson LLP
20090316507 - Generation of test sequences during memory built-in self testing of multiple memories: The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address... Agent: Christopher P Maiorana, PC Lsi Corporation
20090316508 - Precise trcd measurement in a semiconductor memory device: A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read command, a column address... Agent: Young & Thompson
20090316506 - Serially decoded digital device testing: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift... Agent: Connolly Bove Lodge & Hutz LLP
20090316509 - Memory with high speed sensing: A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line... Agent: Freescale Semiconductor, Inc. Law Department
20090316510 - Semiconductor device and data processing system: Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of at least one of the other ports in a... Agent: Sughrue Mion, PLLC
20090316511 - Method and apparatus for selectively disabling termination circuitry: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry... Agent: Coats & Bennett/qimonda
20090316512 - Block redundancy implementation in heirarchical ram's: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder... Agent: Mcandrews Held & Malloy, Ltd
20090316513 - Semiconductor memory apparatus having a sub-word line driver for increasing an area margin in the memory core area: A semiconductor memory apparatus with a sub-word line driver is presented which has an increased area margin in the memory core area. The sub-word line driver is configured to operate in response to activation of a main word line and in response to positive and negative sub-word line enable signals.... Agent: Ladas & Parry LLP
20090316514 - Delay locked loop implementation in a synchronous dynamic random access memory: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to... Agent: Hamilton, Brook, Smith & Reynolds, P.C.12/17/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090310395 - Content-addressable memory: A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and... Agent: The Webb Law Firm, P.C.
20090310396 - Digital memory with controllable input/output terminals: Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being... Agent: Schwabe, Williamson & Wyatt, P.C.
20090310397 - Ferroelectric memory device, method for driving ferroelectric memory device, and electronic equipment: A ferroelectric memory device includes: a memory cell having a ferroelectric capacitor connected between a plate line and a bit line; a first node connected to the bit line through a charge transfer MISFET; a potential generation circuit that has a first capacitor having a first terminal connected to the... Agent: Harness, Dickey & Pierce, P.L.C
20090310398 - Low power, small size sram architecture: A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors... Agent: Townsend And Townsend And Crew, LLP
20090310399 - Semiconductor device: In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb.... Agent: Mattingly & Malur, P.C.
20090310400 - Semiconductor device: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit... Agent: Mattingly & Malur, P.C.
20090310401 - Integrated circuit including a memory element programmed using a seed pulse: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.... Agent: Dicke, Billig & Czaja
20090310402 - Method and apparatus for decoding memory: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be... Agent: Ovonyx, Inc
20090310403 - Nonvolatile memory device using variable resistive element: A nonvolatile memory device includes multiple memory blocks divided into multiple memory block groups. Each memory block group includes at least two memory blocks of the multiple memory blocks. The nonvolatile memory device also includes a main word line common to the memory blocks, and multiple sub-word lines corresponding to... Agent: Volentine & Whitt PLLC
20090310406 - M+l bit read column architecture for m bit memory cells: A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present... Agent: Leffert Jay & Polglaze, P.A.
20090310408 - Memory system and method of accessing a semiconductor memory device: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the... Agent: Harness, Dickey & Pierce, P.L.C
20090310407 - Sensing against a reference cell: Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range... Agent: Leffert Jay & Polglaze, P.A.
20090310409 - Nonvolatile semiconductor memory: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is... Agent: The Marbury Law Group, PLLC
20090310410 - Nonvolatile semiconductor memory device: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one... Agent: Mcdermott Will & Emery LLP
20090310412 - Methods of data management in non-volatile memory devices and related non-volatile memory systems: A data management method includes assigning data buffered in a first memory device into at least two different groups for transfer to a second memory device. At least one of the different groups has at least two units of the data assigned thereto. The data is transferred from the first... Agent: Myers Bigel Sibley & Sajovec
20090310411 - Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a nor-type flash operating below +/- 10v bvds: An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has... Agent: Saile Ackerman LLC
20090310413 - Reverse order page writing in flash memories: To store, in a memory block whose word lines are written successively in a word line writing order, a plurality of data pages that are ordered by logical page address, the pages are written to the word lines so that every page that is written to any one of the... Agent: Vierra Magen/sandisk Corporation
20090310414 - Nand string based nand/nor flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same: A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining... Agent: Saile Ackerman LLC
20090310415 - Non-volatile memory devices including vertical nand strings and methods of forming the same: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be... Agent: Myers Bigel Sibley & Sajovec
20090310416 - Selective threshold voltage verification and compaction: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution... Agent: Leffert Jay & Polglaze, P.A.
20090310417 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity... Agent: Oliff & Berridge, PLC
20090310420 - Method for correlated multiple pass programming in nonvolatile memory: A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size,... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090310418 - Method for index programming and reduced verify in nonvolatile memory: In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090310421 - Nonvolatile memory with correlated multiple pass programming: A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size,... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090310419 - Nonvolatile memory with index programming and reduced verify: In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090310404 - Memory device and method of controlling read level: Provided are memory devices and read level controlling methods. A memory device may include: a memory cell array that includes a plurality of memory cells; a counter that counts a number of memory cells with a threshold voltage included in a reference threshold voltage interval among the plurality of memory... Agent: Harness, Dickey & Pierce, P.L.C
20090310405 - Row-decoder and select gate decoder structures suitable for flashed-based eeprom operating below +/-10v bvds: A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row... Agent: Saile Ackerman LLC
20090310423 - Method of programming and erasing a non-volatile memory array: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090310422 - Non-volatile semiconductor storage device: A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a series of erase operations are executed. A second storage unit stores a value of an erase... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090310427 - Eeprom devices and methods of operating and fabricating the same: In one aspect, an electrically erasable and programmable read-only memory (EEPROM) is provided. The EEPROM includes a semiconductor substrate including spaced apart first, second and third active regions, a common floating gate traversing over the first through third active regions, source/drain regions formed in the third active region on opposite... Agent: Volentine & Whitt PLLC
20090310425 - Memory devices including vertical pillars and methods of manufacturing and operating the same: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring... Agent: Mills & Onello LLP
20090310424 - Method of erasing a flash eeprom memory: The invention is a new method for erasing a flash EEPROM memory device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090310426 - Semiconductor memory device: There is offered a semiconductor memory device that has reduced number of high withstand voltage transistors so as to suppress an increase in a die size. A second transistor of N channel type is connected between a word line and a decoder circuit. A control signal from a control circuit... Agent: Morrison & Foerster LLP
20090310428 - Mis-transistor-based nonvolatile memory for multilevel data storage: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a... Agent: Ipusa, P.l.l.c
20090310429 - Single-ended differential signal amplification and data reading: A method and system that can be used with signals read from a memory cell or other feature that varies in amplitude as a function of the data being read. The data read from the memory cell may be of the type that decreases in voltage when a ‘low’ is... Agent: Brooks Kushman P.C. / Sun / Stk
20090310430 - Methods for characterizing device variation in electronic memory circuits: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the... Agent: Ryan, Mason & Lewis, LLP
20090310432 - Bit line sense amplifier of semiconductor memory device having open bit line structure: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a... Agent: Volentine & Whitt PLLC
20090310431 - Semiconductor device including capacitorless ram: There is provided a semiconductor device including a capacitorless RAM. The semiconductor device includes a field effect transistor (FET) having a floating body structure. FET includes a channel body region arranged in a first region comprising a first semiconductor (e.g., p-SiGe) having a given band gap and a second region... Agent: Young & Thompson
20090310433 - Data alignment and de-skew system and method for double data rate input data stream: A system for aligning data is provided. The system comprises a demultiplexing component adapted to bifurcate a double data rate (DDR) data stream into first and second single data rate (SDR) data streams, a delay architecture adapted to generate delayed SDR data streams from the SDR data streams, a logic... Agent: Honeywell International Inc. Patent Services12/10/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090303767 - System, method and apparatus for memory with embedded associative section for computations: An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second... Agent: Pearl Cohen Zedek Latzer, LLP
20090303768 - Memory module, method for using same and memory system: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where... Agent: Sughrue Mion, PLLC
20090303770 - Memory chip and semiconductor device: A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked... Agent: Mcginn Intellectual Property Law Group, PLLC
20090303769 - Rom array with shared bit-lines: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each... Agent: Schwegman, Lundberg & Woessner / Atmel
20090303771 - Radio frequency identification device initializing a memory using an offset voltage: An RFID device sets initial data stored in a memory using an offset voltage and includes an analog block, a digital block, and a memory block. The memory blocks is configured to read/write data in a cell array unit. The memory block includes an offset controller that is configured to... Agent: Ladas & Parry LLP
20090303774 - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090303773 - Multi-terminal reversibly switchable memory device: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.... Agent: Unity Semiconductor Corporation
20090303772 - Two-terminal reversibly switchable memory device: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.... Agent: Unity Semiconductor Corporation
20090303778 - Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and... Agent: Ryan, Mason & Lewis, LLP
20090303777 - Semiconductor memory device: A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303776 - Static random access memory cell: A six transistor (“6T) static random access memory (“SRAM”) cell and method for using the same are disclosed herein. The 6T SRAM cell includes a single read pass gate transistor and a single write pass gate transistor. The single read pass gate transistor is connected to a read bit line... Agent: Texas Instruments Incorporated
20090303775 - Static random access memory cell and devices using same: A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled... Agent: Barnes & Thornburg, LLP
20090303779 - Spin torque transfer mtj devices with high thermal stability and low write currents: An integrated circuit structure includes a first fixed magnetic element; a second fixed magnetic element; and a composite free magnetic element between the first and the second fixed magnetic elements. The composite free magnetic element includes a first free layer and a second free layer.... Agent: Slater & Matsil, L.L.P.
20090303784 - Asymetric threshold three terminal switching device: An asymmetric-threshold three-terminal electronic switching device includes three terminals coupled to a threshold-switching material. A signal applied across first and second terminals affects an electrical characteristic between the second and third electrodes to a greater extent than the same signal applied across the first and third electrodes. The affected electrical... Agent: Ovonyx, Inc
20090303780 - Integrated circuit including an array of diodes coupled to a layer of resistance changing material: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing... Agent: Dicke, Billig & Czaja
20090303781 - Method and apparatus for thin film memory: A multi-layer thin-film device includes thin film memory and thin film logic. The thin film memory may be programmable resistance memory, such as phase change memory, for example. The thin film logic may be complementary logic.... Agent: Ovonyx, Inc
20090303785 - Phase change memory devices and read methods using elapsed time-based read voltages: A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods... Agent: Myers Bigel Sibley & Sajovec
20090303782 - Standalone thin film memory: A standalone memory device includes thin-film peripheral circuitry, including decoding circuitry. The standalone thin film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass. The memory is configured for operation with an external memory controller.... Agent: Ovonyx, Inc
20090303786 - Switch array circuit and system using programmable via structures with phase change materials: The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in... Agent: Scully, Scott, Murphy & Presser, P.C.
20090303783 - Thin film input/output: Input/Output circuitry employs thin-film switching devices to drive output signals from an integrated circuit to an external device and to receive input signals from an external device. Three terminal ovonic threshold switches (3T OTS) may be employed to drive input and output signals.... Agent: Ovonyx, Inc
20090303787 - Nonvolatile memories with tunnel dielectric with chlorine: In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase... Agent: Haynes And Boone, LLPIPSection
20090303788 - Methods and apparatus utilizing predicted coupling effect in the programming of non-volatile memory: Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20090303789 - Dynamically configurable mlc state assignment: Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20090303792 - Method for programming a multilevel memory: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than... Agent: Birch Stewart Kolasch & Birch
20090303790 - Nonvolatile semiconductor memory device and method for controlling the same: a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, and applying a second voltage to the word lines of the nonvolatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303791 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality... Agent: Hogan & Hartson L.L.P.
20090303793 - Memory device and method: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to... Agent: Larson Newman & Abel, LLP
20090303795 - Memory device and method: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to... Agent: Larson Newman & Abel, LLP
20090303796 - Semiconductor memory device: A semiconductor memory device including: a memory cell coupled to a bit line via a select gate transistor; a sense amplifier configured to have a current source for supplying current to the bit line, and detect cell current of the memory cell flowing on the bit line; and a select... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303794 - Structure and method of a field-enhanced charge trapping-dram: A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090303797 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303798 - Memory device and method: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to... Agent: Larson Newman & Abel, LLP
20090303800 - Non-volatile memory control circuit: An efficient erasure is performed. The voltage of a source line SL is manipulated in units of a sector comprising a plurality of memory cells. An erase command is received for the desired memory cells to be erased in a plurality of word line WL units arranged within a sector... Agent: Cantor Colburn, LLP
20090303799 - Non-volatile semiconductor memory device and erasing method thereof: A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303805 - Semiconductor memory device and method of controlling semiconductor memory device: A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite... Agent: Arent Fox LLP
20090303801 - Carbon nanotube memory including a buffered data path: Carbon nanotube memory comprises a buffered data path including a forwarding write line and a returning read line for transferring data. Furthermore, bit line is multi-divided for reducing parasitic capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives a memory cell output through... Agent: Juhan Kim
20090303802 - Semiconductor memory module and semiconductor memory system having termination resistor units: A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second... Agent: Volentine & Whitt PLLC
20090303803 - Independent bi-directional margin control per level and independently expandable reference cell levels for voltage mode sensing: A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.... Agent: Dla Piper LLP (us )
20090303804 - Semiconductor device and method for driving the same: A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an equalizing signal generating unit configured to generate an equalizing signal which is controlled with an overdriving voltage VPP... Agent: Ip & T Law Firm PLC
20090303806 - Synchronous semiconductor memory device: A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from... Agent: Sughrue Mion, PLLC
20090303807 - Semiconductor device and semiconductor system having the same: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank... Agent: Harness, Dickey & Pierce, P.L.C
20090303809 - Circuit and method for terminating data line of semiconductor integrated circuit: A data line termination circuit in a semiconductor integrated circuit includes a data line, a control unit for generating a termination control signal activated during a time section that includes a driving section in which data is driven to the data line, and a termination unit for terminating the data... Agent: Baker & Mckenzie LLP Patent Department
20090303808 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the... Agent: Ip & T Law Firm PLC
20090303812 - Programmable pulsewidth and delay generating circuit for integrated circuits: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at... Agent: Keusey, Tutunjian & Bitetto, P.C.
20090303811 - Row address decoder and semiconductor memory device having the same: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row... Agent: Ladas & Parry LLP
20090303810 - Semiconductor memory device: Disclosed is a semiconductor memory device. The semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for driving a first sub-word line signal in response to the first enable signal, a... Agent: Cooper & Dunham, LLP
20090303815 - Apparatus for redundancy reconfiguration of faculty memories: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input... Agent: Bacon & Thomas, PLLC
20090303814 - Integrated circuit that stores defective memory cell addresses: An integrated circuit including an array of memory cells, a circuit, volatile storage, and non-volatile storage. The circuit is configured to detect defective memory cells in the array of memory cells and provide addresses of the defective memory cells. The volatile storage is configured to store the addresses, where each... Agent: Dicke, Billig & Czaja
20090303813 - Integrated circuit that stores first and second defective memory cell addresses: An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses... Agent: Dicke, Billig & Czaja
20090303816 - Semiconductor memory apparatus and method of controlling redundancy thereof: A semiconductor memory apparatus includes a memory cell array. A redundancy controller that determines whether to activate a redundancy enable signal on the basis of a refresh signal and outputs the redundancy enable signal. A comparator outputs a redundancy selection signal in response to the redundancy enable signal and an... Agent: Venable LLP
20090303817 - Leakage testing method for dynamic random access memory having a recess gate: A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the... Agent: Jianq Chyun Intellectual Property Office
20090303818 - Test circuit device for semiconductor memory apparatus: A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local... Agent: Baker & Mckenzie LLP Patent Department
20090303820 - Apparatus and method for low power sensing in a multi-port sram using pre-discharged bit lines: A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different... Agent: Cantor Colburn LLP-ibm Burlington
20090303821 - Apparatus and method for low power, single-ended sensing in a multi-port sram using pre-discharged bit lines: An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being... Agent: Cantor Colburn LLP-ibm Burlington
20090303822 - Bit line equalizing control circuit of a semiconductor memory apparatus: A bit line equalizing control circuit of a semiconductor memory apparatus includes a control signal generating unit that receives a bank active signal to generate a control signal such that a bit line equalizing signal is delayed and enabled, a bit line equalizing selecting unit that generates a bit line... Agent: Baker & Mckenzie LLP Patent Department
20090303819 - Write and read assist circuit for sram with power recycling: A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected... Agent: Martine Penilla & Gencarella, LLP
20090303823 - Sense amp circuit, and semiconductor memory device using the same: A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at least one of the pair of first differential output signals reaching a certain voltage and provides an activation signal. A latch-type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090303824 - Dynamic random access memory device and method for self-refreshing memory cells: A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal.... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090303825 - Semiconductor memory device: A semiconductor memory device includes a first plurality of banks arranged in a first direction to form a first group of banks; a second plurality of banks arranged in the first direction to form a second group of banks, the first group of banks and the second group of banks... Agent: Ip & T Law Firm PLC
20090303826 - Static random-access memory with boosted voltages: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate... Agent: Treyz Law Group
20090303827 - Semiconductor memory device: A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in... Agent: Ip & T Law Firm PLC12/03/2009 > 72 patent applications in 38 patent subcategories. patent applications/inventions, industry category
Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.