|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
11/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval November recently filed with US Patent Office 11/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/26/2009 > 48 patent applications in 27 patent subcategories.
20090290400 - Bit cell designs for ternary content addressable memory: A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for comparing search data with content data stored in a ternary content addressable memory (TCAM) unit, includes a first static logic gate for comparing a... Agent: Texas Instruments Incorporated
20090290399 - Content addressable memory based on a ripple search scheme: A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM), includes a storage unit for storing a portion of content data, and a match module for comparing the portion of the content data with a... Agent: Texas Instruments Incorporated
20090290401 - Placement and optimization of process dummy cells: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield... Agent: International Business Machines Corporation Dept. 18g
20090290403 - Semiconductor device: According to an aspect of the present invention, there is provided a semiconductor device including: first and second blocks that each includes a word line group of first to N-th word lines, the word lines extending in a given direction, the word lines having a first width, the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090290402 - Semiconductor memory devices and methods of arranging memory cell arrays thereof: A semiconductor memory device and a method of arranging a memory cell array of the semiconductor device are provided. The semiconductor memory device has a memory cell array including a word line pair including a first word line and a second word line that are arranged in a first direction,... Agent: Harness, Dickey & Pierce, P.L.C
20090290404 - Semiconductor memory device: A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to... Agent: Mcdermott Will & Emery LLP
20090290406 - Low loading pad design for stt mram or other short pulse signal transmission: A low loading pad for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The low loading pad includes a plurality of hollow-shaped lower metal layers and a top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers.... Agent: Qualcomm Incorporated
20090290405 - Magnetic memory cell reading apparatus: The magnetic memory device is equipped with a plurality of storage cells laid out in two dimensions in (i+1) rows and (j+1) columns (where i, j are integers of one or higher). Two magnetoresistive effect revealing bodies 2a, 2b are disposed in each of the storage cells 1, and each... Agent: Greenblum & Bernstein, P.L.C
20090290407 - Memory cells, memory cell constructions, and memory cell programming methods: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through... Agent: Wells St. John P.s.
20090290409 - Pad design with buffers for stt-mram or other short pulse signal transmission: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input... Agent: Qualcomm Incorporated
20090290408 - Reconfigurable magnetic logic device using spin torque: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has... Agent: Campbell Nelson Whipps, LLC
20090290410 - Spin torque transfer mram device: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area,... Agent: Haynes And Boone, LLPIPSection
20090290412 - Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied... Agent: Wells St. John P.s.
20090290411 - Write verify method for resistive random access memory: Write verify methods for resistance random access memory (RRAM) are disclosed. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the... Agent: Campbell Nelson Whipps, LLC
20090290413 - Magnetic random access memory with an elliptical magnetic tunnel junction: A magnetic tunnel junction (MTJ)-based magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure and methods for manufacturing and using same. The TAS MTJ-based MRAM cell includes a magnetic tunnel junction that is formed with an anisotropic shape and that comprises a ferromagnetic storage layer,... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department
20090290415 - Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090290414 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090290416 - Nonvolatile semiconductor memory device: The nonvolatile semiconductor memory device related to an embodiment of the present invention includes a cell array including a memory string, a bit line connected to the memory string, a first wire connected to a cell source line of a memory cell, a second wire connected to a cell well... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090290417 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing... Agent: Muir Patent Consulting, PLLC
20090290418 - Method of verifying a program operation in a non-volatile memory device: A method of verifying a program operation in a non-volatile memory device includes performing a program operation, verifying whether or not each of a plurality of program target memory cells is programmed to a voltage higher than a verifying voltage, counting a number of fail status bits in response to... Agent: Mannava & Kang, P.C.
20090290419 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20090290420 - Program method of nonvolatile memory device: A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to... Agent: Ip & T Law Firm PLC
20090290421 - Flash memory device and method of programming the same: A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual... Agent: Marger Johnson & Mccollom, P.C.
20090290424 - Method and system for program pulse generation during programming of nonvolatile electronic devices: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence... Agent: Schwegman, Lundberg & Woessner / Atmel
20090290423 - Method of erasing a nonvolatile memory device: In a method of erasing a nonvolatile memory device, an erase operation is performed on memory cells of a selected block. A first soft program operation is performed on the cells on which the erase operation has been performed. The erase operation and the first soft program operation are repeatedly... Agent: Townsend And Townsend And Crew, LLP
20090290422 - Method of operating a nonvolatile memory device: A method of operating a nonvolatile memory device includes floating a drain select line, a source select line, a well, and a common source line of the nonvolatile memory device; precharging a program-inhibited bit line; and performing a program operation by applying a program voltage to a selected word line.... Agent: Townsend And Townsend And Crew, LLP
20090290425 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090290426 - Charge loss compensation during programming of a memory device: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090290427 - Method of erasing a nonvolatile memory device: The present invention relates to a method of erasing a nonvolatile memory device. According to an aspect of the present invention, an erase operation is performed on a selected memory block. The bit lines of the memory block are precharged, and a change of a voltage level of the bit... Agent: Townsend And Townsend And Crew, LLP
20090290428 - Read/verification reference voltage supply unit of nonvolatile memory device: A verification reference voltage supply unit includes a reference voltage supply unit, a temperature-dependent voltage supply unit, and an amplification unit. The reference voltage supply unit is configured to supply a first reference voltage and a second reference voltage, each of which is configured to maintain a constant value irrespective... Agent: Mannava & Kang, P.C.
20090290429 - Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage: Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting... Agent: Vierra Magen/sandisk Corporation
20090290430 - Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array: A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit... Agent: Dla Piper LLP (us )
20090290432 - Method of reading data in a non-volatile memory device: A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature of memory cells, setting a first voltage and a second voltage of a bit line sensing signal in accordance... Agent: Townsend And Townsend And Crew, LLP
20090290431 - Nonvolatile memory device: A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of memory cells of the memory cell area is connected by bit lines and word lines. The... Agent: Townsend And Townsend And Crew, LLP
20090290433 - Method of inputting address in nonvolatile memory device and method of operating the nonvolatile memory device: A method of inputting address in a nonvolatile memory device includes inputting a row address including an information for selecting a memory block and an information for selecting a page, and inputting a column including an information for selecting a column and an information for selecting a plane.... Agent: Mannava & Kang, P.C.
20090290434 - Dual function data register: A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090290435 - Nonvolatile memory device and method of testing the same: A nonvolatile memory device includes a clock input stage configured to receive a clock signal for a test, a control signal output unit configured to output data input-output (IO) control signals according to the clock signal, n number of IO stages for data IO, and n number of storage units... Agent: Mannava & Kang, P.C.
20090290436 - Test circuit for multi-port memory device: A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode.... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090290437 - Circuit for and an electronic device including a nonvolatile memory cell and a process of forming the electronic device: A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The... Agent: Larson Newman & Abel, LLP
20090290438 - Semiconductor memory device including write selectors: A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmitting data which... Agent: Mcdermott Will & Emery LLP
20090290439 - High performance metal gate polygate 8 transistor sram cell with reduced variability: A static random access memory cell includes a metal hi-k layer; a poly-SiON gate stack over the metal hi-k layer; a plurality of inverters disposed within the poly-SiON gate stack; and a plurality of field effect transistors placed in the metal hi-k layer.... Agent: Michael Buchenhorner, P.A.
20090290440 - Row addressing: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row... Agent: Fletcher Yoder (micron Technology, Inc.)
20090290441 - Memory block testing: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages,... Agent: Leffert Jay & Polglaze, P.A.
20090290442 - Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells).... Agent: Zilka-kotab, PC- Mrm1
20090290443 - Memory circuit with sense amplifier: A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal... Agent: Freescale Semiconductor, Inc. Law Department
20090290444 - Semiconductor device: A semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of... Agent: Knobbe Martens Olson & Bear LLP
20090290445 - Semiconductor device having latency counter: A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits for sequentially shifting the normal-phase (reverse-phase) command signal... Agent: Sughrue Mion, PLLC
20090290446 - Memory word-line tracking scheme: A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end... Agent: K & L Gates LLPIPDocketing11/19/2009 > 48 patent applications in 27 patent subcategories.
20090285006 - Semiconductor memory and method for operating a semiconductor memory: A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically... Agent: Slater & Matsil, L.L.P.
20090285007 - Integrated circuit with an array of resistance changing memory cells: An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation... Agent: Dicke, Billig & Czaja
20090285008 - Memory devices with selective pre-write verification and methods of operation thereof: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location... Agent: Myers Bigel Sibley & Sajovec
20090285009 - Nonvolatile memory devices using variable resistive elements: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory... Agent: Harness, Dickey & Pierce, P.L.C
20090285010 - Write assist circuit for improving write margins of sram cells: A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines.... Agent: Slater & Matsil, L.L.P.
20090285011 - Static random access memory: A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input... Agent: Alston & Bird LLP
20090285012 - Integrated circuit, cell arrangement, method of manufacturing an integrated circuit, method of operating an integrated circuit, and memory module: According to one embodiment of the present invention, an integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing... Agent: Slater & Matsil, L.L.P.
20090285013 - Magneto-resistance effect element and magnetic memory device: The invention relates to a magneto-resistance effect element and a magnetic memory device. Lowering the magnetic domain wall movement current and drive at room temperature in a current induction single magnetic domain wall movement phenomenon are achieved. A magneto-resistance effect element is formed by including at least: a magnet wire... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090285016 - Circuit for reading memory cells: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of... Agent: Trop, Pruner & Hu, P.C.
20090285014 - Integrated circuit and method for switching a resistively switching memory cell: An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch.... Agent: Dicke, Billig & Czaja
20090285015 - Phase-change memory device including biasing circuit: A memory cell device is provided which includes a substrate, a plurality of unit memory cells connected between a word line and respective bit lines, where each memory cell including a resistance variable element, such a phase-change element, and a diode connected in series between the word line and the... Agent: Volentine & Whitt PLLC
20090285017 - Memory device and memory: A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information... Agent: K&l Gates LLP
20090285018 - Gated diode memory cells: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate... Agent: F. Chau & Associates, LLC
20090285024 - Flash memory device, programming method thereof and memory system including the same: A verify voltage may be changed into a plurality of voltage levels based upon a logic state of each of the memory cells and characteristics or logic states of other memory cells (e.g., adjacent) to each of the memory cells.... Agent: Muir Patent Consulting, PLLC
20090285023 - Memory device and memory programming method: Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells... Agent: Harness, Dickey & Pierce, P.L.C
20090285022 - Memory programming method: A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the... Agent: Harness, Dickey & Pierce, P.L.C
20090285020 - Method of programming a multi level cell in a non-volatile memory device: In a method of programming a multi level cell, program speed increases as a program operation/erase operation is repeatedly performed. Particularly, in an ISPP method of reducing a program start voltage, much time may be required to finish a first verifying operation in an initial step where a few program... Agent: Townsend And Townsend And Crew, LLP
20090285021 - Non-volatile memory device and method of verifying a program operation in the same: A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to... Agent: Ip & T Law Firm PLC
20090285025 - Method of controlling a program control of a flash memory device: A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis.... Agent: Marshall, Gerstein & Borun LLP
20090285026 - Program and verify method of nonvolatile memory device: A program and verify method of a nonvolatile memory device, which can minimize the time taken for program and verify operations. The program and verify method includes precharging an output terminal of a block selector to a second level, making the output terminal of the block selector float, and, in... Agent: Ip & T Law Firm PLC
20090285027 - Non-volatile memory devices and methods of operating non-volatile memory devices: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are... Agent: Harness, Dickey & Pierce, P.L.C
20090285028 - Method of programming nonvolatile memory device: The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing a program operation on a first page, counting a program pulse application number until the program operation... Agent: Townsend And Townsend And Crew, LLP
20090285019 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090285029 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090285030 - Multi-bit nonvolatile memory devices and methods of operating the same: A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node... Agent: Harness, Dickey & Pierce, P.L.C
20090285034 - Latency counter, semiconductor memory device including the same, and data processing system: To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit... Agent: Sughrue Mion, PLLC
20090285035 - Pipelined wordline memory architecture: A method is provided for reducing semiconductor memory wordline propagation delays of long wordlines by inserting pipeline registers in the wordlines between groups of memory cells.... Agent: Duncan Elliott
20090285032 - Self pre-charging and equalizing bit line sense amplifier: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge... Agent: Law Office Of Monica H Choi
20090285033 - Semiconductor memory device: A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not... Agent: Young & Thompson
20090285036 - Fuse data read circuit having control circuit between fuse and current mirror circuit: A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided... Agent: Mcginn Intellectual Property Law Group, PLLC
20090285037 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Fish & Richardson P.C.
20090285038 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Fish & Richardson P.C.
20090285039 - Method and apparatus for locally generating a virtual ground for write assist on column selected sram cells: A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally... Agent: Ibm-acc-washington C/o Myers Andras Sherman LLP
20090285040 - Semiconductor memory device: A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a pair of storage nodes that are complementary to each other. One storage node constituting the pair of... Agent: SprinkleIPLaw Group
20090285041 - Non-volatile semiconductor storage device and method of writing data thereto: A non-volatile semiconductor storage device includes: a plurality of memory cells storing information based on a change in resistance value; and a plurality of first and second wirings connected to the plurality of memory cells and activated in reading data from and writing data to a certain one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090285031 - System and method for simulating an aspect of a memory circuit: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one... Agent: Zilka-kotab, PC- Mrm1
20090285042 - Memory interface circuit and memory system including the same: The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a... Agent: Harness, Dickey & Pierce, P.L.C
20090285043 - Block repair scheme: Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with... Agent: Fletcher Yoder (micron Technology, Inc.)
20090285044 - Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability: A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage... Agent: Qualcomm Incorporated
20090285045 - Area efficient first-in first-out circuit: A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the... Agent: Lng/lsi Joint Customer C/o Luedeka, Neely & Graham, P.C.
20090285046 - Method to reduce leakage of a sram-array: A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching... Agent: Michael J. Le Strange IBM Intellectual Property Law
20090285047 - Row decode driver gradient design in a memory device: A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The... Agent: Duft Bornsen & Fishman LLP
20090285048 - Counter circuit, latency counter, semiconductor memory device including the same, and data processing system: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first... Agent: Sughrue Mion, PLLC11/12/2009 > 48 patent applications in 27 patent subcategories.
20090279340 - N-way mode content addressable memory array: A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data... Agent: Farjami & Farjami LLP
20090279341 - Proximity optical memory module: A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20090279342 - Method to improve ferroelectric memory performance and reliability: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip.... Agent: Texas Instruments Incorporated
20090279343 - Operating method of electrical pulse voltage for rram application: Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090279344 - Resistance change memory device: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279345 - Resistive memory element sensing using averaging: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element... Agent: Dickstein Shapiro LLP
20090279346 - Fault tolerant asynchronous circuits: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.... Agent: Schwegman, Lundberg & Woessner, P.A.
20090279347 - Semiconductor memory device: A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different... Agent: Mcdermott Will & Emery LLP
20090279348 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279350 - Bipolar switching of phase change device: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090279349 - Phase change device having two or more substantial amorphous regions in high resistance state: Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090279351 - Semiconductor memory devices and methods having core structures for multi-writing: A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a... Agent: Myers Bigel Sibley & Sajovec
20090279352 - Storage nodes, phase change memories including a doped phase change layer, and methods of operating and fabricating the same: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change... Agent: Harness, Dickey & Pierce, P.L.C
20090279353 - Magnetic tunnel junction transistor: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least... Agent: Law Office Of Ido Tuchman (yor)
20090279354 - Stacked magnetic devices: Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying... Agent: Ryan, Mason & Lewis, LLP
20090279355 - Low power floating body memory cell based on low bandgap material quantum well: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.... Agent: Titash Rakshit
20090279356 - Nonvolatile semiconductor memory device: A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279357 - Nonvolatile semiconductor storage device and method of testing the same: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279358 - Semiconductor device and control method of the same: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090279360 - Nand based nmos nor flash memory cell, a nand based nmos nor flash memory array, and a method of forming a nand based nmos nor flash memory array: A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile... Agent: Saile Ackerman LLC
20090279359 - Nand with back biased operation: Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
20090279361 - Addressable memory array: This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte,... Agent: Fish & Richardson P.C.
20090279362 - Partial scrambling to reduce correlation: Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved... Agent: Zagorin O'brien Graham LLP (023)
20090279363 - Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090279364 - Method of programming in a flash memory device: A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is... Agent: Townsend And Townsend And Crew, LLP
20090279365 - Non-volatile semiconductor memory system: A non-volatile semiconductor memory system includes a first memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile semiconductor memory cells and a second memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279367 - Power saving sensing scheme for solid state memory: Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of... Agent: Knobbe Martens Olson & Bear LLP
20090279368 - Circuit and method for generating pumping voltage in semiconductor memory apparatus and semiconductor memory apparatus using the same: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external... Agent: Baker & Mckenzie LLP Patent Department
20090279369 - Data output apparatus and method for outputting data thereof: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals... Agent: Baker & Mckenzie LLP Patent Department
20090279366 - Hybrid solid-state memory system having volatile and non-volatile memory: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is... Agent: Eaton Peabody Patent Group, LLC
20090279370 - Memory circuit and method of sensing a memory element: The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20090279371 - Hybrid sense amplifier and method, and memory device using same: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090279372 - Semiconductor memory device and sense amplifier: In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying... Agent: Young & Thompson
20090279373 - Auto-refresh operation control circuit for reducing current consumption of semiconductor memory apparatus: An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation by receiving a precharge signal. The auto-refresh operation control circuit is configured to prevent an over-driving operation during an auto-refresh operation and... Agent: Ladas & Parry LLP
20090279376 - Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices: A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090279374 - System and method for mitigating reverse bias leakage: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of... Agent: Brooks, Cameron & Huebsch , PLLC
20090279375 - Voltage down converter for high speed memory: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current.... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090279377 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090279378 - Semiconductor memory device: A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a... Agent: Mannava & Kang, P.C.11/05/2009 > 48 patent applications in 27 patent subcategories.
20090273961 - Semiconductor device: A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and... Agent: Miles & Stockbridge PC
20090273960 - System for providing on-die termination of a control signal bus: A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090273962 - Four-terminal multiple-time programmable memory bitcell and array architecture: Embodiments disclosed herein relate to a non-volatile memory bitcell and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell is in an erased state, methods of setting the bitcell in a programmed state and methods of setting the bitcell in... Agent: Patterson & Sheridan, L.L.P.
20090273963 - Semiconductor storage device, semiconductor storage device manufacturing method and package resin forming method: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090273964 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends, a transition from the low resistance state to... Agent: Birch Stewart Kolasch & Birch
20090273966 - Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The... Agent: Slater & Matsil, L.L.P.
20090273967 - Method and integrated circuit for determining the state of a resistivity changing memory cell: A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result... Agent: Dicke, Billig & Czaja
20090273965 - Nonvolatile memory device: Ferromagnetic layers (18, 22) have magnetizations oriented to such directions as to cancel each other, so that the net magnetization of the ferromagnetic layers (18, 22) is substantially zero. That is, the ferromagnetic layers (18, 22) are exchange-coupled with a nonmagnetic layer (20) interposed therebetween, thereby forming an SAF structure.... Agent: Mcdermott Will & Emery LLP
20090273969 - Capacitive divider sensing of memory cells: The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.... Agent: Brooks, Cameron & Huebsch , PLLC
20090273970 - Memory device including a programmable resistance element: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times... Agent: Sughrue Mion, PLLC
20090273968 - Method and apparatus for implementing self-referencing read operation for pcram devices: A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay node,... Agent: Cantor Colburn LLP-ibm Burlington
20090273971 - Continuously driving non-volatile memory element: Embodiments discussed herein generally relate to utilizing non-volatile memory elements to continuously drive other circuitry. There are many advantages to utilizing non-volatile memory to continuously drive other circuitry. For example, back end of the line (BEOL) compatible process may be used to fabricate the non-volatile memory elements that does not... Agent: Patterson & Sheridan, L.L.P.
20090273972 - Magnetic logic element with toroidal multiple magnetic films and a method of logic treatment using the same: A magnetic logic element with toroidal magnetic multilayers (5,6,8,9). The magnetic logic element comprises a toroidal closed section which is fabricated by etching a unit of magnetic multilayers (5,6,8,9) deposited on a substrate. Optionally, the magnetic logic element may also comprise a metal core (10) in the closed toroidal section.... Agent: Connolly Bove Lodge & Hutz, LLP
20090273973 - Multi-level cell access buffer with dual function: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory... Agent: Smart & Biggar P.o. Box 2999, Station D
20090273975 - Non-volatile multilevel memory cells with data read of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold... Agent: Brooks, Cameron & Huebsch , PLLC
20090273974 - Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory: Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs... Agent: Cook Alex Ltd
20090273976 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090273977 - Multilayered nonvolatile memory with adaptive control: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix,... Agent: F. Chau & Associates, LLC
20090273980 - Nand architecture memory with voltage sensing: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell... Agent: Leffert Jay & Polglaze, P.A.
20090273978 - Nand flash memory: A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage higher than the first voltage to the control gate during the writing operation, and then... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090273979 - Programming method to reduce word line to word line breakdown for nand flash: A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage... Agent: Leffert Jay & Polglaze, P.A.
20090273981 - Methods and apparatuses for programming flash memory using modulated pulses: Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. Embodiments generally comprise a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. Alternative embodiments may include a threshold verifier capable of... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global
20090273982 - Semiconductor memory device, semiconductor device, and data write method: A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives the data held at the address from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090273983 - Nonvolatile memory device and programming method: Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-inhibited cells during the pass voltage charge operation, and applying the pass voltage to... Agent: Volentine & Whitt PLLC
20090273984 - Biasing system and method: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system... Agent: Fletcher Yoder (micron Technology, Inc.)
20090273987 - Data output circuit of semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal,... Agent: Venable LLP
20090273986 - Non-volatile memory with redundancy data buffered in remote buffer circuits: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090273985 - Semiconductor device having multiple i/o modes: Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to... Agent: Mannava & Kang, P.C.
20090273988 - Circuit and methods to improve the operation of soi devices: According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on... Agent: Connolly Bove Lodge & Hutz LLP
20090273989 - Synchronous command base write recovery time auto precharge control: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous... Agent: Fletcher Yoder (micron Technology, Inc.)
20090273990 - Semiconductor device: There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving... Agent: Mannava & Kang, P.C.
20090273991 - Semiconductor memory device, operating method thereof, and compression test method thereof: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the... Agent: Mannava & Kang, P.C.
20090273992 - Semiconductor device and operating method thereof: A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal operation, and to output the data strobe signal through a plurality of input paths in response to a... Agent: Mannava & Kang, P.C.
20090273993 - Semiconductor memory device and operation method thereof: A semiconductor memory device that generates a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof. The semiconductor memory device includes a pulse signal generating unit for generating first and second pulse signals by synchronizing a write instruction with first and second... Agent: Mannava & Kang, P.C.
20090273994 - Dual mode accessing signal control apparatus and dual mode timing signal generating apparatus: A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and... Agent: Holland & Knight LLP
20090273995 - Apparatus for removing crosstalk in semiconductor memory device: An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of... Agent: Mannava & Kang, P.C.
20090273996 - Memory testing system and memory module thereof: A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an... Agent: North America Intellectual Property Corporation
20090273997 - Controlling apparatus and controlling method for controlling a pre-charge activity on a sram array: A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090273998 - Bitcell current sense device and method thereof: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell... Agent: Larson Newman & Abel, LLP
20090273999 - Sense amplifier and data sensing method thereof: A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090274000 - System and method of command based and current limit controlled memory device power up: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be... Agent: Fletcher Yoder (micron Technology, Inc.)
20090274001 - Semiconductor memory device and method for operating the same: Semiconductor memory device and method for operating the same includes a data output unit configured to output data in synchronization with a data output clock and a clock control unit configured to selectively transfer the data output clock to the data output unit under the control of a read command.... Agent: Mannava & Kang, P.C.
20090274002 - Semiconductor integrated circuit and method of processing address and command signals thereof: A semiconductor integrated circuit device includes an input unit configured to receive address and command signals, an internal address generator configured to output an internal address signal by adjusting a timing of the input address signal to correspond to a predetermined internal signal processing timing margin, and an internal command... Agent: Baker & Mckenzie LLP Patent DepartmentPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.30968 seconds