Static information storage and retrieval inventions 10/09

20090244948 - Embedded memory apparatus with reduced power ring area: An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According... Agent: Rosenberg, Klein & Lee

20090244949 - Memory device and method providing logic connections for data transfer: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled... Agent: Slater & Matsil, L.L.P.

20090244950 - Semiconductor memory device highly integrated in direction of columns: First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets.... Agent: Mcdermott Will & Emery LLP

20090244952 - Electrode master for ferroelectric recording and method for recording on ferroelectric recording medium: The present invention provides an electrode master for ferroelectric recording that records information on a ferroelectric recording medium in which the direction of polarization of a ferroelectric material has been unified in one direction by applying a voltage thereto, based on the direction of polarization of the ferroelectric material by... Agent: Young & Thompson

20090244951 - Semiconductor memory device and semiconductor memory system: A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of... Agent: Mcdermott Will & Emery LLP

20090244953 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244954 - Structure and method for improving storage latch susceptibility to single event upsets: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and... Agent: Cantor Colburn LLP-ibm Burlington

20090244955 - Semiconductor storage device: This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels... Agent: Fujitsu Patent Center C/o Cpa Global

20090244956 - Semiconductor memory device: In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a... Agent: Posz Law Group, PLC

20090244958 - Hybrid superconducting-magnetic memory cell and array: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form... Agent: Wall & Tong, LLP IBM Corporation

20090244960 - Magnetoresistive effect element and magnetic memory: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244957 - Multilevel magnetic storage device: The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.

20090244959 - Thin film magnetic memory device writing data with bidirectional current: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets... Agent: Mcdermott Will & Emery LLP

20090244962 - Immunity of phase change material to disturb in the amorphous phase: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that... Agent: Trop, Pruner & Hu, P.C.

20090244961 - Phase change memory: The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of... Agent: Brooks, Cameron & Huebsch , PLLC

20090244963 - Programming multilevel cell phase change memories: A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result,... Agent: Trop, Pruner & Hu, P.C.

20090244964 - Reducing temporal changes in phase change memories: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.... Agent: Trop, Pruner & Hu, P.C.

20090244965 - Multi-layer magnetic random access memory using spin-torque magnetic tunnel junctions and method for write state of the multi-layer magnetic random access memory: A stacked magnetic tunnel junction (MTJ) structure of a multi-layer magnetic random access memory (MRAM) which includes a plurality of stacked MTJ devices serially connected to each other and an access transistor shared between the stacked MTJ devices. The stacked MTJ structure further includes a write word line through which... Agent: Cantor Colburn LLP-ibm Yorktown

20090244969 - Semiconductor memory device comprising memory cell having charge accumulation layer and control gate and method of erasing data thereof: A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244968 - Semiconductor memory device including memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a select transistor, a memory cell transistor, a select gate line, a word line, and a row decoder. The memory cell transistor includes a charge accumulation layer and a control gate, and a current path one end of which is connected to a current path... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244971 - Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device: A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling... Agent: Nixon & Vanderhye, PC

20090244972 - Nonvolatile semiconductor memory device and usage method thereof: A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being... Agent: The Marbury Law Group, PLLC

20090244970 - Random access memory with cmos-compatible nonvolatile storage element and parallel storage capacitor: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20090244973 - Memory read-out: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system... Agent: Slater & Matsil, L.L.P.

20090244974 - Memory system and data writing method: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244975 - Flash memory device and block selection circuit thereof: The present invention relates to a block selection circuit of a flash memory device. The block selection circuit includes a control signal output unit, switching means, and an operation controller. The control signal output unit outputs a control signal for enabling or disabling memory blocks connected thereto by employing block... Agent: Townsend And Townsend And Crew, LLP

20090244976 - Non-volatile semiconductor memory device: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states... Agent: Mcdermott Will & Emery LLP

20090244977 - Variable initial program voltage magnitude for non-volatile storage: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional... Agent: Vierra Magen/sandisk Corporation

20090244967 - Flash memory device having dummy cells and method of operating the same: Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.... Agent: Volentine & Whitt PLLC

20090244966 - Threshold evaluation of eprom cells: Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090244978 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244979 - Erase degradation reduction in non-volatile memory: Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20090244980 - Method for reducing lateral movement of charges and memory device thereof: Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the... Agent: Harness, Dickey & Pierce, P.L.C

20090244983 - Flash memory device and program method thereof: A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic... Agent: F. Chau & Associates, LLC

20090244982 - Memory block reallocation in a flash memory device: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have... Agent: Leffert Jay & Polglaze, P.A.

20090244981 - Non-volatile semiconductor memory device and its writing method: It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244984 - Method for driving a nonvolatile semiconductor memory device: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244985 - Method for erasing a p-channel non-volatile memory: A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge... Agent: Jianq Chyun Intellectual Property Office

20090244988 - Compiled memory, asic chip, and layout method for compiled memory: Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A... Agent: Arent Fox LLP

20090244987 - Dynamic column block selection: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090244986 - Semiconductor memory device and methods thereof: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read... Agent: Harness, Dickey & Pierce, P.L.C

20090244989 - Bitline voltage driver: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090244990 - Semiconductor memory device: A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to... Agent: Young & Thompson

20090244991 - Semiconductor memory device: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090244992 - Integrated circuit and method for reading the content of a memory cell: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal... Agent: Slater & Matsil, L.L.P.

20090244994 - Data strobe signal generating circuit capable of easily obtaining valid data window: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to... Agent: Cooper & Dunham, LLP

20090244993 - Maintaining dynamic count of fifo contents in multiple clock domains: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In... Agent: Cochran Freund & Young LLC Lsi Corporation

20090244995 - Circuit for locking a delay locked loop (dll) and method therefor: A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data... Agent: Larson Newman & Abel, LLP

20090244996 - Circuit using a shared delay locked loop (dll) and method therefor: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output... Agent: Larson Newman & Abel, LLP

20090244997 - Method for training dynamic random access memory (dram) controller timing delays: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value... Agent: Larson Newman & Abel, LLP

20090244998 - Synchronous memory device: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially... Agent: F. Chau & Associates, LLC

20090244999 - Clock control during self-test of multi port memory: A multiport memory 18, 20 is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be used as a shared... Agent: Nixon & Vanderhye P.C.

20090245001 - Integrated circuit and method for testing the circuit: An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal,... Agent: Arent Fox LLP

20090245000 - Semiconductor integrated circuit: A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a... Agent: Knobbe Martens Olson & Bear LLP

20090245002 - Semiconductor memory device having high stability and quality of readout operation: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second... Agent: Volentine & Whitt PLLC

20090245003 - Semiconductor memory device, method of operating semiconductor memory device, and memory system: A semiconductor memory device is provided which comprises: a sense amplifier; and a bit line, wherein the disconnection of the sense amplifier from the bit line is performed in a data read operation when temperature in the semiconductor memory device is at a first temperature, and wherein the disconnection of... Agent: Arent Fox LLP

20090245004 - Semiconductor device including multi-chip: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must... Agent: Mattingly & Malur, P.C.

20090245005 - Recovery of existing sram capacity from fused-out blocks: A system, device, and method are disclosed. In one embodiment the system includes an interconnect within an integrated circuit. The system also includes a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the... Agent: Intel Corporation C/o Cpa Global

20090245006 - Semiconductor memory device: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output... Agent: Foley And Lardner LLP Suite 500

20090245007 - Selectively controlled memory: Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed.... Agent: Schwabe, Williamson & Wyatt, P.C.

20090245008 - System and method for providing voltage power gating: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090245009 - 256 meg dynamic random access memory: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are... Agent: Jones Day

20090245010 - Data driver circuit for a dynamic random access memory (dram) controller or the like and method therefor: A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an... Agent: Larson Newman & Abel, LLP

20090245011 - Wordline driver for dram and driving method thereof: A wordline driver for DRAM comprises a multiplexer, an inverter and a transistor switch. One end of the multiplexer is connected to a wordline charging voltage, and the other end is connected to an external voltage, wherein the external voltage is less than the wordline charging voltage, and initially the... Agent: Connolly Bove Lodge & Hutz LLP

20090245012 - Semiconductor storage device and memory system: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.... Agent: Arent Fox LLP

20090245013 - Sequential storage circuitry for an integrated circuit: Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it... Agent: Nixon & Vanderhye P.C.