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Static information storage and retrieval October categorized by USPTO classification 10/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/30/2009 > patent applications in patent subcategories. categorized by USPTO classification
10/23/2009 > patent applications in patent subcategories. categorized by USPTO classification
10/15/2009 > patent applications in patent subcategories. categorized by USPTO classification
20090257262 - Dram and memory array: A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction,... Agent: Jianq Chyun Intellectual Property Office
20090257263 - Method and apparatus for computer memory: A method and apparatus for forming computer memory 10 including RAM, ROM, Stacks and other registers. The memory array 10 includes a number of individual memory cells 40, 42, 44, 46 connected to each other by word lines 18, 20 and bit lines 30, 32. Memory cells 40, 42, 44,... Agent: Henneman & Associates, PLC
20090257270 - Damascene integration methods for graphitic films in three-dimensional memories and memories formed therefrom: In some aspects, a microelectronic structure is provided that includes (1) a first conducting layer; (2) a first dielectric layer formed above the first conducting layer and having a feature that exposes a portion of the first conducting layer; (3) a graphitic carbon film disposed on a sidewall of the... Agent: Dugan & Dugan, PC
20090257269 - Low-complexity electronic circuits and methods of forming the same: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.... Agent: Goodwin Procter LLP Patent Administrator
20090257264 - Memory and method of evaluating a memory state of a resistive memory cell: An integrated circuit comprises a first signal line, a second signal line and a resistive memory cell. The resistive memory cell is actively connectable to the first signal line. The integrated circuit further comprises a coupling device configured to generate a difference of potential between the first and second signal... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090257265 - Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same: A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090257266 - Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same: A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element,... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090257267 - Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same: A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a... Agent: Zagorin O'brien Graham LLP (023)
20090257271 - Resistance change element and method of manufacturing the same: In a resistance change memory (ReRAM) storing data by utilizing change in resistance of a resistance change element, a lower electrode (ground-side electrode) of the resistance change element is formed of a transition metal such as Ni, and an upper electrode (positive polarity-side electrode) is configured of a noble metal... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090257268 - Semiconductor device having single-ended sensing amplifier: A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal... Agent: Mcginn Intellectual Property Law Group, PLLC
20090257273 - 2t sram cell structure: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N... Agent: Wpat, PC
20090257272 - Reduced size charge pump for dram system: A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality of bank enable signals; a plurality of charge pump components, coupled between the plurality of memory banks and the bank... Agent: North America Intellectual Property Corporation
20090257274 - Semiconductor memory device: A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20090257275 - Seasoning phase change memories: A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.... Agent: Trop, Pruner & Hu, P.C.
20090257278 - Flash memory device having shared row decoder: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a... Agent: Volentine & Whitt PLLC
20090257279 - Memory device operation: Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20090257281 - Method of programming a flash memory device using self boosting: A method of programming a flash memory device controls a channel boosting level to ensure device properties. The flash memory device is programmed in an Incremental Step Pulse Program (ISPP) manner by applying a program voltage to a selected memory cell and a pass voltage to unselected memory cells. The... Agent: Townsend And Townsend And Crew, LLP
20090257280 - Nand flash memory device and method of operating same: An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection... Agent: F. Chau & Associates, LLC
20090257282 - Non-volatile storage system with initial programming voltage based on trial: A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a... Agent: Vierra Magen/sandisk Corporation
20090257277 - Flash memory including reduced swing amplifiers: For realizing low power and high speed flash memory, reduced swing amplifiers are used for reading, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense... Agent: Juhan Kim
20090257276 - Nonvolatile analog memory: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns... Agent: Jianq Chyun Intellectual Property Office
20090257283 - Method for deleting data from nand type nonvolatile memory: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data... Agent: Eric Robinson
20090257284 - Method and apparatus for improving storage performance using a background erase: Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy... Agent: Trask Britt, P.C./ Micron Technology
20090257286 - Apparatus and method for outputting data in semiconductor integrated circuit: An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to... Agent: Baker & Mckenzie LLP Patent Department
20090257285 - Semiconductor memory apparatus: A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by... Agent: Baker & Mckenzie LLP Patent Department
20090257288 - Apparatus and method for increasing data line noise tolerance: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current... Agent: Leffert Jay & Polglaze, P.A.
20090257289 - Internal voltage generator and semiconductor memory device including the same: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending... Agent: Mannava & Kang, P.C.
20090257287 - Programmable bias circuit architecture for a digital data/clock receiver: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20090257290 - Low power shift register and semiconductor memory device including the same: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock... Agent: Mannava & Kang, P.C.
20090257292 - Semiconductor device having resistance based memory array, method of reading, and writing, and systems associated therewith: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.... Agent: Harness, Dickey & Pierce, P.L.C
20090257293 - Semiconductor memory device: A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the... Agent: Mcdermott Will & Emery LLP
20090257291 - Semiconductor memory device and method for generating pipe-in signal thereof: A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in... Agent: Mannava & Kang, P.C.
20090257294 - Programmable linear receiver for digital data clock signals: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20090257295 - Randomizing current consumption in memory devices: In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory... Agent: Fish & Richardson P.C.
20090257297 - Multi-chip semiconductor device providing enhanced redundancy capabilities: A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the... Agent: Volentine & Whitt PLLC
20090257296 - Programmable memory repair scheme: The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage... Agent: Sidley Austin LLP
20090257298 - Semiconductor device having single-ended sensing amplifier: A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit... Agent: Mcginn Intellectual Property Law Group, PLLC
20090257299 - Software refreshed memory device and method: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory... Agent: Dickstein Shapiro LLP
20090257300 - Fuse information control device, semiconductor integrated circuit using the same, and control method thereof: A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of... Agent: Baker & Mckenzie LLP Patent Department
20090257302 - Semiconductor memory apparatus capable of reducing ground noise: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP
20090257301 - Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels,... Agent: Baker & Mckenzie LLP Patent Department10/08/2009 > patent applications in patent subcategories. categorized by USPTO classification
20090251939 - Priority encoder: A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with... Agent: Martine Penilla & Gencarella, LLP
20090251940 - Nonvolatile semiconductor memory device using a variable resistance film and method of manufacturing the same: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090251941 - Semiconductor device: A semiconductor device is provided, which includes a transistor, a memory element, a first control circuit and a second control circuit. A gate of the transistor is electrically connected to the first control circuit through a first word line, one of a source and a drain of the transistor is... Agent: Cook Alex Ltd
20090251942 - Method of programming a memory device of the one-time programmable type and integrated circuit incorporating such a memory: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode.... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20090251943 - Test circuit for an unprogrammed otp memory array: Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090251944 - Memory cell having improved mechanical stability: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090251945 - System and method of operation for resistive change memory: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes a data storage element which includes a variable resistance and an electrode, and a controller which selects a first mode that stores data by the resistance value of the variable resistance and a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090251946 - Data cells with drivers and methods of making and operating the same: Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In... Agent: Wells St. John P.s.
20090251947 - Semiconductor device having single-ended sensing amplifier: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use... Agent: Mcginn Intellectual Property Law Group, PLLC
20090251948 - Semiconductor memory device: In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the... Agent: Sughrue Mion, PLLC
20090251949 - Array structural design of magnetoresistive random access memory (mram) bit cells: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source... Agent: Qualcomm Incorporated
20090251950 - Integrated circuit, memory cell arrangement, thermal select magneto-resistive memory cell, method of operating a thermal select magneto-resistive memory cell, and method of manufacturing a thermal select magneto-resistive memory cell: According to one embodiment of the present invention, an integrated circuit includes a thermal select magneto-resistive memory cell. The memory cell includes a stack of layers including a storage memory layer. The memory cell also includes a heating element which covers at least a part of the sidewalls of the... Agent: Slater & Matsil, L.L.P.
20090251951 - Magnetoresistive element and magnetic random access memory: A magnetoresistive element includes a foundation layer, a first magnetic layer on the foundation layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer is made of a ferromagnetic metal containing one or more elements selected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090251952 - State machine sensing of memory cells: The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell... Agent: Brooks, Cameron & Huebsch , PLLC
20090251953 - Variable resistance memory device: A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word... Agent: Harness, Dickey & Pierce, P.L.C
20090251954 - Variable resistance memory device and system: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second... Agent: Volentine & Whitt PLLC
20090251956 - Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same: A magnetic memory device includes a lower structure or an antiferromagnetic layer, a pinned layer, an information storage layer, and a free layer formed on the lower structure or the antiferromagnetic layer. In a method of operating a magnetic memory device, information from the storage information layer is read or... Agent: Harness, Dickey & Pierce, P.L.C
20090251955 - Mram and data read/write method for mram: An MRAM according to the present invention is provided with a magnetic recording layer being a ferromagnetic layer and a pinned layer connected to the magnetic recording layer through a nonmagnetic layer. The magnetic recording layer includes a magnetization switching region, a first magnetization fixed region and a second magnetization... Agent: Young & Thompson
20090251957 - System and method for writing data to magnetoresistive random access memory cells: Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department
20090251958 - Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory... Agent: Neil Steinberg
20090251959 - Semiconductor memory device and driving method thereof: A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090251960 - High temperature memory device: Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on... Agent: Krueger Iselin LLP (1391)
20090251962 - Three-dimensional memory device and driving method thereof: A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A... Agent: F. Chau & Associates, LLC
20090251963 - Non-volatile memory device and method of manufacturing the same: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the... Agent: Harness, Dickey & Pierce, P.L.C
20090251965 - Nonvolatile memory device including circuit formed of thin film transistors: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.... Agent: Mcdermott Will & Emery LLP
20090251964 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the present invention is a NAND-type flash memory which is electrically capable of programming/erasing. The nonvolatile semiconductor memory device has at least 3 or more memory cell columns in which a plurality of memory cells are connected in series, and these memory cell... Agent: Miles & Stockbridge PC
20090251966 - Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location... Agent: Law Office Of Alan W. Cannon
20090251968 - Integrated circuit having a base structure and a nanostructure: In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.... Agent: Slater & Matsil, L.L.P.
20090251967 - Non-volatile storage having a connected source and well: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line... Agent: Vierra Magen/sandisk Corporation
20090251969 - Analog read and write paths in a solid state memory device: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.
20090251970 - Semiconductor device and control method thereof: A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090251961 - Flash memory device and voltage generating circuit for the same: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate... Agent: Volentine & Whitt PLLC
20090251971 - Non-volatile semiconductor storage device and memory system: According to an aspect of the invention, a non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090251972 - Nonvolatile memory arrays with charge trapping dielectric and with non-dielectric nanodots: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.... Agent: Haynes And Boone, LLPIPSection
20090251973 - Trench monos memory cell and array: The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode.... Agent: Saile Ackerman LLC
20090251974 - Memory circuits with reduced leakage power and design structures for same: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the... Agent: Ryan, Mason & Lewis, LLP
20090251975 - Circuit and method for a sense amplifier with instantaneous pull up/pull down sensing: A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the... Agent: Slater & Matsil, L.L.P.
20090251976 - Method and apparatus for dqs postamble detection and drift compensation in a double data rate (ddr) physical interface: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control... Agent: Abelman, Frayne & Schwab
20090251977 - Device having malfunction preventing circuit: A fixing device fixes a toner image on a recording medium. The fixing device includes a heat source that converts electric power into heat and a fixing member that gives the heat generated by the heat source to the recording medium on which the toner image is formed. The fixing... Agent: Patterson & Sheridan, L.L.P.
20090251978 - Integration of lbist into array bisr flow: A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090251979 - Method for suppressing current leakage in memory: A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing... Agent: Jianq Chyun Intellectual Property Office
20090251980 - Semiconductor memory device: A semiconductor memory device includes a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sense amplifier. The charging transistor charges a bit line from a... Agent: Young & Thompson
20090251981 - Memory with a fast stable sensing amplifier: A memory includes a memory cell, a sensing amplifier, four N-type MOS transistors, a reference circuit, and a comparator. The sensing amplifier is used for sensing digital data stored in the memory cell of the memory and generating an output signal corresponding to the digital data when the memory cell... Agent: North America Intellectual Property Corporation
20090251982 - Low energy memory component: The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for... Agent: Morgan Lewis & Bockius LLP/rambus Inc.
20090251985 - Semiconductor memory apparatus: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response... Agent: Venable LLP
20090251983 - Semiconductor memory apparatus capable of reducing ground noise: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP
20090251984 - Static memory device and static random access memory device: A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage... Agent: Lee & Morse, P.C.
20090251986 - Fifo peek access: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read... Agent: Cochran Freund & Young LLC Lsi Corporation
20090251987 - Memory data transfer: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals... Agent: Courtney Staniford & Gregory LLP
20090251988 - System and method for providing a non-power-of-two burst length in a memory system: A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length... Agent: Cantor Colburn LLP-ibm Poughkeepsie10/01/2009 > patent applications in patent subcategories. categorized by USPTO classification
20090244948 - Embedded memory apparatus with reduced power ring area: An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According... Agent: Rosenberg, Klein & Lee
20090244949 - Memory device and method providing logic connections for data transfer: In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled... Agent: Slater & Matsil, L.L.P.
20090244950 - Semiconductor memory device highly integrated in direction of columns: First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets.... Agent: Mcdermott Will & Emery LLP
20090244952 - Electrode master for ferroelectric recording and method for recording on ferroelectric recording medium: The present invention provides an electrode master for ferroelectric recording that records information on a ferroelectric recording medium in which the direction of polarization of a ferroelectric material has been unified in one direction by applying a voltage thereto, based on the direction of polarization of the ferroelectric material by... Agent: Young & Thompson
20090244951 - Semiconductor memory device and semiconductor memory system: A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of... Agent: Mcdermott Will & Emery LLP
20090244953 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244954 - Structure and method for improving storage latch susceptibility to single event upsets: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and... Agent: Cantor Colburn LLP-ibm Burlington
20090244955 - Semiconductor storage device: This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels... Agent: Fujitsu Patent Center C/o Cpa Global
20090244956 - Semiconductor memory device: In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a... Agent: Posz Law Group, PLC
20090244958 - Hybrid superconducting-magnetic memory cell and array: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form... Agent: Wall & Tong, LLP IBM Corporation
20090244960 - Magnetoresistive effect element and magnetic memory: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244957 - Multilevel magnetic storage device: The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.... Agent: Seagate Technology LLC C/o Westman, Champlin & Kelly, P.A.
20090244959 - Thin film magnetic memory device writing data with bidirectional current: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets... Agent: Mcdermott Will & Emery LLP
20090244962 - Immunity of phase change material to disturb in the amorphous phase: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that... Agent: Trop, Pruner & Hu, P.C.
20090244961 - Phase change memory: The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of... Agent: Brooks, Cameron & Huebsch , PLLC
20090244963 - Programming multilevel cell phase change memories: A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result,... Agent: Trop, Pruner & Hu, P.C.
20090244964 - Reducing temporal changes in phase change memories: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.... Agent: Trop, Pruner & Hu, P.C.
20090244965 - Multi-layer magnetic random access memory using spin-torque magnetic tunnel junctions and method for write state of the multi-layer magnetic random access memory: A stacked magnetic tunnel junction (MTJ) structure of a multi-layer magnetic random access memory (MRAM) which includes a plurality of stacked MTJ devices serially connected to each other and an access transistor shared between the stacked MTJ devices. The stacked MTJ structure further includes a write word line through which... Agent: Cantor Colburn LLP-ibm Yorktown
20090244969 - Semiconductor memory device comprising memory cell having charge accumulation layer and control gate and method of erasing data thereof: A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244968 - Semiconductor memory device including memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a select transistor, a memory cell transistor, a select gate line, a word line, and a row decoder. The memory cell transistor includes a charge accumulation layer and a control gate, and a current path one end of which is connected to a current path... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244971 - Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device: A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling... Agent: Nixon & Vanderhye, PC
20090244972 - Nonvolatile semiconductor memory device and usage method thereof: A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being... Agent: The Marbury Law Group, PLLC
20090244970 - Random access memory with cmos-compatible nonvolatile storage element and parallel storage capacitor: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20090244973 - Memory read-out: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system... Agent: Slater & Matsil, L.L.P.
20090244974 - Memory system and data writing method: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244975 - Flash memory device and block selection circuit thereof: The present invention relates to a block selection circuit of a flash memory device. The block selection circuit includes a control signal output unit, switching means, and an operation controller. The control signal output unit outputs a control signal for enabling or disabling memory blocks connected thereto by employing block... Agent: Townsend And Townsend And Crew, LLP
20090244976 - Non-volatile semiconductor memory device: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states... Agent: Mcdermott Will & Emery LLP
20090244977 - Variable initial program voltage magnitude for non-volatile storage: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional... Agent: Vierra Magen/sandisk Corporation
20090244967 - Flash memory device having dummy cells and method of operating the same: Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.... Agent: Volentine & Whitt PLLC
20090244966 - Threshold evaluation of eprom cells: Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20090244978 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244979 - Erase degradation reduction in non-volatile memory: Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090244980 - Method for reducing lateral movement of charges and memory device thereof: Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the... Agent: Harness, Dickey & Pierce, P.L.C
20090244983 - Flash memory device and program method thereof: A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic... Agent: F. Chau & Associates, LLC
20090244982 - Memory block reallocation in a flash memory device: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have... Agent: Leffert Jay & Polglaze, P.A.
20090244981 - Non-volatile semiconductor memory device and its writing method: It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244984 - Method for driving a nonvolatile semiconductor memory device: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244985 - Method for erasing a p-channel non-volatile memory: A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge... Agent: Jianq Chyun Intellectual Property Office
20090244988 - Compiled memory, asic chip, and layout method for compiled memory: Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A... Agent: Arent Fox LLP
20090244987 - Dynamic column block selection: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090244986 - Semiconductor memory device and methods thereof: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read... Agent: Harness, Dickey & Pierce, P.L.C
20090244989 - Bitline voltage driver: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090244990 - Semiconductor memory device: A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to... Agent: Young & Thompson
20090244991 - Semiconductor memory device: A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090244992 - Integrated circuit and method for reading the content of a memory cell: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal... Agent: Slater & Matsil, L.L.P.
20090244994 - Data strobe signal generating circuit capable of easily obtaining valid data window: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to... Agent: Cooper & Dunham, LLP
20090244993 - Maintaining dynamic count of fifo contents in multiple clock domains: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In... Agent: Cochran Freund & Young LLC Lsi Corporation
20090244995 - Circuit for locking a delay locked loop (dll) and method therefor: A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data... Agent: Larson Newman & Abel, LLP
20090244996 - Circuit using a shared delay locked loop (dll) and method therefor: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output... Agent: Larson Newman & Abel, LLP
20090244997 - Method for training dynamic random access memory (dram) controller timing delays: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value... Agent: Larson Newman & Abel, LLP
20090244998 - Synchronous memory device: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially... Agent: F. Chau & Associates, LLC
20090244999 - Clock control during self-test of multi port memory: A multiport memory 18, 20 is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be used as a shared... Agent: Nixon & Vanderhye P.C.
20090245001 - Integrated circuit and method for testing the circuit: An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal,... Agent: Arent Fox LLP
20090245000 - Semiconductor integrated circuit: A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a... Agent: Knobbe Martens Olson & Bear LLP
20090245002 - Semiconductor memory device having high stability and quality of readout operation: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second... Agent: Volentine & Whitt PLLC
20090245003 - Semiconductor memory device, method of operating semiconductor memory device, and memory system: A semiconductor memory device is provided which comprises: a sense amplifier; and a bit line, wherein the disconnection of the sense amplifier from the bit line is performed in a data read operation when temperature in the semiconductor memory device is at a first temperature, and wherein the disconnection of... Agent: Arent Fox LLP
20090245004 - Semiconductor device including multi-chip: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must... Agent: Mattingly & Malur, P.C.
20090245005 - Recovery of existing sram capacity from fused-out blocks: A system, device, and method are disclosed. In one embodiment the system includes an interconnect within an integrated circuit. The system also includes a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the... Agent: Intel Corporation C/o Cpa Global
20090245006 - Semiconductor memory device: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output... Agent: Foley And Lardner LLP Suite 500
20090245007 - Selectively controlled memory: Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed.... Agent: Schwabe, Williamson & Wyatt, P.C.
20090245008 - System and method for providing voltage power gating: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090245009 - 256 meg dynamic random access memory: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are... Agent: Jones Day
20090245010 - Data driver circuit for a dynamic random access memory (dram) controller or the like and method therefor: A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an... Agent: Larson Newman & Abel, LLP
20090245011 - Wordline driver for dram and driving method thereof: A wordline driver for DRAM comprises a multiplexer, an inverter and a transistor switch. One end of the multiplexer is connected to a wordline charging voltage, and the other end is connected to an external voltage, wherein the external voltage is less than the wordline charging voltage, and initially the... Agent: Connolly Bove Lodge & Hutz LLP
20090245012 - Semiconductor storage device and memory system: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.... Agent: Arent Fox LLP
20090245013 - Sequential storage circuitry for an integrated circuit: Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it... Agent: Nixon & Vanderhye P.C.Previous industry: Electric power conversion systems
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