|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
09/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval September class, title,number 09/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/24/2009 > patent applications in patent subcategories.
- Process variation compensated multi-chip memory package: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection... Agent: Volentine & Whitt PLLC
- Semiconductor memory devices with interface chips having memory chips stacked thereon: A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips... Agent: Myers Bigel Sibley & Sajovec
- Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells: A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the... Agent: Dicke, Billig & Czaja
- Design method for read-only memory devices: A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address... Agent: Ip Legal Services
- One-time programmable memory cell: A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as... Agent: Farjami & Farjami LLP
- Programmable memory cell: A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The... Agent: Farjami & Farjami LLP
- N-ary three-dimensional mask-programmable read-only memory: N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of N-3DROM over other N-ary memory (e.g. multi-level-cell flash) is that its array efficiency... Agent: Guobiao Zhang
- Semiconductor device having resistance based memory array, method of reading, and systems associated therewith: In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store... Agent: Harness, Dickey & Pierce, P.L.C
- Semiconductor memory device and semiconductor memory system: A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Sensing resistance variable memory: The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold... Agent: Brooks, Cameron & Huebsch , PLLC
- Dynamic memory word line driver scheme: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
- Electromechanical switch and method of forming the same: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the... Agent: F. Chau & Associates, LLC
- Magnetically de-coupling magnetic tunnel junctions and bit/word lines for reducing bit selection errors in spin-momentum transfer switching: Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic... Agent: Ryan, Mason & Lewis, LLP
- Integrated circuit including memory element doped with dielectric material: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing... Agent: Dicke, Billig & Czaja
- Memory cell: Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using... Agent: Brooks, Cameron & Huebsch , PLLC
- Nonvolatile memory device using variable resistive element: A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls... Agent: F. Chau & Associates, LLC
- Semiconductor device and its fabrication method: An electrically rewritable non-volatile memory device is configured by the EEPROM 3, and an electrically non-rewritable non-volatile memory device is configured by the OTPROM 4a. Both the EEPROM 3 and the OTPROM 4a are configured by phase change memory devices each of which can be fabricated in the same fabrication... Agent: Mattingly & Malur, P.C.
- Crossbar diode-switched magnetoresistive random access memory system: A magnetic memory or MRAM memory system comprising an M×N crossbar array of MRAM cells. Each memory cell stores binary data bits with switchable magnetoresistive tunnel junctions (MJT) where the electrical conductance changes as the magnetic moment of one electrode (the storage layer) in the MJT switches direction. The switching... Agent: K&l Gates LLP
- Magnetic memory device: A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
- Magnetic memory device: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ... Agent: Mcdermott Will & Emery LLP
- Sonos device with insulating storage layer and p-n junction isolation: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
- Iterative memory cell charging based on reference cell value: Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group... Agent: Fish & Richardson P.C.
- Nonvolatile semiconductor memory device and control method: The nonvolatile semiconductor memory device related to the present invention includes a plurality of memory cells, a read/program circuit which supplies a program voltage and a program verification voltage to the plurality of memory cells and desired data is programmed, supplies a first program verification voltage to the plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Semiconductor memory device having stacked gate including charge accumulation layer and control gate: A semiconductor memory device includes a memory cell, a bit line, a source line, a detection circuit, and a sense amplifier. The memory cell holds or more levels of data. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Scaleable memory systems using third dimension memory: A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays... Agent: Unity Semiconductor Corporation
- Memory structure having volatile and non-volatile memory portions: A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active... Agent: Fletcher Yoder (micron Technology, Inc.)
- Random access memory with cmos-compatible nonvolatile storage element: Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
- Adaptive algorithm in cache operation with dynamic data latch requirements: A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
- Different combinations of wordline order and look-ahead read to improve non-volatile memory performance: For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a wordline can store are written concurrently. More than one, but less than all... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
- Systems and devices including multi-gate transistors and methods of using, making, and operating the same: Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit line and another terminal disposed on alternating sides of the digit line. In some embodiments, each transistor among the plurality of transistors comprises a... Agent: Fletcher Yoder (micron Technology, Inc.)
- Interface for nand-type flash memory: A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface includes a standard NAND flash interface pin arrangement and a clock (CLK) pin. The synchronous NAND interface is configured to interface with a... Agent: Slater & Matsil, L.L.P.
- Nand type non-volatile memory and operating method thereof: A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row.... Agent: Jianq Chyun Intellectual Property Office
- Non-volatile semiconductor memory device: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Method of operating sonos memory device: A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the... Agent: Lee & Morse, P.C.
- Multi-plane type flash memory and methods of controlling program and read operations thereof: A multi-plane type flash memory device comprises a plurality of planes each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plane or latching an output data bit to be received from the corresponding plane, cache buffers each... Agent: Townsend And Townsend And Crew, LLP
- Adjusting programming or erase voltage pulses in response to the number of programming or erase failures: Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A number of the memory cells that failed to program or erase is determined and is compared to... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum
- Method of supplying an operating voltage of a flash memory device: A method of supplying an operating voltage of a flash memory device includes supplying an operating voltage to a word line selected according to an input address, and changing a pass voltage according to a change of the operating voltage level. The pass voltage is supplied to unselected word lines... Agent: Townsend And Townsend And Crew, LLP
- System for operating a memory device: A system for operating a memory device comprises a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a... Agent: Jianq Chyun Intellectual Property Office
- Non-volatile memory cell with btbt programming: A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as... Agent: Nixon Peabody LLP
- Controlling slew rate performance across different output driver impedances: Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength... Agent: Fletcher Yoder (micron Technology, Inc.)
- System and method for reducing pin-count of memory devices, and memory device testers for same: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode... Agent: Dorsey & Whitney LLP Intellectual Property Department
- Systems and devices including multi-transistor cells and methods of using, making, and operating the same: Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row... Agent: Wells St. John P.s.
- Vcc control inside data register of memory device: A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a... Agent: Cool Patent, P.C. C/o Cpa Global
- Semiconductor device: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1”... Agent: Brundidge & Stanger, P.C.
- Appartus and method for controlling refresh with current dispersion effect in semiconductor device: A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is... Agent: Cooper & Dunham, LLP
- Circuits to delay signals from a memory device: Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying... Agent: Schwegman, Lundberg & Woessner / Atmel
- Digital dll circuit: A digital delay locked loop circuit generates a delay value to delay the timing of taking in read-data by a memory interface when data is read from a memory. The digital delay locked loop circuit includes a selector that selects either one of a clock signal and a data strobe... Agent: Arent Fox LLP
- Low power synchronous memory command address scheme: A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal;... Agent: North America Intellectual Property Corporation
- Integrated circuit including built-in self test circuit to test memory and memory test method: An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided... Agent: Mcginn Intellectual Property Law Group, PLLC
- Bit line precharge circuit having precharge elements outside sense amplifier: A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second... Agent: Cooper & Dunham, LLP
- Integrated circuit including memory refreshed based on temperature: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh... Agent: Dicke, Billig & Czaja
- Semiconductor memory device and operation method therefor: Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which requires a refresh operation is formed; an interface section configured to carry out an interfacing process between an external apparatus and the memory array section; and a refresh control block for controlling the... Agent: Lerner, David, Littenberg, Krumholz & Mentlik
- Semiconductor device and controlling method of semiconductor device: A semiconductor device includes: a setting circuit which sets a first setting value; a control circuit which receives a predetermined control signal and the first setting value so as to output a second setting value; and an output circuit which outputs a predetermined level in response to the first setting... Agent: Mcdermott Will & Emery LLP
- Memory system: A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit... Agent: Quintero Law Office, PC
- Semiconductor memory device removing parasitic coupling capacitance between word lines: A semiconductor memory device includes a main word line shared by a plurality of mats. Each of the mats includes a plurality of sub word lines. A decoding unit is configured to decode a row address bit and output a word line driving signal. A plurality of sub word line... Agent: Ladas & Parry LLP
- Memory controller with staggered request signal output: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is... Agent: Shemwell Mahamedi LLP09/17/2009 > patent applications in patent subcategories.
- Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively... Agent: Neil Steinberg
- Multi-chip package: A multi-chip package includes a plurality of memory chips and a control chip. The control chip stores information about whether the memory chips are operating normally and selects chips that are operating normally according to an address signal.... Agent: Townsend And Townsend And Crew, LLP
- Phase change random access memory and layout method of the same: A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region and a global wordline is formed in the active region so as to intersect with the... Agent: Ladas & Parry LLP
- Fuse devices and methods of operating the same: A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.... Agent: Harness, Dickey & Pierce, P.L.C
- Semiconductor integrated circuit for supporting a test mode: A semiconductor integrated circuit for supporting a test mode includes a program region including at least one One Time Programmable Cell Array, and a program region control unit configured to activate the program region in response to an enabled fuse signal of a fuse corresponding to the program region, and... Agent: Baker & Mckenzie LLP Patent Department
- Ferroelectric memory and method for testing the same: A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the... Agent: Knobbe Martens Olson & Bear LLP
- Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first... Agent: Schwabe, Williamson & Wyatt, P.C.
- Semiconductor memory device: A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Nonvolatile semiconductor memory device, and writing method, reading method and erasing method of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a memory cell including a resistance memory element which changes from a low resistance state into a high resistance state by application of a voltage which is higher than a reset voltage and lower than a set voltage and changes from the high resistance... Agent: Westerman, Hattori, Daniels & Adrian, LLP
- Memory using variable tunnel barrier widths: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory... Agent: Unity Semiconductor Corporation
- Non-volatile electrochemical memory device: A non-volatile electrochemical memory cell formed of a stack of thin films comprising at least one first active layer, suited to releasing and accepting, in a reversible manner, at least one ion species, at least one second active layer, suited to releasing and accepting said ion species, in a reversible... Agent: Pearne & Gordon LLP
- Semiconductor storage device and operation method thereof: A semiconductor storage device includes: a bit line; a first word line; a second word line; a first inverter in which one terminal of a first load transistor is connected to a first driver transistor and their junction point forms a first node; a second inverter in which one terminal... Agent: Sonnenschein Nath & Rosenthal LLP
- Magnetoresistive tunnel junction magnetic device and its application to mram: The magnetic device comprises a magnetic device comprising a magnetoresistive tunnel junction (100), itself comprising: a reference magnetic layer (120) having magnetization in a direction that is fixed; a storage magnetic layer (110) having magnetization in a direction that is variable; and an intermediate layer (130) acting as a tunnel... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP
- Non-volatile memory with resistive access component: Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value... Agent: Schwegman, Lundberg & Woessner/micron
- Phase change memory adaptive programming: Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range,... Agent: Schwegman, Lundberg & Woessner/micron
- Phase change memory cell with constriction structure: Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may... Agent: Schwegman, Lundberg & Woessner/micron
- Semiconductor device: There is provided a technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the... Agent: Miles & Stockbridge PC
- Memory devices and methods: Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage... Agent: Harness, Dickey & Pierce, P.L.C
- Reading array cell with matched reference cell: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
- Non-volatile memory device: A non-volatile memory device increases a number of word lines and a storage capacity using a multi level cell. The non-volatile memory device addresses a problem of self-boosting not being adequately generated due to the increased number of word lines. The non-volatile memory device includes a memory cell array configured... Agent: Townsend And Townsend And Crew, LLP
- Flash memory device and method for programming flash memory device having leakage bit lines: Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation... Agent: Volentine & Whitt PLLC
- Interleaved memory program and verify method, device and system: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory... Agent: Trask Britt, P.C./ Micron Technology
- Semiconductor memory device and erase method in the same: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the... Agent: Townsend And Townsend And Crew, LLP
- Manufacturing method of nonvolatile semiconductor storage device and nonvolatile semiconductor storage device: In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a... Agent: Miles & Stockbridge PC
- Nonvolatile memory device and read method thereof: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second... Agent: F. Chau & Associates, LLC
- Programming method and memory device using the same: A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
- Nonvolatile semiconductor storage device and operation method thereof: A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Reduction of punch-through disturb during programming of a memory device: In one or more of the disclosed embodiments, a punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing word lines on the drain side of the series string with a Vpass voltage,... Agent: Leffert Jay & Polglaze, P.A.
- Analog sensing of memory cells with a source follower driver in a semiconductor memory device: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
- Read reference technique with current degradation protection: A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The... Agent: Larson Newman & Abel, LLP
- Method of testing a non-volatile memory device: A method of testing a non-volatile memory device on a wafer is disclosed. The method includes performing an erase operation and a first verify operation about every memory cell in the non-volatile memory device, storing data of a first latch in a page buffer for storing result in accordance with... Agent: Townsend And Townsend And Crew, LLP
- Non-volatile semiconductor memory with page erase: In a nonvolatile memory, less than a full block may be erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block.... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
- Memory and control unit: A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an... Agent: Schwabe, Williamson & Wyatt, P.C.
- Internal voltage generating circuit having selectively driven drivers in semiconductor memory apparatus: An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output... Agent: Baker & Mckenzie LLP Patent Department
- Low power memory architecture: A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can... Agent: Borden Ladner Gervais LLP Anne Kinsman
- Semiconductor device and method comprising a high voltage reset driver and an isolated memory array: A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set... Agent: Texas Instruments Incorporated
- Semiconductor memory device with signal aligning circuit: A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals... Agent: Mannava & Kang, P.C.
- Advanced bit line tracking in high performance memory compilers: A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling... Agent: Qualcomm Incorporated
- Memory with write port configured for double pump write: A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of the... Agent: Mhkkg/sun
- Memory device having strobe terminals with multiple functions: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of... Agent: Schwegman, Lundberg & Woessner/micron
- Address multiplexing in pseudo-dual port memory: A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to... Agent: Qualcomm Incorporated
- Method of operating a non-volatile memory device: A method of operating a non-volatile memory device reduces a time for discharging a precharged voltage when a program operation or a read operation is performed, thereby decreasing a total operation time of the non-volatile memory device. The non-volatile memory device discharges a bit line and a word line using... Agent: Townsend And Townsend And Crew, LLP
- Circuit and method for a vdd level memory sense amplifier: A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control... Agent: Slater & Matsil, L.L.P.
- Memory and voltage monitoring device thereof: A memory and a voltage monitoring device thereof are provided. the voltage monitoring device of the memory includes a system voltage detector, a charge pump circuit and a data output unit. The system voltage detector is coupled to the charge pump circuit and the data output unit for detecting a... Agent: J C Patents, Inc.
- Memory system with low current consumption and method for the same: A memory system includes: a high-voltage-supply booster circuit for driving an access control circuit from a low voltage for memory access to a high voltage for memory access by supplying electric charge that is stored in advance to an access control circuit in response to an access start request for... Agent: Ibm Corporation RochesterIPLaw Dept. 917
- Three-dimensional memory devices and methods of manufacturing and operating the same: A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at... Agent: Jianq Chyun Intellectual Property Office
- Assymetric data path position and delays technique enabling high speed access in integrated circuit memory devices: An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the... Agent: Hogan & Hartson LLP
- Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks: A multi-bank block architecture for integrated circuit memory devices which effectively reduces the total length of the datapath for a given input/output (I/O) from the memory cells in the memory array to the actual device I/O pad. In accordance with the present, a memory block in a memory device is... Agent: Hogan & Hartson LLP
- Multi-bank memory device method and apparatus: In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically... Agent: Coats & Bennett/qimonda
- Semiconductor memory device having column decoder: A semiconductor memory device includes a cell matrix having a number of cells, a multiplicity of column decoders for selectively activating the cells in response to code signals containing column address information for the cells, wherein each column decoder contains a pre-driving unit for providing a state output signal transiting... Agent: Blakely Sokoloff Taylor & Zafman LLP
- Semiconductor integrated circuit having address control circuit: A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in response to a column command signal and... Agent: Baker & Mckenzie LLP Patent Department
- Data output circuit having shared data output control unit: A data output circuit is provided which is capable of reducing a size and current consumption by commonly using a data output control unit for a plurality of data output units. The data output circuit includes a data output control unit for receiving an external clock signal and generate clock... Agent: Cooper & Dunham, LLP09/10/2009 > patent applications in patent subcategories.
- Low cost, high-density rectifier matrix memory: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.... Agent: Goodwin Procter LLP Patent Administrator
- Integrated circuit, memory module, and method of manufacturing an integrated circuit: An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.... Agent: Slater & Matsil, L.L.P.
- Multi-bit memory device using multi-plug: A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode... Agent: Harness, Dickey & Pierce, P.L.C
- Data retention structure for non-volatile memory: A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage... Agent: Unity Semiconductor Corporation
- Resistive memory device for programming resistance conversion layers and method thereof: Example embodiments provide a method for programming a resistive memory device that includes a resistance conversion layer. The method may include applying multiple pulses to the resistance conversion layer. The multiple pulses may include at least two pulses, where a magnitude of each pulse of the at least two pulses... Agent: Harness, Dickey & Pierce, P.L.C
- Random access memory with cmos-compatible nonvolatile storage element in series with storage capacitor: Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
- Self-contained charge storage molecules for use in molecular capacitors: The invention encompasses self-contained charge storage molecules for use in memory devices such as for example static, permanent and dynamic random access memory. In particular, the invention encompasses molecules possessing structural features, which allow such molecules to form self-contained charge storage units for use, for example, in a molecular capacitor.... Agent: Morgan, Lewis & Bockius, LLP. (pa)
- Magnetoresistive element: A magnetoresistive element includes a first magnetic layer which includes a first surface and a second surface and has a first standard electrode potential, a second magnetic layer, a barrier layer which is provided between the second magnetic layer and the first surface of the first magnetic layer, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Semiconductor memory device: A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Memory device: A phase-change memory device includes a first insulator having a hole therethrough, a first electrode that conforms at least partially to the hole, a phase-change material in electrical communication with the first electrode, and a second electrode in electrical communication with the phase-change material. When current is passed from the... Agent: Honigman Miller Schwartz & Cohn LLP
- Phase change memory device accounting for volume change of phase change material and method for manufacturing the same: A phase change memory device includes a silicon substrate including a plurality of active regions which extend in a first direction and are arranged at regular intervals in a second direction perpendicular to the first direction. Switching elements are formed in each active region of the silicon substrate and are... Agent: Ladas & Parry LLP
- Phase change random access memory: Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation... Agent: Harness, Dickey & Pierce, P.L.C
- Resistive memory device: A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage correlative to a resistance state of the resistive memory element. The sensing circuit if further configured to sense the voltage correlative to the resistance... Agent: Fletcher Yoder (micron Technology, Inc.)
- Suspended structures: A multi-level lithography processes for the fabrication of suspended structures are presented. The process is based on the differential exposure and developing conditions of several a plurality of resist layers, without harsher processes, such as etching of sacrificial layers or the use of hardmasks. These manufacturing processes are readily suited... Agent: Knobbe Martens Olson & Bear LLP
- Flash multi-level threshold distribution scheme: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while... Agent: Borden Ladner Gervais LLP Anne Kinsman
- Method of operating a flash memory device: A method of operating a flash memory device includes reading a first bit data by employing a first read voltage or a second read voltage higher than the first read voltage according to a program state of a first flag cell. The first flag cell is programmed when the first... Agent: Townsend And Townsend And Crew, LLP
- Multi-level nonvolatile memory device using variable resistive element: A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell,... Agent: F. Chau & Associates, LLC
- Non-volatile memory device and method of operating the same: A non-volatile memory device is disclosed. The non-volatile memory device includes an encoder configured to set random data in a unit of a word line, and generate second data to be programmed in a memory cell by performing logic operation about the random data and first data inputted for program,... Agent: Townsend And Townsend And Crew, LLP
- Nonvolatile memory device and method of operating the same and control device for controlling the same: A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input... Agent: Mannava & Kang, P.C.
- Method apparatus, and system providing adjustable memory page configuration: A method, apparatus and system are described which provide a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.... Agent: Dickstein Shapiro LLP
- Flash memory device and program method thereof: A flash memory device that includes a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to verify the program operation, respectively; and... Agent: F. Chau & Associates, LLC
- Nonvolatile semiconductor storage device: A nonvolatile semiconductor memory comprising: a plurality of memory cell blocks each including a plurality of memory cells serially connected to each other; a word line that is connected to corresponding ones of the plurality of memory cells each included in respective one of the plurality of memory cellblocks; and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Storage unit of single-conductor non-volatile memory cell and method of erasing the same: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over... Agent: J C Patents, Inc.
- Multi-state memory cell: Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric and/or the intergate dielectric. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
- Reprogrammable nonvolatile memory devices and methods: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array.... Agent: Myers Bigel Sibley & Sajovec
- Non-volatile memory and-array: A non-volatile memory cell on a semiconductor substrate includes a first and a second transistor. Each transistor is arranged as a memory element that includes two diffusion regions capable of acting as either source or drain, a charge storage element and a control gate element. A channel region is located... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
- Nitride read-only memory cell and nitride read-only memory array: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other... Agent: Jianq Chyun Intellectual Property Office
- Erase block data splitting: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs... Agent: Leffert Jay & Polglaze, P.A.
- Semiconductor memory device: When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory... Agent: Stroock & Stroock & Lavan LLP
- Apparatus and method for detecting word line leakage in memory devices: Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a... Agent: Townsend And Townsend And Crew, LLP
- Devices, systems, and methods for a power generator system: Methods, devices, and systems are disclosed for a power generator system. A power generator system ay comprise at least one control device including control logic. The at least one control device may be configured to receive at least one control signal and output an upper reference voltage and lower reference... Agent: Trask Britt, P.C./ Micron Technology
- Integrated circuit that selectively outputs subsets of a group of data bits: An integrated circuit including an array of memory cells, a control circuit, and an output circuit. The array of memory cells is configured to provide a group of data bits. The control circuit is configured to provide a test mode signal. The output circuit is configured to receive the test... Agent: Dicke, Billig & Czaja
- Method of testing nonvolatile memory device: A method includes performing test bit setting; programming a first page using data set by the test bit setting, and storing a fail status bit in a page buffer, which is connected to a first bit line having a fail status, based on a verification result of the test program;... Agent: Mannava & Kang, P.C.
- Digit line equilibration using access devices at the edge of sub-arrays: A method of equilibrating digit lines, a memory array device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second... Agent: Trask Britt, P.C./ Micron Technology
- Twin cell architecture for integrated circuit dynamic random access memory (dram) devices and those devices incorporating embedded dram: A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage... Agent: Hogan & Hartson LLP
- Sense amplifier circuit and method for a dram: A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with... Agent: Graybeal Jackson LLP
- Erasing control circuit and method for erasing environment configuration memory in a computer system: A computer system includes a power switch, a reset switch, environment configuration memory, and an erasing control circuit. The power switch is for starting the computer system as triggered. The reset switch is for resetting the computer system as triggered. The environment configuration memory is for storing an operational environment... Agent: Rabin & Berdo, PC
- Memory that retains data when switching partial array self refresh settings: A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array... Agent: Dicke, Billig & Czaja
- System and method for hidden-refresh rate modification: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when... Agent: Trask Britt, P.C./ Micron Technology
- Power management module for memory module: A power management module for a memory module is provided. The memory module is coupled to a chipset. The power management module includes a basic input/output system (BIOS), a power regulation module, and a DC-DC converter module. The BIOS is coupled to the chipset, and contains a power consumption data... Agent: J C Patents, Inc.
- Pumping circuit for multiple nonvolatile memories: A pumping circuit for multiple nonvolatile memories, comprising: a high voltage source; and a high voltage pass block with a gate controlled by a local booster to introduce the high voltage source into a plurality of nonvolatile memories for erase/write operation.... Agent: Wpat, PC
- Semiconductor memory apparatus: A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the core voltage to the compensation voltage input node; a compensation controlling unit configured to generate a compensation control signal to determine... Agent: Venable LLP
- Split decoder storage array and methods of forming the same: A memory device includes a memory array comprising a plurality of generally parallel rows and a plurality of generally parallel columns intersecting the plurality of rows; a first address decoder circuit disposed on a first side of the memory array; and a second address decoder circuit disposed on a second... Agent: Goodwin Procter LLP Patent Administrator
- Circuit and methods for eliminating skew between signals in semicoductor integrated circuit: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data... Agent: Volentine & Whitt PLLC
- Method, device and system for reducing the quantity of interconnections on a memory device: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion... Agent: Trask Britt, P.C./ Micron Technology09/03/2009 > patent applications in patent subcategories.
- Range-matching cell and content addressable memories using the same: A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell (100); a first comparator (110) connected to the memory cell; a second comparator (120) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators... Agent: Harness, Dickey & Pierce, P.L.C
- Diagonal connection storage array: In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets... Agent: Goodwin Procter LLP Patent Administrator
- Memory module and memory device: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal,... Agent: Young & Thompson
- Semiconductor memory device: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
- Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
- Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
- Circuit arrangement comprising a non-volatile memory cell and method: The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory... Agent: Cohen, Pontani, Lieberman & Pavane LLP
- Method of programming a memory having electrically programmable fuses: An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal,... Agent: Freescale Semiconductor, Inc. Law Department
- Ferroelectric memory device: A ferroelectric memory includes ferroelectric capacitors including ferroelectric films between first electrodes and second electrodes; cell transistors; and a bit line contact connecting the cell transistors to a bit line, wherein the first electrode is connected to one of source and drain of the cell transistor at a first node,... Agent: Knobbe Martens Olson & Bear LLP
- Method and apparatus for implementing concurrent multiple level sensing operation for resistive memory devices: An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data... Agent: Cantor Colburn LLP-ibm Burlington
- Nonvolatile memory device and method of controlling the same: A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Phase change memory: A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
- Apparatus and method for improving storage latch susceptibility to single event upsets: An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state circuit coupled to separate data nodes within the DICE latch; and... Agent: Cantor Colburn LLP-ibm Burlington
- Magnetic memory device: A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
- Magnetoresistive device and magnetic memory using the same: A magnetic film stack is composed of a synthetic antiferromagnet including a plurality of ferromagnetic layers, adjacent two of which are antiferromagnetically coupled through a non-magnetic layer; and a reversal inducing layer exhibiting ferromagnetism. The reversal inducing layer is ferromagnetically coupled to the synthetic antiferromagnet, and designed to have a... Agent: Foley And Lardner LLP Suite 500
- Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device: A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode... Agent: Slater & Matsil, L.L.P.
- Integrated circuit including an electrode having an outer portion with greater resistivity: An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the... Agent: Dicke, Billig & Czaja
- Magnetic storage device: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
- Double programming methods of a multi-level-cell nonvolatile memory: A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
- Multi-bit flash memory device and memory cell array: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.... Agent: Volentine & Whitt PLLC
- Memory device having read cache: A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and... Agent: Dla Piper LLP (us )
- Charge loss compensation during programming of a memory device: A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed.... Agent: Leffert Jay & Polglaze, P.A.
- Semiconductor memory device: A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit... Agent: Arent Fox LLP
- Non-volatile memory: A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in... Agent: J C Patents, Inc.
- Semiconductor memory device for high-speed data input / output: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer... Agent: Blakely Sokoloff Taylor & Zafman LLP
- Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programmed into a memory cell and changes the data held according to a verify result from the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
- Apparatus, system, and method for adjusting memory hold time: An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first... Agent: Kunzler & Mckenzie
- Pre-charge voltage generation and power saving modes: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC
- Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof: A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper... Agent: Mannava & Kang, P.C.
- I/o circuit with phase mixer for slew rate control: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines.... Agent: Dorsey & Whitney LLP Intellectual Property Department
- Semiconductor memory device and operation method thereof: Semiconductor memory device and operation method thereof includes an output enable signal generator configured to synchronize a read command to a data clock signal to generate an output enable signal according to a CAS latency, a sampling control signal generator configured to generate a sampling control signal that is activated... Agent: Blakely Sokoloff Taylor & Zafman LLP
- Adjusting a digital delay function of a data memory unit: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read... Agent: Coats & Bennett, PLLC
- Integrated circuit, method for acquiring data and measurement system: An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The... Agent: Slater & Matsil LLP
- Semiconductor memory device: Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality... Agent: Blakely Sokoloff Taylor & Zafman LLP
- Semiconductor memory device and parallel test method of the same: Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outside of a chip.... Agent: Mannava & Kang, P.C.
- Non-volatile memory device with plural reference cells, and method of setting the reference cells: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to... Agent: Dla Piper LLP (us )
- Multi-chip assembly and method for driving the same: Disclosed are a multi-chip assembly and a method for driving the same. The multi-chip assembly includes a first chip designed with a first device driven by a first power source and a second chip designed with a second device driven by a second power source. A power applying section applies... Agent: Ladas & Parry LLP
- Back-gate decode personalization: A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4th) terminal (substrates/bodies) of MOSFET devices is implemented by the present invention to realize a novel decode personalization. The novel construction and operation of the decode personalization provides... Agent: Scully, Scott, Murphy & Presser, P.C.
- Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals: Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory... Agent: Qualcomm IncorporatedPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.78565 seconds