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Static information storage and retrieval August inventions list 08/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
08/27/2009 > patent applications in patent subcategories. inventions list

20090213632 - System and method for providing content-addressable magnetoresistive random access memory cells: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic... Agent: Orrick, Herrington & Sutcliffe, LLP Ip Prosecution Department

20090213633 - Four vertically stacked memory layers in a non-volatile re-writeable memory device: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon... Agent: Unity Semiconductor Corporation

20090213634 - Stacked memory and fuse chip: A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut... Agent: Sughrue Mion, Pllc

20090213635 - Semiconductor memory device having replica circuit: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second... Agent: Turocy & Watson, LLP

20090213637 - Ferroelectric random access memory device: An FRAM device can includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines... Agent: Mills & Onello LLP

20090213636 - Layered bi compound nanoplate array of such nanoplates, their making methods and devices using them: A Bi4Ti3O12 nanoplate, an array of such Bi4Ti3O12 nanoplate and their making methods as well as their applications are provided. Using a vapor phase growth method, a flux layer of VOx is deposited on a SrTiO3 (001) faced substrate and then Bi4Ti3O12 is deposited on the flux layer. A Bi4Ti3O12... Agent: Masao Yoshimura, Chen Yoshimura LLP

20090213638 - Magnectic memory element and magnetic memory apparatus: A magnetic memory element is provided with first and second ferromagnetic fixed layers, a ferromagnetic memory layer, nonmagnetic first and second intermediate layers. The memory layer is disposed between the first and second fixed layers, and has a variable magnetization direction. In order to cancel asymmetry of a write-in current... Agent: Nixon & Vanderhye, Pc

20090213640 - Current driven memory cells having enhanced current and enhanced current symmetry: A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents... Agent: Virtual Law Partners LLP

20090213639 - Resistance change memory device: A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090213641 - Memory with active mode back-bias voltage control and method of operating same: Data storage cells of a static random access memory array are selectively provided with back-bias voltages to reduce current leakage during an active mode of operation. Circuitry electrically connected with the array receives control signals and provides the back-bias voltages to certain idle data storage cells of the array based... Agent: Brooks Kushman P.c. / Sun / Stk

20090213642 - Integrated circuit, memory cell arrangement, memory cell, memory module, method of operating an integrated circuit, and method of manufacturing a memory cell: According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured... Agent: Slater & Matsil, L.l.p.

20090213643 - Integrated circuit and method of improved determining a memory state of a memory cell: According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the... Agent: Slater & Matsil, L.l.p.

20090213644 - Method and apparatus for accessing a multi-mode programmable resistance memory: A memory is configurable among a plurality of operational modes. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix.... Agent: Ovonyx, Inc

20090213645 - Method and apparatus for accessing a multi-mode programmable resistance memory: A memory is configurable among a plurality of operational modes and types of interfaces. The operational modes may dictate the number of storage levels to be associated with each cell within the memory's storage matrix. Individual operational modes may be matched to individual interfaces, operated one at a time or... Agent: Ovonyx, Inc

20090213646 - Phase-change random access memories capable of suppressing coupling noise during read-while-write operation: A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line... Agent: Harness, Dickey & Pierce, P.L.C

20090213647 - Phase-change random access memory capable of reducing word line resistance: A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed.... Agent: Harness, Dickey & Pierce, P.L.C

20090213648 - Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective... Agent: Edell, Shapiro & Finnan, Llc

20090213650 - Mis-transistor-based nonvolatile memory: A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate... Agent: Ladas & Parry

20090213649 - Semiconductor processing device and ic card: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted... Agent: Miles & Stockbridge Pc

20090213654 - Programming analog memory cells for reduced variance after retention: A method includes defining a nominal level of a physical quantity to be stored in analog memory cells for representing a given data value. The given data value is written to the cells in first and second groups of the cells, which have respective first and second programming responsiveness such... Agent: D. Kligler I.p. Services Ltd

20090213652 - Programming method for non-volatile memory device: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first... Agent: Volentine & Whitt Pllc

20090213653 - Programming of analog memory cells using a single programming pulse per state transition: A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells. The data... Agent: D. Kligler I.p. Services Ltd

20090213651 - Two-bit non-volatile flash memory cells and methods of operating memory cells: A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit... Agent: Jianq Chyun Intellectual Property Office

20090213655 - Memory system with user configurable density/performance option: The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20090213657 - Electronic device comprising non volatile memory cells and corresponding programming method: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20090213656 - Flash memory having insulating liners between source/drain lines and channels: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090213658 - Reading non-volatile storage with efficient setup: A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the... Agent: Vierra Magen/sandisk Corporation

20090213659 - Flash memory device and flash memory system including the same: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data... Agent: F. Chau & Associates, Llc

20090213660 - Three-terminal single poly nmos non-volatile memory cell: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090213661 - Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within... Agent: Volentine & Whitt Pllc

20090213662 - Memory device and applications thereof: A system that incorporates teachings of the present disclosure may include, for example, a memory device having a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values. Additional embodiments are disclosed.... Agent: Akerman Senterfitt

20090213668 - Adjustable pipeline in a memory circuit: A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one... Agent: Zagorin O'brien Graham LLP (115)

20090213663 - Circuits, devices, systems, and methods of operation for capturing data signals: Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090213664 - Nonvolatile memory utilizing mis memory transistors with function to correct data reversal: A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the... Agent: Ladas & Parry LLP

20090213665 - Nonvolatile semiconductor memory device: Provided is a nonvolatile semiconductor memory device which reads out a memory cell at high speed. A minute current source (105) is connected to a clamp NMOS transistor (103) for clamping a drain voltage of a memory cell (101), and a minute current is caused to flow through the clamp... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.

20090213666 - Low voltage operation bias current generation circuit: Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor... Agent: Fletcher Yoder (micron Technology, Inc.)

20090213667 - Semiconductor memory device enhancing reliability in data reading: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line... Agent: Mcdermott Will & Emery LLP

20090213669 - High voltage switch circuit having boosting circuit and flash memory device including the same: A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in... Agent: Townsend And Townsend And Crew, LLP

20090213670 - Asynchronous, high-bandwidth memory component using calibrated timing elements: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are... Agent: Shemwell Mahamedi LLP

20090213671 - Circuit and method for controlling redundancy in semiconductor memory apparatus: Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral... Agent: Ladas & Parry LLP

20090213672 - Logic embedded memory having registers commonly used by macros: A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090213673 - Data processor memory circuit: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory... Agent: Nixon & Vanderhye P.c.

20090213674 - Method and device for controlling a memory access and correspondingly configured semiconductor memory: A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells... Agent: Lee & Hayes, Pllc

20090213675 - Semiconductor memory device: A memory includes memory cells, wherein in a first cycle of writing first logic data, sense amplifiers apply a first potential to bit lines, drivers apply a second potential to a selected word line and a third potential to a selected source line, and the second and third potentials with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090213678 - High yielding, voltage, temperature, and process insensitive lateral poly fuse memory: The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding,... Agent: Michael J. Ure

20090213677 - Memory cell array: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the... Agent: Cypress Semiconductor Corporation

20090213676 - Memory device: A nonvolatile memory device contains at least one nonvolatile memory module and an electrical buffer for buffering a supply voltage for the at least one nonvolatile memory module. A microprocessor may be connected in parallel or serial fashion to the memory device, or may contain the memory device.... Agent: Kenyon & Kenyon LLP

20090213680 - Method and apparatus for monitoring memory addresses: Disclosed herein is a method and apparatus for monitoring a memory address transmitted along an address path and converted into a row or column address of memory. The method includes: generating a path decision signal for deciding whether to connect the address path to a data terminal of the memory... Agent: Edwards Angell Palmer & Dodge LLP

20090213679 - Power dependent memory access: An apparatus and method of accessing a memory by determining available power, and accessing a number of bits of the memory in parallel, wherein the number of bits accessed in parallel is based at least in part on the available power.... Agent: Dickstein Shapiro LLP

  
08/20/2009 > patent applications in patent subcategories. inventions list

20090207641 - Novel transmission lines for cmos integrated circuits: Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based... Agent: Schwegman, Lundberg & Woessner/micron

20090207642 - Semiconductor signal processing device: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors... Agent: Mcdermott Will & Emery LLP

20090207643 - Data storage devices using magnetic domain wall movement and methods of operating the same: Data storage devices using movement of magnetic domain walls and methods of operating the same are provided. A data storage device includes a magnetic track having a verifying region. Within the verifying region, first and second magnetic domains are arranged alternately. The first magnetic domains correspond to first data and... Agent: Harness, Dickey & Pierce, P.L.C

20090207644 - Memory cell architecture: Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic state; that is, restricting memory data storage to either logic “0” or “1.” The opposite logic state, “1” or “0,” can be available... Agent: Watchstone P+d, PLLC

20090207645 - Method and apparatus for accessing a bidirectional memory: A bidirectional memory cell includes an ovonic threshold switch (OTS) and a bidirectional memory element. The OTS is configured to select the bidirectional memory element and to prevent inadvertent accesses to the memory element.... Agent: Ovonyx, Inc

20090207646 - Integrated circuit with resistive memory cells and method for manufacturing same: An integrated circuit including a resistive memory cell and a method of manufacturing the integrated circuit are described. The integrated circuit comprises a plurality of resistive memory cells and a plurality of voltage supply contacts, wherein at least four resistive memory cells are in signal connection with one voltage supply... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090207647 - Nonvolatile semiconductor storage device and data writing method therefor: A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090207648 - Multi-level dynamic memory device: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that... Agent: Mills & Onello LLP

20090207649 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.... Agent: Dickstein Shapiro LLP

20090207650 - System and method for integrating dynamic leakage reduction with write-assisted sram architecture: A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write... Agent: Cantor Colburn LLP-ibm Burlington

20090207651 - Method for switching magnetic random access memory elements and magnetic element structures: A method for storing data in a magnetic memory element of an array of elements which avoids inadvertent switching of other elements is disclosed. First and second magnetic fields are applied to a selected magnetic element for a first time interval to switch the element into an intermediate state where... Agent: Ratnerprestia

20090207652 - Semiconductor device including resistance storage element: A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write... Agent: Mcdermott Will & Emery LLP

20090207653 - Memory storage device with heating element: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to... Agent: Ibm Corporation, T.j. Watson Research Center

20090207654 - Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same: Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality of parallel IO lines connecting the first element with the second element. The plurality of IO lines may have different lengths and... Agent: Harness, Dickey & Pierce, P.L.C

20090207659 - Memory device and memory data read method: Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error... Agent: Harness, Dickey & Pierce, P.L.C

20090207657 - Multi level inhibit scheme: Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the... Agent: Leffert Jay & Polglaze, P.A.

20090207656 - Operating method of memory: An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred... Agent: J C Patents, Inc.

20090207658 - Operating method of memory device: An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to... Agent: J C Patents, Inc.

20090207660 - Program method of flash memory device: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when... Agent: Marshall, Gerstein & Borun LLP

20090207661 - Segmented bitscan for verification of programming: A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether... Agent: Vierra Magen/sandisk Corporation

20090207655 - Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for a general purpose cmos technology with thick gate oxide: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The... Agent: Fogg & Powers LLC

20090207663 - Flash memory devices including ready/busy control circuits and methods of testing the same: A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal... Agent: Myers Bigel Sibley & Sajovec

20090207662 - Multi-transistor non-volatile memory element: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating... Agent: Haynes And Boone, LLPIPSection

20090207664 - Flash memory device for variably controlling program voltage and method of programming the same: Provided is a method of programming the flash memory device including setting increments of program voltages according to data states expressed as threshold voltage distributions of multi-level memory cells. An Increment Step Pulse Programming (ISPP) clock signal corresponds to a loop clock signal and the increments of the program voltages... Agent: F. Chau & Associates, LLC

20090207665 - Non-volatile one time programmable memory: A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20090207666 - Methods of restoring data in flash memory devices and related flash memory device memory systems: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit... Agent: Myers Bigel Sibley & Sajovec

20090207667 - Nand flash memory array with cut-off gate line and methods for operating and fabricating the same: A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line).... Agent: Casella & Hespos

20090207670 - Data output buffer whose mode switches according to operation frequency and semiconductor memory device having the same: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer... Agent: Volentine & Whitt PLLC

20090207668 - Data strobe clock buffer in semiconductor memory apparatus, method of controlling the same, and semiconductor apparatus having the same: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal... Agent: Baker & Mckenzie LLP Patent Department

20090207669 - Page buffer circuit of memory device and program method: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and... Agent: Townsend And Townsend And Crew, LLP

20090207671 - Memory data detecting apparatus and method for controlling reference voltage based on error in stored data: Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first... Agent: Harness, Dickey & Pierce, P.L.C

20090207673 - Semiconductor integrated circuit with multi test: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat... Agent: Baker & Mckenzie LLP Patent Department

20090207672 - Synchronous memory devices and control methods for performing burst write operations: Synchronous memory devices and control methods for performing burst write operations are disclosed. In one embodiment, a synchronous memory device for controlling a burst write operation comprises a first buffer circuit for buffering a first control signal requesting an exit from the burst write operation in synchronization with a clock... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090207674 - Device and method generating internal voltage in semiconductor memory device: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command... Agent: Volentine & Whitt PLLC

20090207675 - Wak devices in sram cells for improving vccmin: A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node... Agent: Slater & Matsil, L.L.P.

20090207676 - Semiconductor memory device having reduced current consumption during data mask function: The present invention describes a semiconductor memory device having a data mask function and includes a common driving control unit for generating a common driving control signal in response to a data mask signal and a write command signal supplied to the common driving control unit. A plurality of driving... Agent: Ladas & Parry LLP

20090207677 - Semiconductor device utilizing data mask and data outputting method using the same: A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop (DLL) clock... Agent: Ladas & Parry LLP

20090207678 - Memory writing interference test system and method thereof: The present invention is a memory writing interference test system and method thereof. The test system comprises a memory, a progressing unit, a write-in unit, a read-out unit, and a discriminating unit. By sequentially writing data and then reading out the written data from one memory block after one through... Agent: Chih Feng Yeh Brian M. Mcinnis

20090207679 - Systems and methods for data transfers between memory cells: Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier... Agent: Law Offices Of Mark L. Berrier

20090207680 - Method for the allocation of addresses in the memory cells of a rechargeable energy accumulator: A method for placing addresses in the memory cells of a rechargeable energy storage device for use in a motor vehicle, each of which memory cells includes at least one sensor device and an individualizing device for storing an address. In order to optimize the placing of addresses in the... Agent: Crowell & Moring LLP Intellectual Property Group

20090207682 - Semiconductor memory device: A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes... Agent: Arent Fox LLP

20090207681 - Systems and devices including local data lines and methods of using, making, and operating the same: Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portion of a capacitor plate connected to the... Agent: Fletcher Yoder (micron Technology, Inc.)

20090207683 - Input circuit of semiconductor memory apparatus and controlling method thereof: Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area... Agent: Baker & Mckenzie LLP Patent Department

  
08/13/2009 > patent applications in patent subcategories. inventions list

20090201709 - Content addressable memory: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and... Agent: Miles & Stockbridge PC

20090201711 - Memory module with a circuit providing load isolation and memory domain translation: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one... Agent: Knobbe Martens Olson & Bear LLP

20090201710 - Semiconductor memory device: A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201712 - Presetable ram: A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided... Agent: Townsend And Townsend And Crew, LLP

20090201713 - Unit cell of nonvolatile memory device and nonvolatile memory device having the same: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write... Agent: Morgan Lewis & Bockius LLP

20090201715 - Carbon diode array for resistivity changing memories: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell including a resistivity changing memory element and a carbon diode electrically coupled to the resistivity changing memory element.... Agent: Slater & Matsil, L.L.P.

20090201716 - Memory element with positive temperature coefficient layer: An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the... Agent: Slater & Matsil, L.L.P.

20090201717 - Resistance-change memory: A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines,... Agent: Knobbe Martens Olson & Bear LLP

20090201714 - Resistive memory cell and method for operating same: An integrated circuit comprising at least one resistive memory cell, comprising a resistive memory element and a selection device, said resistive memory element having at least two resistive OFF-states, each OFF-state defining a predefined resistance value is described. Moreover, a memory, a computing system and method of operating a memory... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090201718 - Dram including a tunable gain amp as a local sense amp: DRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a capacitor, and gain of the tunable gain amp is adjusted by setting a local amp... Agent: Juhan Kim

20090201719 - Method and system for semiconductor memory: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port.... Agent: SprinkleIPLaw Group

20090201720 - Multibit magnetic random access memory device: A multi-bit magnetic random access memory device and a method for writing to and sensing the multi-bit magnetic random access memory device. The magnetic memory includes a memory cell with a multilayer structure having a plurality of data layers which can each store one bit. The structure includes a plurality... Agent: Sughrue Mion, PLLC

20090201721 - Phase change memory device and write method thereof: A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and... Agent: Lee & Morse, P.C.

20090201722 - Method including magnetic domain patterning using plasma ion implantation for mram fabrication: A method for defining magnetic domains in a magnetic thin film on a substrate, includes: coating the magnetic thin film with a resist; patterning the resist, wherein areas of the magnetic thin film are substantially uncovered; and exposing the magnetic thin film to a plasma, wherein plasma ions penetrate the... Agent: Applied Materials C/o Pillsbury Winthrop Shaw Pittman LLP

20090201723 - Single transistor memory cell: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored... Agent: Courtney Staniford & Gregory LLP

20090201728 - Erase method of flash memory device: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when... Agent: Marshall, Gerstein & Borun LLP

20090201725 - Multi-level memory cell programming methods: A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090201726 - Non-volatile semiconductor storage system: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201727 - Read method of memory device: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read... Agent: Townsend And Townsend And Crew, LLP

20090201729 - Memory device and memory device heat treatment method: A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the... Agent: Harness, Dickey & Pierce, P.L.C

20090201730 - Method and apparatus of operating a non-volatile dram: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is... Agent: Saile Ackerman LLC

20090201731 - Method and apparatus for accessing memory with read error by changing comparison: In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090201732 - System and method for purging a flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects... Agent: Stec, Inc. C/oIPLaw Dept.

20090201733 - Flash memory device: A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and... Agent: Myers Bigel Sibley & Sajovec

20090201734 - Verified purge for flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers... Agent: Stec, Inc. C/oIPLaw Dept.

20090201736 - Increased nand flash memory read throughput: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data... Agent: Schwegman, Lundberg & Woessner/micron

20090201735 - Non-volatile memory apparatus for controlling page buffer and controlling method thereof: A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages... Agent: Baker & Mckenzie LLP Patent Department

20090201737 - Nonvolatile semiconductor memory device: A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second... Agent: Turocy & Watson, LLP

20090201738 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201740 - Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module: An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell,... Agent: Viering, Jentschura & Partner

20090201739 - Method for driving semiconductor device, and semiconductor device: In a case of writing to a trap type non-volatile memory cell that includes: a laminated insulating film, containing a charge accumulation layer, that is formed on a semiconductor substrate where source, drain and well regions are formed; and a first gate electrode formed on the laminated insulating film, charge... Agent: Young & Thompson

20090201741 - Non-volatile memory cell with injector: In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090201724 - Memory device and method thereof: A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at... Agent: Larson Newman Abel & Polansky, LLP

20090201742 - Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form... Agent: Saile Ackerman LLC

20090201743 - Multiwalled carbon nanotube memory device: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made... Agent: Scully, Scott, Murphy & Presser, P.C.

20090201744 - Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a... Agent: Dla Piper LLP (us )

20090201746 - Parallel-to-serial data sort device: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and... Agent: Fletcher Yoder (micron Technology, Inc.)

20090201745 - Semiconductor memory device: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to... Agent: Mcdermott Will & Emery LLP

20090201747 - Memory, bit-line pre-charge circuit and bit-line pre-charge method: A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The... Agent: Volpe And Koenig, P.C.

20090201748 - Removable nonvolatile memory system with destructive read: A removable nonvolatile memory system is provided including storing read data onto a memory portion of a memory device; and accessing the memory portion including reading the read data from the memory portion, and writing predetermined data onto the memory portion after reading the memory portion.... Agent: Law Offices Of Mikio Ishimaru

20090201749 - Semiconductor storage device and method for operating the same: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a... Agent: Myers Bigel Sibley & Sajovec

20090201750 - Semiconductor integrated circuit and method of measuring a maximum delay: A semiconductor integrated circuit includes a memory, a master interface circuit that performs one of receiving a data transfer request from the memory and outputting a data transfer request to the memory, a slave interface circuit that performs one of receiving data from the memory and outputting data to the... Agent: Sughrue Mion, PLLC

20090201751 - Semiconductor device in which a memory array is refreshed based on an address signal: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM... Agent: Sughrue Mion, PLLC

20090201754 - Semiconductor device having transmission control circuit: A semiconductor device has a transmission control circuit comprising a signal transmission circuit, an output control circuit, a replica circuit and a detection circuit. The single transmission circuit receives a predetermined signal in synchronization with a first control signal, and transmits and outputs the signal through a signal bus in... Agent: Sughrue Mion, PLLC

20090201752 - Semiconductor memory device: There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines... Agent: Foley And Lardner LLP Suite 500

20090201753 - Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the... Agent: Foley And Lardner LLP Suite 500

20090201755 - Maintenance of amplified signals using high-voltage-threshold transistors: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the... Agent: Leffert Jay & Polglaze, P.A.

20090201756 - Method and circuit for implementing enhanced efuse sense circuit: A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090201757 - Semiconductor device: Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.... Agent: Sughrue Mion, PLLC

20090201758 - Method for designing integrated circuit incorporating memory macro: An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes: assigning a plurality of memory instances operating at the same operation frequency to a single memory macro; arranging a frequency multiplier which receives... Agent: Mcginn Intellectual Property Law Group, PLLC

  
08/13/2009 > patent applications in patent subcategories. inventions list

20090201709 - Content addressable memory: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and... Agent: Miles & Stockbridge PC

20090201711 - Memory module with a circuit providing load isolation and memory domain translation: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one... Agent: Knobbe Martens Olson & Bear LLP

20090201710 - Semiconductor memory device: A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201712 - Presetable ram: A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided... Agent: Townsend And Townsend And Crew, LLP

20090201713 - Unit cell of nonvolatile memory device and nonvolatile memory device having the same: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write... Agent: Morgan Lewis & Bockius LLP

20090201715 - Carbon diode array for resistivity changing memories: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell including a resistivity changing memory element and a carbon diode electrically coupled to the resistivity changing memory element.... Agent: Slater & Matsil, L.L.P.

20090201716 - Memory element with positive temperature coefficient layer: An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the... Agent: Slater & Matsil, L.L.P.

20090201717 - Resistance-change memory: A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines,... Agent: Knobbe Martens Olson & Bear LLP

20090201714 - Resistive memory cell and method for operating same: An integrated circuit comprising at least one resistive memory cell, comprising a resistive memory element and a selection device, said resistive memory element having at least two resistive OFF-states, each OFF-state defining a predefined resistance value is described. Moreover, a memory, a computing system and method of operating a memory... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090201718 - Dram including a tunable gain amp as a local sense amp: DRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a capacitor, and gain of the tunable gain amp is adjusted by setting a local amp... Agent: Juhan Kim

20090201719 - Method and system for semiconductor memory: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port.... Agent: SprinkleIPLaw Group

20090201720 - Multibit magnetic random access memory device: A multi-bit magnetic random access memory device and a method for writing to and sensing the multi-bit magnetic random access memory device. The magnetic memory includes a memory cell with a multilayer structure having a plurality of data layers which can each store one bit. The structure includes a plurality... Agent: Sughrue Mion, PLLC

20090201721 - Phase change memory device and write method thereof: A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and... Agent: Lee & Morse, P.C.

20090201722 - Method including magnetic domain patterning using plasma ion implantation for mram fabrication: A method for defining magnetic domains in a magnetic thin film on a substrate, includes: coating the magnetic thin film with a resist; patterning the resist, wherein areas of the magnetic thin film are substantially uncovered; and exposing the magnetic thin film to a plasma, wherein plasma ions penetrate the... Agent: Applied Materials C/o Pillsbury Winthrop Shaw Pittman LLP

20090201723 - Single transistor memory cell: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored... Agent: Courtney Staniford & Gregory LLP

20090201728 - Erase method of flash memory device: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when... Agent: Marshall, Gerstein & Borun LLP

20090201725 - Multi-level memory cell programming methods: A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090201726 - Non-volatile semiconductor storage system: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201727 - Read method of memory device: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read... Agent: Townsend And Townsend And Crew, LLP

20090201729 - Memory device and memory device heat treatment method: A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the... Agent: Harness, Dickey & Pierce, P.L.C

20090201730 - Method and apparatus of operating a non-volatile dram: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is... Agent: Saile Ackerman LLC

20090201731 - Method and apparatus for accessing memory with read error by changing comparison: In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090201732 - System and method for purging a flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects... Agent: Stec, Inc. C/oIPLaw Dept.

20090201733 - Flash memory device: A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and... Agent: Myers Bigel Sibley & Sajovec

20090201734 - Verified purge for flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers... Agent: Stec, Inc. C/oIPLaw Dept.

20090201736 - Increased nand flash memory read throughput: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data... Agent: Schwegman, Lundberg & Woessner/micron

20090201735 - Non-volatile memory apparatus for controlling page buffer and controlling method thereof: A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages... Agent: Baker & Mckenzie LLP Patent Department

20090201737 - Nonvolatile semiconductor memory device: A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second... Agent: Turocy & Watson, LLP

20090201738 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090201740 - Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module: An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell,... Agent: Viering, Jentschura & Partner

20090201739 - Method for driving semiconductor device, and semiconductor device: In a case of writing to a trap type non-volatile memory cell that includes: a laminated insulating film, containing a charge accumulation layer, that is formed on a semiconductor substrate where source, drain and well regions are formed; and a first gate electrode formed on the laminated insulating film, charge... Agent: Young & Thompson

20090201741 - Non-volatile memory cell with injector: In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090201724 - Memory device and method thereof: A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at... Agent: Larson Newman Abel & Polansky, LLP

20090201742 - Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device: A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form... Agent: Saile Ackerman LLC

20090201743 - Multiwalled carbon nanotube memory device: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made... Agent: Scully, Scott, Murphy & Presser, P.C.

20090201744 - Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a... Agent: Dla Piper LLP (us )

20090201746 - Parallel-to-serial data sort device: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and... Agent: Fletcher Yoder (micron Technology, Inc.)

20090201745 - Semiconductor memory device: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to... Agent: Mcdermott Will & Emery LLP

20090201747 - Memory, bit-line pre-charge circuit and bit-line pre-charge method: A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The... Agent: Volpe And Koenig, P.C.

20090201748 - Removable nonvolatile memory system with destructive read: A removable nonvolatile memory system is provided including storing read data onto a memory portion of a memory device; and accessing the memory portion including reading the read data from the memory portion, and writing predetermined data onto the memory portion after reading the memory portion.... Agent: Law Offices Of Mikio Ishimaru

20090201749 - Semiconductor storage device and method for operating the same: A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a... Agent: Myers Bigel Sibley & Sajovec

20090201750 - Semiconductor integrated circuit and method of measuring a maximum delay: A semiconductor integrated circuit includes a memory, a master interface circuit that performs one of receiving a data transfer request from the memory and outputting a data transfer request to the memory, a slave interface circuit that performs one of receiving data from the memory and outputting data to the... Agent: Sughrue Mion, PLLC

20090201751 - Semiconductor device in which a memory array is refreshed based on an address signal: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM... Agent: Sughrue Mion, PLLC

20090201754 - Semiconductor device having transmission control circuit: A semiconductor device has a transmission control circuit comprising a signal transmission circuit, an output control circuit, a replica circuit and a detection circuit. The single transmission circuit receives a predetermined signal in synchronization with a first control signal, and transmits and outputs the signal through a signal bus in... Agent: Sughrue Mion, PLLC

20090201752 - Semiconductor memory device: There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines... Agent: Foley And Lardner LLP Suite 500

20090201753 - Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the... Agent: Foley And Lardner LLP Suite 500

20090201755 - Maintenance of amplified signals using high-voltage-threshold transistors: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the... Agent: Leffert Jay & Polglaze, P.A.

20090201756 - Method and circuit for implementing enhanced efuse sense circuit: A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090201757 - Semiconductor device: Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.... Agent: Sughrue Mion, PLLC

20090201758 - Method for designing integrated circuit incorporating memory macro: An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes: assigning a plurality of memory instances operating at the same operation frequency to a single memory macro; arranging a frequency multiplier which receives... Agent: Mcginn Intellectual Property Law Group, PLLC

  
08/06/2009 > patent applications in patent subcategories. inventions list

20090196083 - Integrated circuits to control access to multiple layers of memory: Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include... Agent: Unity Semiconductor Corporation

20090196084 - Memory chip array: Provided is a memory chip array comprising a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip array and is minimized in area.... Agent: Harness, Dickey & Pierce, P.L.C

20090196085 - Sram memory cell protected against current or voltage spikes: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090196086 - High bandwidth cache-to-processing unit communication in a multiple processor/cache system: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die... Agent: Freescale Semiconductor, Inc. Law Department

20090196087 - Non-volatile register: A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element.... Agent: Unity Semiconductor Corporation

20090196089 - Phase change material, phase change memory device including the same, and methods of manufacturing and operating the phase change memory device: Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si—O—Sb alloy further including O. The Si—O—Sb alloy... Agent: Harness, Dickey & Pierce, P.L.C

20090196088 - Resistance control in conductive bridging memories: An integrated circuit may comprise one or more resistive storage cells, wherein each resistive storage cell comprises a resistive storage medium that is switchable between at least a high resistive state and a low resistive state; and a resistance element communicatively coupled to the resistive storage medium in series.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090196090 - Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers: Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits... Agent: Hewlett Packard Company

20090196094 - Integrated circuit including electrode having recessed portion: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.... Agent: Dicke, Billig & Czaja

20090196096 - Memory cells, methods of forming memory cells, and methods of forming programmed memory cells: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change... Agent: Wells St. John P.s.

20090196095 - Multiple memory cells and method: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor.... Agent: Schwegman, Lundberg & Woessner/micron

20090196092 - Programming bit alterable memories: Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the... Agent: Trop, Pruner & Hu, P.C.

20090196091 - Self-aligned phase change memory: A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and... Agent: Trop, Pruner & Hu, P.C.

20090196093 - Stacked die memory: A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second... Agent: Dicke, Billig & Czaja

20090196097 - Device for reading memory data and method using the same: Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line... Agent: Harness, Dickey & Pierce, P.L.C

20090196098 - Multiple-level memory with analog read: A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers,... Agent: Ryan, Mason & Lewis, LLP

20090196099 - Page buffer circuit of memory device and program method: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and... Agent: Townsend And Townsend And Crew, LLP

20090196100 - Systems and methods for reducing unauthorized data recovery from solid-state storage devices: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices... Agent: Knobbe Martens Olson & Bear LLP

20090196101 - Memory module: The present invention provides a reliable memory module. The memory module including a plurality of memory devices arranged on a circuit board and controlled by an external memory controller includes a buffer having a function of detecting and correcting an error and a nonvolatile storage area that stores contents of... Agent: Young & Thompson

20090196102 - Flexible memory operations in nand flash devices: A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090196103 - Non-volatile memory device having configurable page size: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090196104 - Memory and method operating the memory: A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, and a capacitor. The first transistor has... Agent: Bacon & Thomas, PLLC

20090196106 - Mem suspended gate non-volatile memory: A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20090196105 - Scalable electrically eraseable and programmable memory (eeprom) cell array: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20090196107 - Semiconductor device and its memory system: A semiconductor device selects one mask pattern among from a plurality of the mask patterns, which are stored in a mask resister circuit for mask controlling of a bit width (vertical axis), by a mask pattern selection signal, and controls input and output of data based on the selected mask... Agent: Sughrue Mion, PLLC

20090196108 - Semiconductor memory device and semiconductor memory device test method: A semiconductor memory device having a first memory block used when it is determined to be used in a first case, a second memory block used as an alternative of the first memory blocks when it is determined to be used in a second case, a write section that writes... Agent: Staas & Halsey LLP

20090196109 - Rank select using a global select pin: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in... Agent: Fletcher Yoder (micron Technology, Inc.)

20090196110 - Integrated circuit, and method for transferring data: An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based... Agent: Dicke, Billig & Czaja

20090196111 - Page buffer circuit of memory device and program method: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and... Agent: Townsend And Townsend And Crew, LLP

20090196112 - Block decoding circuits of semiconductor memory devices and methods of operating the same: A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The... Agent: Harness, Dickey & Pierce, P.L.C

20090196113 - Fuse circuit and semiconductor memory device including the same: The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing... Agent: Lee & Morse, P.C.

20090196114 - Semiconductor storage device: A semiconductor storage device includes: a plurality of I/O terminals configured in a block, and including a representative I/O terminal and a non-representative I/O terminal; a plurality of memory cells each associated with the plurality of I/O terminals to store data; a data input portion to which data to be... Agent: Mcginn Intellectual Property Law Group, PLLC

20090196115 - Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power... Agent: Mcdermott Will & Emery LLP

20090196116 - Semiconductor memory having a bank with sub-banks: Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090196117 - System and method for memory array decoding: A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M... Agent: Harness, Dickey & Pierce P.L.C

20090196118 - Design structure of implementing power savings during addressing of dram architectures: A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of... Agent: Cantor Colburn LLP - IBM Rochester Division

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