|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
07/2009 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval July category listing 07/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/30/2009 > patent applications in patent subcategories. category listing
20090190386 - Hybrid content addressable memory: A CAM device memory array having different types of memory cells is disclosed. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090190385 - Sram including reduced swing amplifiers: SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense amp for reading the local sense amp, and a third reduced... Agent: Juhan Kim
20090190387 - Semiconductor device: A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over... Agent: Harness, Dickey & Pierce, P.L.C
20090190388 - Resistive memory and methods for forming same: A method of fabricating a resistive storage device is provided. The method generally comprises providing an electrode structure stack comprising a first electrode and an electrode structure mask arranged at the first electrode, forming a support structure at least partly at the electrode structure mask, removing the electrode structure mask... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090190389 - Multi-port sram with six-transistor memory cells: In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from... Agent: Haynes And Boone, LLPIPSection
20090190390 - Integrated circuits, cell, cell arrangement, method of reading a cell, memory module: An embodiment of the invention provides an integrated circuit having a cell. The cell includes a first magnetic layer structure having a first magnetization along a first axis, a non-magnetic spacer layer structure disposed above the first magnetic layer structure, and a second magnetic layer structure disposed above the non-magnetic... Agent: Slater & Matsil, L.L.P.
20090190391 - Magnetoresistive random access memory: A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090190392 - Electronic device, method of manufacturing the same, and storage device: An electronic device includes: a first conductor; an insulative supporting film formed in a part on one surface of the first conductor; and a second conductor, one surface of which is opposed to the one surface of the first conductor and a part of which is supported by the supporting... Agent: K&l Gates LLP
20090190393 - Phase change memory device with dummy cell array: A phase change memory device includes a cell array having a phase change resistance cell arranged at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a first bit line discharge signal. A column switching unit... Agent: Ladas & Parry LLP
20090190394 - Capacitorless dram on bulk silicon: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A... Agent: Knobbe Martens Olson & Bear LLP
20090190397 - Memory device and data reading method: A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first... Agent: Harness, Dickey & Pierce, P.L.C
20090190396 - Memory device and method of reading memory data: A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide... Agent: Harness, Dickey & Pierce, P.L.C
20090190398 - Method of programming data in a nand flash memory device and method of reading data in the nand flash memory device: A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit... Agent: Lee & Morse, P.C.
20090190400 - Non-volatile memory device with both single and multiple level cells: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090190399 - Semiconductor memory device capable of correcting a read level properly: In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090190401 - Memory device employing nvram and flash memory cells: A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM... Agent: Myers Bigel Sibley & Sajovec
20090190402 - Integrated sram and flotox eeprom memory device: A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a... Agent: Saile Ackerman LLC
20090190403 - Flash memory devices and erasing methods thereof: Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-programming includes first post-programming the memory block... Agent: Myers Bigel Sibley & Sajovec
20090190404 - Nand flash content addressable memory: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20090190405 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090190406 - Random telegraph signal noise reduction scheme for semiconductor memories: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on... Agent: Fletcher Yoder (micron Technology, Inc.)
20090190395 - Nonvolatile semiconductor memory device: Provided is a nonvolatile semiconductor memory device which can enhance a stable control of a voltage applied to a memory cell and has excellent capability of controlling a drain voltage. The nonvolatile semiconductor memory device includes: a plurality of memory cells; a write buffer receiving data to be written to... Agent: Myers Bigel Sibley & Sajovec
20090190407 - Semiconductor memory device: Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When... Agent: Brinks Hofer Gilson & Lione/seiko Instruments Inc.
20090190408 - Method of operating an integrated circuit, integrated circuit and method to determine an operating point: Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to... Agent: Slater & Matsil, L.L.P.
20090190409 - Integrated circuit, cell arrangement, method for operating an integrated circuit and for operating a cell arrangement, memory module: An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one monitoring memory cell and at least one memory cell, wherein the at least one monitoring memory cell has a shorter retention time than the at least one memory cell. The cell arrangement further includes... Agent: Slater & Matsil, L.L.P.
20090190410 - Using differential data strobes in non-differential mode to enhance data capture window: A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself,... Agent: Hogan & Hartson LLP
20090190412 - Nonvolatile memory device with load-free wired-or structure and an associated driving method: A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an... Agent: Marger Johnson & Mccollom, P.C.
20090190411 - Semiconductor memory device and control method: A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on... Agent: Mcginn Intellectual Property Law Group, PLLC
20090190413 - Self-repair integrated circuit and repair method: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region.... Agent: Keusey, Tutunjian & Bitetto, P.C.
20090190414 - Semiconductor device: A semiconductor device includes a mode register and a plurality of voltage generators in connection with a plurality of banks. Based on an operation mode set to the mode register, the voltage generators are selectively driven in response to an access to each bank and a CAS latency number defining... Agent: Mcdermott Will & Emery LLP
20090190415 - Read-write circuit for short bit line dram: A read-write circuit serving as a global sense amp for SBL (short bit line) DRAM is realized, wherein the read-write circuit includes a common line, such that the common line is used for connecting a read circuit, a latch circuit, a write circuit, a left select circuit and a right... Agent: Juhan Kim
20090190416 - Semiconductor storage device and method for producing semiconductor storage device: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The... Agent: Arent Fox LLP
20090190417 - Semiconductor integrated circuit device and method of testing same: A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and... Agent: Young & Thompson
20090190419 - Circuit and method for controlling sense amplifier of semiconductor memory apparatus: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense... Agent: Venable LLP
20090190420 - Delay locked loop with frequency control: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of... Agent: Schwegman, Lundberg & Woessner/micron
20090190418 - Semiconductor memory, method of controlling the semiconductor memory, and memory system: A semiconductor memory comprising an address transition detection circuit for detecting a transition of an address and outputs an address detection signal; an address input circuit for inputting an input address based upon the address detection signal; a command judgment circuit for decoding a command signal input and outputting a... Agent: Arent Fox LLP
20090190421 - Semiconductor memory device and semiconductor memory system for compensating crosstalk: A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk compensator. The crosstalk compensator may be connected between the channels to compensate for crosstalk. The crosstalk compensator may comprise a capacitor connected... Agent: Marger Johnson & Mccollom, P.C.
20090190422 - Electronic fuses: The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data received from said fusebox; a data communication path linking said fusebox... Agent: Nixon & Vanderhye, PC
20090190423 - Semiconductor memory and manufacturing method thereof: A semiconductor memory is provided which performs redundancy on a memory cell by a given bit unit, the semiconductor memory includes: a comparator circuit that compares an input address and a redundancy address; a judgment circuit that judges whether to perform the redundancy based on a compared result, wherein the... Agent: Fujitsu Patent Center C/o Cpa Global
20090190424 - Semiconductor circuit: Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharge control signal, and NMOS transistors and PMOS transistors to precharge... Agent: Sherr & Vaughn, PLLC
20090190425 - Sense amplifier read line sharing: A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier... Agent: Haynes And Boone, LLPIPSection
20090190426 - Circuits, methods and design structures for adaptive repair of sram arrays: The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability... Agent: Ryan, Mason & Lewis, LLP
20090190427 - System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller: A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a first set of thermal sensors... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090190428 - Nonvolatile semiconductor memory device: In a semiconductor device equipped with a nonvolatile memory, using a simple configuration, a write operation and the like are reliably made feasible even when stability of power supply from an external component is inhibited. The semiconductor device includes a nonvolatile memory core including a nonvolatile memory and a switch... Agent: Mcdermott Will & Emery LLP
20090190429 - System to provide memory system power reduction without reducing overall memory system performance: A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20090190431 - Double data rate-single data rate input block and method for using same: A disclosed embodiment is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data... Agent: Farjami & Farjami LLP
20090190430 - Non-volatile latch circuit for restoring data after power interruption: A nonvolatile latch circuit that exhibits improved the performance of a system is presented. The nonvolatile latch circuit is capable of storing all kinds of the states generated during the operation of the system as non-volatility information. The nonvolatile latch circuit is capable of restoring the previous state where of... Agent: Ladas & Parry LLP
20090190432 - Dram with page access: A DRAM chip with a data I/O-interface of an access width equal to a page size.... Agent: Slater & Matsil, L.L.P.07/23/2009 > patent applications in patent subcategories. category listing
20090185407 - Semiconductor memory device having transistors of stacked structure: Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines,... Agent: Myers Bigel Sibley & Sajovec
20090185408 - Memory device, memory system and method for design of memory device: A memory device may include, but is not limited to, at least one memory module, and a plurality of lumped constant circuit elements. The at least one memory module is electrically coupled to a transmission system that has a characteristic impedance. The plurality of lumped constant circuit elements with an... Agent: Sughrue Mion, PLLC
20090185409 - Enhanced static random access memory stability using asymmetric access transistors and design structure for same: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell... Agent: Ryan, Mason & Lewis, LLP
20090185410 - Method and system for providing spin transfer tunneling magnetic memories utilizing unidirectional polarity selection devices: A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are... Agent: Strategic Patent Group, P.C.
20090185411 - Integrated circuit including diode memory cells: The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.... Agent: Dicke, Billig & Czaja
20090185412 - Phase-change material, memory unit and method for electrically storing/reading data: A phase-change material and a memory unit using the phase-change material are provided. The phase-change material is in a single crystalline state and includes a compound of a metal oxide or nitroxide, wherein the metal is at least one selected from a group consisting of indium, gallium and germanium. The... Agent: Law Offices Of Mikio Ishimaru
20090185413 - Semiconductor device having input circuit with output path control unit: A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering... Agent: Ladas & Parry LLP
20090185417 - Apparatus and method of memory programming: A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to... Agent: Harness, Dickey & Pierce, P.L.C
20090185415 - Cell operation monitoring: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
20090185418 - Flash memory device configured to switch wordline and initialization voltages: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the... Agent: Volentine & Whitt PLLC
20090185419 - Page buffer circuit with reduced size and methods for reading and programming data with the same: A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the... Agent: Townsend And Townsend And Crew, LLP
20090185420 - Page buffer circuit with reduced size and methods for reading and programming data with the same: A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the... Agent: Townsend And Townsend And Crew, LLP
20090185416 - System that compensates for coupling based on sensing a neighbor using coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation
20090185421 - Charge-trap flash memory device with reduced erasure stress and related programming and erasing methods thereof: Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap... Agent: Myers Bigel Sibley & Sajovec
20090185422 - Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the... Agent: Lee & Morse, P.C.
20090185424 - Decoding control with address transition detection in page erase function: Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event... Agent: Smart & Biggar P.o. Box 2999, Station D
20090185423 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090185425 - Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement... Agent: Slater & Matsil, L.L.P.
20090185427 - Semiconductor memory device and driving method for the same: The semiconductor memory device includes: a first well of a first conductivity type, a second well of the first conductivity type and a third well of a second conductivity type formed in a substrate: a diffusion bit line extending in a row direction and a word line extending in a... Agent: Mcdermott Will & Emery LLP
20090185426 - Semiconductor memory device and method of forming the same: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be... Agent: Birch Stewart Kolasch & Birch
20090185414 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090185428 - Operating method of multi-level memory cell: An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage... Agent: J C Patents, Inc.
20090185429 - Non-volatile memory with single floating gate and method for operating the same: A non-volatile memory with single floating gate and the method for operating the same are proposed. The non-volatile memory is formed by embedding a FET structure in a semiconductor substrate. The FET comprises a single floating gate, a dielectric, and two ion-doped regions in the semiconductor at two sides of... Agent: Rosenberg, Klein & Lee
20090185430 - Memory sensing and latching circuit: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a... Agent: Farjami & Farjami LLP
20090185431 - Semiconductor device: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as... Agent: Mcdermott Will & Emery LLP
20090185432 - Semiconductor memory device: A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detector configured to detect a voltage level of internal voltage terminals... Agent: Mannava & Kang, P.C.
20090185433 - Semiconductor device: A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting... Agent: Marshall, Gerstein & Borun LLP
20090185434 - Operational mode control in serial-connected memory based on identifier: Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be... Agent: Ridout & Maybee LLP
20090185435 - Method and circuit for implementing enhanced sram write and read performance ring oscillator: A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base... Agent: Ibm Corporation RochesterIPLaw Dept 917
20090185436 - Semiconductor integrated circuit having write controlling circuit: A semiconductor integrated circuit includes a write controlling circuit configured to selectively provide a fixed pulse or a variable pulse according to a level of a test mode signal in a write operation mode, thereby adjusting a pulse width of an internal write pulse that is a current pulse driving... Agent: Baker & Mckenzie LLP Patent Department
20090185437 - Clock-based data storage device, dual pulse generation device, and data storage device: Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090185439 - Architecture of highly integrated semiconductor memory device: A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit... Agent: Mannava & Kang, P.C.
20090185438 - Semiconductor memory device having redundancy circuit for repairing defective unit cell, and method for repairing defective unit cell: A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input.... Agent: Mannava & Kang, P.C.
20090185440 - Active cycyle control circuit for semiconductor memory apparatus: An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle.... Agent: Venable LLP
20090185441 - Integrated circuit and method to operate an integrated circuit: Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.... Agent: Slater & Matsil, L.L.P.
20090185442 - Memory system and method with serial and parallel modes: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a... Agent: Smart & Biggar P.o. Box 2999, Station D07/16/2009 > patent applications in patent subcategories. category listing
20090180306 - Semiconductor memory device: A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same... Agent: Mcdermott Will & Emery LLP
20090180307 - Program lock circuit for a mask programmable anti-fuse memory array: A program lock circuit for inhibiting programming of memory cells. A memory array can have both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. Since the one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090180308 - Method of using spin injection device: A spin injection device capable of spin injection magnetization reversal at low current density, a magnetic apparatus using the same, and magnetic thin film using the same, whereby the spin injection device (14) including a spin injection part (1) comprising a spin polarization part (9) including a ferromagnetic fixed layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090180309 - Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively... Agent: Wells St. John P.s.
20090180310 - Resistance change type memory: A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090180311 - Core-rotating element of ferromagnetic dot and information memory element using the core of ferromagnetic dot: The present invention provides a novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape. In addition, the present invention is achieved... Agent: Oliff & Berridge, PLC
20090180312 - Unidirectional-current magnetization-reversal magnetoresistance element and magnetic recording apparatus: A memory for which writing is conducted by using a unidirectional write current. Currents which differ in current pulse width are applied to a magnetoresistance element in a film thickness direction of the magnetoresistance element consisting of a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090180313 - Chalcogenide anti-fuse: An ovonic threshold switch may be used to form an anti-fuse. As manufactured, the fuse may be in its amorphous state, as is conventional for ovonic threshold switches. However, when exposed to a sufficient voltage under appropriate circumstances, the anti-fuse may fuse in a more conductive state. As fused, the... Agent: Trop, Pruner & Hu, P.C.
20090180314 - Multi-level programmable pcram memory: A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to provide a memory device having three or more discrete resistance levels, and thus three or more discrete logic levels. The non-volatile memory device may be formed... Agent: Schwegman, Lundberg & Woessner/micron
20090180315 - System and method of selectively applying negative voltage to wordlines during memory device read operation: Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device includes a word line logic circuit coupled to a plurality of word lines and adapted to selectively apply a positive voltage to a selected word line... Agent: Qualcomm Incorporated
20090180316 - System and devices including memory resistant to program disturb and methods of using, making, and operating the same: Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has... Agent: Fletcher Yoder (micron Technology, Inc.)
20090180318 - Method for controlling semiconductor storage device comprising memory cells each configured to hold multi-bit data, and memory card provided with semiconductor storage device: A method for controlling a semiconductor storage device including memory cells each configured to hold data of 2 bits or more, the method includes starting first signal processing, and inputting lower bits into the semiconductor storage device in a ready state, writing the lower bits to the memory cells, changing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090180319 - Non-volatile semiconductor memory device and memory system including the same: Provided is a non-volatile semiconductor device. The non-volatile semiconductor memory devices including: first and second word line groups disposed in parallel; dummy word lines disposed between the first and second word line groups; a first bit line group intersecting the first word line group; and a second bit line group... Agent: Volentine & Whitt PLLC
20090180320 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines;... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090180321 - Nonvolatile semiconductor memory device, and reading method, writing method and erasing method of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090180322 - Nand string with a redundant memory cell: The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled non-volatile memory cells to a source line, a drain select line for selectively coupling one or more strings of series-coupled non-volatile memory cells to one or... Agent: Leffert Jay & Polglaze, P.A.
20090180323 - Nonvolatile memory device, program method thereof, and memory system including the same: A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit... Agent: Lee & Morse, P.C.
20090180325 - Partitioned erase and erase verification in non-volatile memory: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of... Agent: Vierra Magen/sandisk Corporation
20090180324 - Semiconductor constructions, nand unit cells, methods of forming semiconductor constructions, and methods of forming nand unit cells: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage... Agent: Wells St. John P.s.
20090180328 - Method for accessing in reading, writing and programming to a nand non-volatile memory electronic device monolithically integrated on semiconductor: A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address... Agent: Trop, Pruner & Hu, P.C.
20090180326 - Non-volatile memory and semiconductor device: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge... Agent: Cook Alex Ltd
20090180327 - Non-volatile semiconductor storage device: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object... Agent: Volentine & Whitt PLLC
20090180317 - Flash memory device including a dummy cell: A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy cell is turned off during a programming... Agent: Volentine & Whitt PLLC
20090180329 - Program method of nonvolatile memory device: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache... Agent: Rabin & Berdo, PC
20090180330 - Non-volatile memory device and methods of using: The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.... Agent: Larson Newman Abel & Polansky, LLP
20090180331 - Semiconductor memory device having bit line pre-charge unit separated from data register: A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090180332 - Operation method of nitride-based flash memory and method of reducing coupling interference: A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory... Agent: J C Patents, Inc.
20090180334 - Non-volatile memory with reduced charge fluence: A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit... Agent: Freescale Semiconductor, Inc. Law Department
20090180333 - Semiconductor memory column decoder device and method: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090180335 - Integrated circuit with reduced pointer uncertainly: One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a selected clock from multiple clocks based on the sample. The second circuit is configured to provide... Agent: Dicke, Billig & Czaja
20090180336 - Self-refresh period measurement circuit of semiconductor device: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a period measurement start signal generator configured to receive a self-refresh signal and an oscillation signal, to allow a self-refresh operation to be performed, and generate a period measurement start signal, to set the time that... Agent: Cooper & Dunham, LLP
20090180337 - Data bus power-reduced semiconductor storage apparatus: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090180338 - Data output circuit of semiconductor memory apparatus and method of controlling the same: The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read command; and a data selecting unit configured to select data from a data line corresponding to a presently selected... Agent: Venable LLP
20090180340 - Semiconductor integrated circuit including column redundancy fuse block: A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the edge area.... Agent: Baker & Mckenzie LLP Patent Department
20090180339 - Semiconductor memory device with three-dimensional array and repair method thereof: A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the... Agent: Volentine & Whitt PLLC
20090180341 - Semiconductor device: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives... Agent: Foley And Lardner LLP Suite 500
20090180342 - Semiconductor memory device and driving method thereof: A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090180343 - Semiconductor memory device: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and... Agent: Miles & Stockbridge PC
20090180344 - Self-refresh period measurement circuit of semiconductor device: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a delay means for delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, and delaying the received oscillation signal to output a third delayed oscillation signal, a first... Agent: Cooper & Dunham, LLP
20090180346 - Portable data storage apparatus: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and... Agent: F. Chau & Associates, LLC
20090180345 - Voltage booster by isolation and delayed sequential discharge: Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can... Agent: Turocy & Watson, LLP
20090180347 - Semiconductor memory device and memory system including the same: Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and... Agent: Volentine & Whitt PLLC07/09/2009 > patent applications in patent subcategories. category listing
20090175062 - Feedback structure for an sram cell: Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a... Agent: Texas Instruments Incorporated
20090175063 - Semiconductor memory device including memory cell array having memory cells using floating body transistors: A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or... Agent: Volentine & Whitt PLLC
20090175064 - Semiconductor memory device with reduced coupling noise: A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit... Agent: Sughrue Mion, PLLC
20090175065 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit,... Agent: Mcdermott Will & Emery LLP
20090175066 - High-speed dram including hierarchical read circuits: DRAM includes hierarchical read circuits with multi-divided bit lines, wherein a local read circuit receives an output from a memory cell through a bit line, a segment read circuit receives an output from one of multiple local read circuits through a segment read line, and a block read circuit receives... Agent: Juhan Kim
20090175070 - Dual node access storage cell having buffer circuits: An integrated circuit includes an array of memory cells, each including a core storage element with first and second complementary storage nodes and first and second cell pass transistors coupled to the first and second storage nodes, respectively. In the cell, a first bitline (BL) is coupled to a first... Agent: Texas Instruments Incorporated
20090175068 - Sram device, and sram device design structure, with adaptable access transistors: An SRAM device comprising a pair of MCSFETs connected as access transistors (pass gates). An SRAM device design structure embodied or stored in a machine readable medium includes two MCSFETs connected as access transistors.... Agent: International Business Machines Corporation Dept. 18g
20090175067 - Sram employing a read-enabling capacitance: Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inverters having first and second storage nodes. Additionally,... Agent: Texas Instruments Incorporated
20090175069 - Storage cell having buffer circuit for driving the bitline: An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first storage node (S) and a complementary second storage node (S-bar), and a first pass gate ) coupled to the first storage node (S). A... Agent: Texas Instruments Incorporated
20090175071 - Phase change memory dynamic resistance test and manufacturing methods: A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090175072 - Phase-change random access memory devices and related methods of operation: A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column... Agent: Myers Bigel Sibley & Sajovec
20090175073 - Nanostructure-based memory: Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are disclosed. In at least some embodiments, the improved memory device is of a nonvolatile type such as a flash memory device, and... Agent: Whyte Hirschboeck Dudek S C Intellectual Property Department
20090175078 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation
20090175080 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090175075 - Flash memory storage apparatus, flash memory controller, and switching method thereof: A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower... Agent: J C Patents, Inc.
20090175076 - Memory device and method for estimating characteristics of multi-bit cell: Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data... Agent: Harness, Dickey & Pierce, P.L.C
20090175077 - Semiconductor memory device and driving method thereof: This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090175079 - Structures and methods to store information representable by a multiple-bit binary word in electrically erasable, programmable read-only memory (eeprom): Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate... Agent: Haynes And Boone, LLPIPSection
20090175082 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090175081 - Nand flash memory having multiple cell substrates: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090175083 - Nonvolatile semiconductor memory device: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines,... Agent: The Marbury Law Group, PLLC
20090175084 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation
20090175085 - Non-volatile semiconductor memory device and method of writing and reading the same: MOS transistors each having different ON withstanding voltages that are drain withstanding voltages when gates thereof are turned on are formed on the same substrate. One of the MOS transistors having the lower ON withstand voltage is used as a memory element. Using the fact that the drain withstanding voltage... Agent: Brinks Hofer Gilson & Lione
20090175074 - Device for reading a low-consumption non-volatile memory and its implementing method: The reading device enables a non-volatile memory consisting of a matrix of memory cells (TM) to be read. Once the memory cells have been selected to be read in a read cycle controlled by a microprocessor unit, sense amplifiers (4) activated at the start of each cycle supply a binary... Agent: Griffin & Szipl, PC
20090175086 - Enable signal generator method and apparatus: According to the embodiments described herein, an enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells,... Agent: Coats & Bennett/qimonda
20090175087 - Method of verifying programming operation of flash memory device: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect... Agent: Volentine & Whitt PLLC
20090175088 - Method and architecture for fast flash memory programming: Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090175089 - Retention in nvm with top or bottom injection: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090175091 - Apparatus and methods for an input circuit for a semiconductor memory apparatus: An input circuit for a semiconductor memory apparatus comprising a input unit configured to selectively latch a plurality of external signals and output the latched signal; and a control unit coupled to the input unit, the control unit configured to control the operations of the input unit according to an... Agent: Baker & Mckenzie LLP Patent Department
20090175090 - Buffered dram: A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090175092 - Semiconductor memory devices for controlling latency: A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a... Agent: Myers Bigel Sibley & Sajovec
20090175093 - Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same: An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an... Agent: Venable LLP
20090175094 - Current sensing method and apparatus for a memory array: A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected... Agent: Zagorin O'brien Graham LLP (023)
20090175095 - Voltage sensing circuit and method for operating the same: A voltage sensing circuit is capable of controlling a pumping voltage to be stably generated in a low voltage environment. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by... Agent: Mannava & Kang, P.C.
20090175096 - Semiconductor device and method for boosting word line: A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090175097 - Method for detecting erroneous word lines of a memory array and device thereof: A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling... Agent: North America Intellectual Property Corporation
20090175098 - Semiconductor memory device including floating body transistor memory cell array and method of operating the same: A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady... Agent: Volentine & Whitt PLLC
20090175099 - Single end read module for register files: A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled... Agent: K & L Gates LLP
20090175100 - Method and apparatus for storage device with a logic unit and method for manufacturing same: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090175101 - Self-feedback control pipeline architecture for memory read path applications: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock... Agent: Saile Ackerman LLC
20090175102 - Method for controlling access of a memory: A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into... Agent: Jianq Chyun Intellectual Property Office
20090175103 - Semiconductor memory asynchronous pipeline: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090175104 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
20090175106 - Apparatus for implementing efuse sense amplifier testing without blowing the efuse: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second... Agent: Ibm Corporation RochesterIPLaw Dept 917
20090175105 - Semiconductor memory device that includes an address coding method for a multi-word line test: Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks,... Agent: Harness, Dickey & Pierce, P.L.C
20090175107 - Apparatus for and method of current leakage reduction in static random access memory arrays: A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20090175109 - Current-mode sense amplifier and sense amplifying method: A current-mode sense amplifier comprises a first current mirror, a second current mirror and an amplifying circuit. The first current mirror outputs a cell current to a memory cell and duplicates the cell current to generate a mirrored cell current. The second current mirror outputs a reference current to the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090175108 - Integrated circuit, cell arrangement, method for manufacturing an integrated circuit and for reading a memory cell status, memory module: An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first... Agent: Slater & Matsil, L.L.P.
20090175110 - Non-volatile memory element and method of operation therefor: A very small magnetic tunnel junction is formed on a semiconductor p-i-n diode. Spin-polarized current which is generated by circular polarized light or elliptically-polarized light, is injected into a free layer of the magnetic tunnel junction so that magnetization direction (two opposite directions) in the free layer is changed based... Agent: Rader Fishman & Grauer PLLC
20090175111 - Circuit having gate oxide protection for low voltage fuse reads and high voltage fuse programming: A circuit for reading and programming a fuse. The electronic circuit includes a data fuse coupled to a data node and a reference fuse coupled to a reference node. A programming circuit is coupled to the data node, wherein the programming circuit is configured to, when activated, cause the data... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090175113 - Characterization of bits in a functional memory: Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports,... Agent: Texas Instruments Incorporated
20090175112 - Table lookup voltage compensation for memory cells: Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090175114 - Multi-port semiconductor memory device having variable access paths and method therefor: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and... Agent: Marger Johnson & Mccollom, P.C.
20090175116 - Clock synchronization circuit and operation method thereof: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock... Agent: Mannava & Kang, P.C.
20090175115 - Memory device, method for accessing a memory device and method for its manufacturing: Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line,... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda07/02/2009 > patent applications in patent subcategories. category listing
20090168478 - Semiconductor memory device that can relieve defective address: A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder (210) for generating a first pre-decoded address (PDA1) by pre-decoding the input address (ADD), a CAM circuit (220) for activating the match signal (MT) by responding to the indication of a... Agent: Mcginn Intellectual Property Law Group, PLLC
20090168479 - Three port content addressable memory: A novel schematic for executing search, write and valid bit clear operations in one cycle in a CAM system that includes a plurality of CAM blocks is disclosed. In one embodiment, the plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality... Agent: Wade James Brady Iii Texas Instruments Incorporated
20090168480 - Three dimensional hexagonal matrix memory array: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090168482 - Three-dimensional memory device: A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on... Agent: Volentine & Whitt PLLC
20090168481 - Tree-structure memory device: A tree-structure memory device. A tree-structure memory device comprises a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction. A plurality of layers having a plurality of memory cells is arranged... Agent: Hitachi C/o Wagner Blecher LLP
20090168484 - Multiple-port sram device: A multiple-port SRAM cell includes a latch having a first node and a second node for retaining a value and its complement, respectively. The cell has a write port separate from a read port for parallel operation. A number of transistors are used to connect the first and second nodes... Agent: K & L Gates LLP
20090168483 - Ultra low voltage and minimum operating voltage tolerant register file: Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.... Agent: Caven & Aghevli LLC C/o Cpa Global
20090168485 - Pipe latch device of semiconductor memory device: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when... Agent: Mcdermott Will & Emery LLP
20090168486 - Large capacity one-time programmable memory cell using metal oxides: A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii)... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090168487 - Cycling to mitigate imprint in ferroelectric memories: One embodiment of the present invention relates to a method for reducing the imprint of a ferroelectric memory cell. The method comprises storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is... Agent: Texas Instruments Incorporated
20090168490 - Ferroelectric memory cell with access transmission gate: One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a... Agent: Texas Instruments Incorporated
20090168489 - Ferroelectric memory devices with partitioned platelines: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least... Agent: Texas Instruments Incorporated
20090168488 - Method to improve ferroelectronic memory performance and reliability: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip.... Agent: Texas Instruments Incorporated
20090168491 - Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element and methods of forming the same: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a steering element above a substrate; and (2) fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (CNT) material above the substrate. Numerous other aspects are provided.... Agent: Dugan & Dugan, PC
20090168494 - Semiconductor device having resistance based memory array, method of operation, and systems associated therewith: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion... Agent: Harness, Dickey & Pierce, P.L.C
20090168495 - Semiconductor memory device and method of writing into semiconductor memory device: In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090168493 - Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell: In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device... Agent: Mills & Onello LLP
20090168492 - Two terminal nonvolatile memory using gate controlled diode elements: A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element.... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090168496 - Memory cell having improved write stability: A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through... Agent: Texas Instruments Incorporated
20090168497 - Memory leakage control circuit and method: In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and comprises a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected... Agent: Shreen K. Danamraj, Esq. Danamraj & Emanuelson, P.C.
20090168498 - Spacer patterned augmentation of tri-gate transistor gate length: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a... Agent: RyderIPLaw C/o Cpa Global
20090168499 - Semiconductor memory device: A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168500 - Semiconductor memory device: A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168501 - Magnetic memory and method for writing to magnetic memory: Provided is a magnetic random access memory employing spin torque magnetization reversal having a small write current value is applied. The memory includes: a switching element the conduction of which is controlled by a gate electrode, and three magnetoresistance effect elements connected to the switching element in series. Each magnetoresistance... Agent: Stanley P. Fisher Reed Smith LLP
20090168502 - Semiconductor device: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible... Agent: Miles & Stockbridge PC
20090168504 - Phase change memory apparatus having an improved cycling endurance and programing method therefor: A phase change memory apparatus includes a phase change memory array in which a plurality of phase change memory devices are arranged, and a pulse generator that supplies a writing current pulse, an erasure current pulse, and a reverse repair current pulse to the phase change memory devices in the... Agent: Bacon & Thomas, PLLC
20090168503 - Phase change memory with bipolar junction transistor select device: A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may... Agent: Trop, Pruner & Hu, P.C.
20090168505 - Semiconductor device: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which... Agent: Miles & Stockbridge PC
20090168506 - Close shaped magnetic multi-layer film comprising or not comprising a metal core and the manufacture method and the application of the same: Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic... Agent: Connolly Bove Lodge & Hutz, LLP
20090168507 - Method of programming cross-point diode memory array: A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090168508 - Static random access memory having cells with junction field effect and bipolar junction transistors: A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least... Agent: Haverstock & Owens, LLP
20090168509 - Ultra low voltage, low leakage, high density, variation tolerant memory bit cells: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.... Agent: Caven & Aghevli LLC C/o Cpa Global
20090168516 - Method for generating soft bits in flash memories: Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090168513 - Multiple level cell memory device with improved reliability: The reliability of multiple level cells in a memory device should be increased by programming the ends of the series strings of memory cells differently than the remaining quantity of memory cells of the series string. The end cells closest to select gate source and select gate drain transistors can... Agent: Leffert Jay & Polglaze, P.A.
20090168515 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality... Agent: Hogan & Hartson L.L.P.
20090168514 - Semiconductor memory device provided with memory cells having charge storage layer and control gate: A semiconductor memory device includes a memory cell, a source line, and a source line control circuit. The memory cell includes a charge storage layer and a control gate and is capable of holding 2 levels or more levels of data. The source line is electrically connected to a source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168518 - Chip select controller and non-volatile memory device including the same: A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer... Agent: Townsend And Townsend And Crew, LLP
20090168517 - Read and volatile nv standby disturb: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.... Agent: Cypress Semiconductor Corporation
20090168520 - 3t high density nvdram cell: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.... Agent: Cypress Semiconductor Corporation
20090168521 - 5t high density nvdram cell: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a... Agent: Cypress Semiconductor Corporation
20090168519 - Architecture of a nvdram array and its sense regime: A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.... Agent: Cypress Semiconductor Corporation
20090168523 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168522 - Semiconductor memory device with improved ecc efficiency: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168524 - Wear level estimation in analog memory cells: A method for operating a memory includes applying at least one pulse to a group of analog memory cells, so as to cause the memory cells in the group to assume respective storage values. After applying the pulse, the respective storage values are read from the memory cells in the... Agent: D. Kligler I.p. Services Ltd
20090168525 - Flash memory controller having reduced pinout: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing... Agent: Haynes And Boone, LLPIPSection
20090168526 - Flash memory device having dummy cell: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an... Agent: Volentine & Whitt PLLC
20090168528 - Flash memory device and data i/o operation method thereof: A flash memory device comprises a memory cell array, an input buffer unit, an output driver unit, first and second page buffer units, and first and second data handling units. The memory cell array includes two or more memory banks. During a data input operation, the first and second data... Agent: Townsend And Townsend And Crew, LLP
20090168527 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, and at least first and second page buffers to which the plurality of bit lines are connected. The plurality of word lines are divided into first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168529 - Nonvolatile semiconductor memory device, method for manufacturing the same, and nonvolatile memory array: A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart... Agent: Mcdermott Will & Emery LLP
20090168530 - Semiconductor storage device and method of reading data therefrom: A semiconductor memory device comprises a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168531 - Method for programming a memory structure: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure... Agent: North America Intellectual Property Corporation
20090168532 - Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays: A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to... Agent: Myers Bigel Sibley & Sajovec
20090168533 - Three-dimensional memory device and programming method: A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in... Agent: Volentine & Whitt PLLC
20090168534 - Three-dimensional memory device with multi-plane architecture: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat... Agent: Volentine & Whitt PLLC
20090168537 - Method of programming a non-volatile memory device: A method of programming a non-volatile memory device includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a program operation, wherein the word lines do not include a second word line adjacent to the... Agent: Lowe Hauptman Ham & Berner, LLP
20090168536 - Method of programming non-volatile memory device: A method of programming a non-volatile memory device includes applying a power supply voltage to a drain select line, applying a high level voltage to a drain-side pass word line or a source-side pass word line, and applying a pass voltage to unselected word lines and a program voltage to... Agent: Lowe Hauptman Ham & Berner, LLP
20090168538 - Method of programming non-volatile memory device: A programming method of a non-volatile memory device may include providing a memory device in which a first word line is preprogrammed in an erase operation of a memory block, pre-programming a second word line according to a program command, and programming the first word line.... Agent: Marshall, Gerstein & Borun LLP
20090168535 - Non-volatile memory device and method of operating the same: A non-volatile memory device includes a memory cell array and a controller. The memory cell array includes memory cells for data storage and a plurality of flag cells. The flag cells indicate program states of the memory cells for each of a plurality of word lines. The controller determines the... Agent: Townsend And Townsend And Crew, LLP
20090168539 - Semiconductor integrated circuit and unstable bit detection method for the same: A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC
20090168511 - Flash memory device and reading method thereof: Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection... Agent: Harness, Dickey & Pierce, P.L.C
20090168510 - Method of operating non-volatile memory device: The present invention relates to an operation of a non-volatile memory device. According to a method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting... Agent: Marshall, Gerstein & Borun LLP
20090168512 - Nonvolatile memory: A nonvolatile memory wherein remaining lifetimes of memory cells can be accurately determined is provided, the nonvolatile memory includes: plural memory cell groups, assigned with respective addresses, arranged for respective words and used for storing one word of data; plural dummy cell groups also assigned the respective addresses and having... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090168540 - Low noise sense amplifier array and method for nonvolatile memory: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090168541 - Electrical erasable programmable memory transconductance testing: A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics... Agent: Freescale Semiconductor, Inc. Law Department
20090168542 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168544 - Erase method and soft programming method of non-volatile memory device: An erase method and a soft programming method of a non-volatile memory device includes performing an erase operation on a memory cell block; applying a pass voltage to a memory cell adjacent to a select transistor of the memory cell block; applying a soft program voltage to the remaining memory... Agent: Lowe Hauptman Ham & Berner, LLP
20090168543 - Method of operating a non-volatile memory device: A method of operating a non-volatile memory device changes a read voltage by determining a degree that threshold voltages of memory cells are changed and overlap each other. The method of operating the non-volatile memory device includes performing a least significant bit (LSB) program of memory cells and determining a... Agent: Townsend And Townsend And Crew, LLP
20090168545 - Semiconductor device and method of fabricating the same: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a first wafer including a light emitting diode (LED), a second wafer including a flash cell formed corresponding to the LED, and a conductive via that electrically connects the first wafer to the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090168547 - Apparatus and methods for a data input circuit for a semiconductor memory apparatus: A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a... Agent: Baker & Mckenzie LLP Patent Department
20090168549 - Data output buffer circuit and semiconductor memory device includig the same: The example embodiments provide a data output buffer circuit which includes a pre-driver configured to adjust a slew rate of an input signal, a main driver configured to output signal supplied from the pre-driver, and a ZQ calibration circuit configured to control the pre-driver so as to decrease the slew... Agent: Harness, Dickey & Pierce, P.L.C
20090168548 - Data output circuit in semiconductor memory apparatus: A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to... Agent: Baker & Mckenzie LLP Patent Department
20090168551 - Low voltage sense amplifier and sensing method: Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier.... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090168550 - Output port, microcomputer and data output method: An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding... Agent: Mcginn Intellectual Property Law Group, PLLC
20090168546 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090168552 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090168553 - Semiconductor memory device and method of operating the same: Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090168555 - Delay circuit and semiconductor memory device having the same: A delay circuit is capable of securing a constant delay time in spite of a process variation as well as voltage and temperature variations. Using the delay circuit that secures a sensing margin time in spite of process, voltage and temperature variations, a semiconductor memory device is capable of amplifying... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090168554 - Low couple effect bit-line voltage generator: A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a... Agent: Volpe And Koenig, P.C.
20090168556 - Semiconductor memory device for generating back-bias voltage with variable driving force: A semiconductor memory device is capable of maintaining a predetermined back-bias voltage level regardless of operation modes of the semiconductor memory device, by generating a back-bias voltage with driving force changed according to the operation modes. The semiconductor memory device includes an active pumping control signal generating unit for generating... Agent: Mannava & Kang, P.C.
20090168558 - 1-transistor type dram driving method with an improved write operation margin: A 1-transistor type DRAM driving process writes a data bit that corresponds to a level applied to a bit line. A first hold period holds data by deactivating a word line of an NMOS transistor and precharging a source and bit line. After the first hold period, a complex operation... Agent: Ladas & Parry LLP
20090168557 - Ultra wide voltage range register file circuit using programmable triple stacking: Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.... Agent: Caven & Aghevli LLC C/o Cpa Global
20090168559 - Method of and apparatus for reading data: Provided are an apparatus and a method of capturing data by using a data transition of a data signal. The method includes detecting a data transition of a data signal input from an external source, generating a pulse signal corresponding to the detected data transition, and capturing the data signal... Agent: Sughrue Mion, PLLC
20090168560 - Circuit and method for controlling local data line in semiconductor memory device: The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on local data lines LIO. The circuit and method for controlling local data lines in accordance with the present invention is characterized by having... Agent: Mannava & Kang, P.C.
20090168562 - Semiconductor device, information control method and electronic device: A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first... Agent: Arent Fox LLP
20090168561 - Test entry circuit and method for generating test entry signal: Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test... Agent: Mannava & Kang, P.C.
20090168563 - Apparatus, system, and method for bitwise deskewing: A system and method for bitwise deskew. A DQS timing is used as reference, the delays of a plurality of transmission wires are calibrated with reference to a DQS line timing. Other embodiments are described and claimed.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090168566 - Semiconductor memory device: A semiconductor memory device adjusts an activation timing and pulse width of a pin strobe signal according to a power supply voltage variation, and thereby loads data on a pipelatch properly and prevents an activation period of a pin strobe signal from falling out of a period for valid data.... Agent: Mannava & Kang, P.C.
20090168565 - Semiconductor memory device and method for operating the same: Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal,... Agent: Mannava & Kang, P.C.
20090168564 - Strobe signal controlling circuit: A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal... Agent: Cooper & Dunham, LLP
20090168567 - Semiconductor memory device: A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit... Agent: Mannava & Kang, P.C.
20090168568 - Semiconductor memory device and method for operating the same: A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal... Agent: Mannava & Kang, P.C.
20090168571 - Dynamic random access memory device and method of determining refresh cycle thereof: Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal... Agent: Volentine & Whitt PLLC
20090168569 - Method and device for redundancy replacement in semiconductor devices using a multiplexer: A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.... Agent: Posz Law Group, PLC
20090168570 - Redundancy circuit using column addresses: A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about... Agent: Baker & Mckenzie LLP Patent Department
20090168572 - Semiconductor memory: In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is... Agent: Whitham, Curtis & Christofferson & Cook, P.C.
20090168573 - Adaptive memory array voltage adjustment: In some embodiments a sensor is to sense a temperature of a memory occurring in the memory during active use of the memory. A controller is to adjust a voltage supply of the memory during active use of the memory in response to the sensed temperature. In some embodiments a... Agent: Intel Corporation C/o Cpa Global
20090168574 - Method of driving 1-transistor type dram having an nmos overlain on top of an soi layer: Driving a 1-transistor DRAM composed of an NMOS on top of a SOI layer such that the 1-transistor DRAM has a corresponding parasitic bipolar transistor component includes precharging, shifting, and deactivating steps. Implementing these steps can result in enhancing the performance of reading, writing and storing binary logic information within... Agent: Ladas & Parry LLP
20090168575 - Device and method to reduce simultaneous switching noise: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic... Agent: Teradyne, Inc. C/o Foley & Larder, LLP
20090168576 - Semiconductor memory device: A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090168577 - Semiconductor storage device, and data reading method: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the... Agent: Arent Fox LLP
20090168578 - Dummy cell for memory circuits: A memory cell array includes reference cells each associated with a plurality of data cells of the array.... Agent: Cypress Semiconductor Corporation
20090168579 - Random access memory data resetting method: A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the... Agent: Jianq Chyun Intellectual Property Office
20090168580 - Fuse monitoring circuit for semiconductor memory device: A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial... Agent: Mannava & Kang, P.C.
20090168581 - Fuse monitoring circuit for semiconductor memory device: A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of... Agent: Mannava & Kang, P.C.
20090168586 - Circuit to control voltage ramp rate: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a... Agent: Schwegman, Lundberg & Woessner / Atmel
20090168582 - Internal voltage generating circuit and semiconductor memory device using the same: Disclosed is an internal voltage generating circuit. The internal voltage generating circuit comprises a voltage divider for generating a level signal by voltage-dividing first internal voltage, a pull-down signal generator for generating a pull-down signal, which has a level adjusted according to a temperature, in response to the level signal,... Agent: Cooper & Dunham, LLP
20090168583 - Internal voltage generator of semiconductor memory device: An internal voltage generator of a semiconductor memory device generates pumping voltages (VPP, VBB, etc.) as internal voltages, which is capable of improving a charge pumping scheme. The internal voltage generator includes a plurality of charge pumping units for generating a pumping voltage by performing a charge pumping operation according... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090168585 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output... Agent: Mannava & Kang, P.C.
20090168584 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down... Agent: Mannava & Kang, P.C.
20090168588 - Low current consumption semiconductor memory device having input/output control circuit and control method thereof: A low-current consumption semiconductor memory device includes a plurality of cell blocks, in which each cell block includes a plurality of cell mats; a plurality of input/output line switches which transmit the plurality of cell blocks to input/output lines; and an input/output line control circuit which receives a block address... Agent: Ladas & Parry LLP
20090168587 - Semiconductor memory device: A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belonging to the respective memory block groups are arranged adjacently in the... Agent: Mannava & Kang, P.C.
20090168589 - Thermal code transmission circuit and semiconductor memory device using the same: Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a... Agent: Cooper & Dunham, LLPPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.4523 seconds