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Static information storage and retrieval June invention type 06/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/25/2009 > patent applications in patent subcategories.
20090161400 - Leakage current cut-off device for ternary content addressable memory: A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary... Agent: Rosenberg, Klein & Lee
20090161399 - Super leakage current cut-off device for ternary content addressable memory: A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.... Agent: Rosenberg, Klein & Lee
20090161402 - Data storage and stackable configurations: A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC
20090161401 - Multi-die memory, apparatus and multi-die memory stack: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common... Agent: Slater & Matsil, L.L.P.
20090161403 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent: Frommer Lawrence & Haug
20090161404 - Asymmetric dipolar ring: A device having a dipolar ring surrounding an interior region that is disposed asymmetrically on the ring. The dipolar ring generates a toroidal moment switchable between at least two stable states by a homogeneous field applied to the dipolar ring in the plane of the ring. The ring may be... Agent: Wright, Lindsey & Jennings LLP
20090161405 - Data storage medium and associated method: A reference plane extends globally parallel to the sensitive material layerand is configured to pass along it at least one element for application of an electrostatic field in combination with the electrode layer. The storage medium also includes, parallel to the reference plane, a plurality of conductive portions forming part... Agent: Brinks Hofer Gilson & Lione
20090161407 - Drive method of nanogap switching element and storage apparatus equipped with nanogap switching element: A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element... Agent: Crowell & Moring LLP Intellectual Property Group
20090161406 - Non-volatile memory and method for fabricating the same: A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate.... Agent: Jianq Chyun Intellectual Property Office
20090161408 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array including memory cells arranged in matrix each having a selective transistor and a variable resistance element having an electric resistance changed from a first state to a second state by applying a first write voltage and from the second state to... Agent: Morrison & Foerster LLP
20090161412 - Semiconductor memory: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to... Agent: Mcdermott Will & Emery LLP
20090161411 - Semiconductor memory device: A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090161410 - Seven transistor sram cell: The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having... Agent: Texas Instruments Incorporated
20090161413 - Mram device with shared source line: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source... Agent: Qualcomm Incorporated
20090161414 - Spin torque magnetic memory and offset magnetic field correcting method thereof: An object of the present invention corrects fluctuation of a writing current between cells in a magnetic random access memory using spin torque magnetization reversal. The present invention includes a magneto-resistive effect element that is disposed between a bit line and a word line, a first variable resistance element that... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090161420 - Field-emitter-based memory array with phase-change storage devices: Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same.... Agent: Goodwin Procter LLP Patent Administrator
20090161415 - Integrated circuit for setting a memory cell based on a reset current distribution: An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current... Agent: Dicke, Billig & Czaja
20090161419 - Nonvolatile memory, memory system, and method of driving: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a... Agent: Volentine & Whitt PLLC
20090161416 - Optimized phase change write method: A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control... Agent: Scully, Scott, Murphy & Presser, P.C.
20090161418 - Phase change memory device having decentralized driving units: A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving... Agent: Ladas & Parry LLP
20090161421 - Phase change memory devices and systems, and related programming methods: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied... Agent: Volentine & Whitt PLLC
20090161417 - Two cell per bit phase change memory: A phase change memory array may have a plurality of cells in which a bit is determined by a single cell. In addition, a portion of the array may include a plurality of cells which are combined so that two cells form one bit of memory. One of the combined... Agent: Trop, Pruner & Hu, P.C.
20090161423 - Magnetic random access memory: An MRAM having a first cell array group (2-0) and a second cell array group (2-1) containing a plurality of cell arrays (21) is used. Each of the first cell array group (2-0) and the second cell array group (2-1) includes a first current source unit for supplying a first... Agent: Young & Thompson
20090161422 - Magnetic tunnel junction device with separate read and write paths: In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.... Agent: Qualcomm Incorporated
20090161424 - Thermally assisted magnetic write memory: A thermally assisted magnetic write memory including of memory points or memory cells, each of which includes a double magnetic tunnel junction separated from one another by a layer made from an antiferromagnetic material, and whereof the stacking order of the layers constituting them is reversed with regard to one... Agent: Burr & Brown
20090161426 - Memory programming method and data access method: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090161425 - Method of determining a flag state of a non-volatile memory device: In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n... Agent: Townsend And Townsend And Crew, LLP
20090161427 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090161430 - Bit map control of erase block defect list in a memory: Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits,... Agent: Turocy & Watson, LLP
20090161431 - Built-in self-repair method for nand flash memory and system thereof: A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in... Agent: Wpat, PC Intellectual Property Attorneys
20090161429 - Dynamic column redundancy replacement: A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to... Agent: Schwegman, Lundberg & Woessner / Atmel
20090161428 - Load balancing by using clock gears: An electronic device is capable of monitoring internal components to predict changes in processing power needs. When a prediction is made, a clock control circuit can be instructed to increase the clock signal frequency in response to a predicted increase in processing power needs, or decrease the clock signal frequency... Agent: Weaver Austin Villeneuve Sampson LLP
20090161432 - Flash memory device and operating method thereof: A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source... Agent: Townsend And Townsend And Crew, LLP
20090161435 - Non-volatile memory device and method of programming the same: When performing a program operation, a non-volatile memory device comprising a multi-plane performs a cache write operation by employing a page buffer circuit of a plane that does not perform the program operation. A data line mux transfers an externally input first data to a page buffer unit of a... Agent: Townsend And Townsend And Crew, LLP
20090161434 - Read, verify word line reference voltage to track source level: A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090161433 - Regulation of source potential to combat cell source ir drop: Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090161437 - Hierarchical common source line structure in nand flash memory: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line... Agent: Ridout & Maybee LLP
20090161436 - Semiconductor memory device: The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090161438 - Methods of forming and programming floating-gate memory cells having carbon nanotubes: Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated... Agent: Leffert Jay & Polglaze, P.A.
20090161439 - Nonvolatile semiconductor memory device: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines,... Agent: The Marbury Law Group, PLLC
20090161440 - Integrated circuits and discharge circuits: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090161441 - Nonvolatile semiconductor memory and method for driving the same: To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells. The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor... Agent: Brinks Hofer Gilson & Lione
20090161442 - Data processing system: A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A... Agent: Nixon & Vanderhye P.C.
20090161446 - Input circuit of semiconductor memory device ensuring enabled data input buffer during data input: An input circuit of a semiconductor memory device that prevents data from being input into a data input buffer prior to the enablement of the data input buffer. The input circuit includes an input buffer enabling control unit that generates an input buffer enabling signal which is enabled before a... Agent: Ladas & Parry LLP
20090161444 - Page buffer and programming method of a non-volatile memory device: A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level... Agent: Townsend And Townsend And Crew, LLP
20090161443 - Page buffer of non-volatile memory device and programming method of non-volatile memory device: A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data... Agent: Townsend And Townsend And Crew, LLP
20090161445 - Semiconductor memory device and data masking method of the same: A semiconductor memory device has a data masking function during a write operation. The semiconductor memory device includes a data mask input unit that receives a data mask signal. A data input unit receives data and delays the output of the data more than the output of the data mask... Agent: Ladas & Parry LLP
20090161447 - Semiconductor memory input/output device: A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe... Agent: Mannava & Kang, P.C.
20090161448 - Semiconductor memory device overdriving for predetermined period and bitline sense amplifying method of the same: A semiconductor memory device overdriving for a predetermined period when sense amplifying a bitline. An overdriving control unit generates an overdriver enabling signal having an enabling period including a point to enable a bitline sense amplifier and a point to select a column. An overdriver provides an overdrive voltage of... Agent: Ladas & Parry LLP
20090161449 - Semiconductor storage device: A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a... Agent: Mcdermott Will & Emery LLP
20090161450 - Storage data unit using hot carrier stressing: The memory comprises at least two data storage units using hot carrier stressing damage to store data. Each data storage unit comprises the first terminal, the second terminal and a third terminal. When the first cross voltage between the second and third terminals is higher than the first threshold voltage... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090161451 - Dual function compatible non-volatile memory device: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090161455 - Data input apparatus with improved setup/hold window: In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal... Agent: Ladas & Parry LLP
20090161453 - Method and apparatus for calibrating write timing in a memory system: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a... Agent: Pvf -- Rambus, Inc. C/o Park, Vaughan & Fleming, LLP
20090161454 - Ringing masking device having buffer control unit: A ringing masking device includes a data strobe buffer unit buffering a data strobe signal and outputting a rising pulse and a falling pulse synchronized with a buffer signal. A buffer control unit latches a burst end signal to generate a buffer control signal and outputs the buffer control signal... Agent: Ladas & Parry LLP
20090161452 - Systems and methods for clean dqs signal generation in source-synchronous ddr2 interface design: A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090161456 - Semiconductor memory device which delays refreshment signal for performing self-refreshment: A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment modes from an input command, outputs type data which indicates the detected refreshment mode, and outputs a refreshment signal which indicates the start... Agent: Mcginn Intellectual Property Law Group, PLLC
20090161458 - Circuit and method for testing multi-device systems: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system,... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090161457 - Semiconductor storage device having redundancy area: A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a... Agent: Mcginn Intellectual Property Law Group, PLLC
20090161459 - Dynamic random access memory with low-power refresh: A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a... Agent: Ip Legal Services
20090161460 - Retention test system and method for resistively switching memory devices: A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a... Agent: Dicke, Billig & Czaja
20090161461 - Semiconductor memory device maintaining word line driving voltage: A semiconductor memory for maintaining a word line driving voltage includes a cell array and a sense amplifier adjacent to the cell array. A dummy cell is formed at a peripheral portion of the cell array in such a manner that a dummy bit line and a word line intersect.... Agent: Ladas & Parry LLP
20090161463 - Circuit providing compensated power for sense amplifier and driving method thereof: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a... Agent: Ladas & Parry LLP
20090161462 - Controlling ac disturbance while programming: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate... Agent: Turocy & Watson, LLP
20090161464 - Semiconductor memory device: A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090161465 - Non-volatile memory device having high speed serial interface: A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data... Agent: Dla Piper LLP (us )
20090161466 - Extending flash memory data retension via rewrite refresh: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to... Agent: Turocy & Watson, LLP
20090161467 - Memory device and refresh method thereof: A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to... Agent: Jianq Chyun Intellectual Property Office
20090161469 - Semiconductor integrated circuit and system: The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on... Agent: Arent Fox LLP
20090161468 - Semiconductor memory, memory system, and memory access control method: A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency... Agent: Arent Fox LLP
20090161470 - Circuit for dynamic readout of fused data in image sensors: A circuit for reading fused data, an image sensing apparatus, a method of reading fused data and a method of manufacturing a circuit for reading fused data. The circuit includes a fuse and a capacitive component configured to provide a data input signal to a data input node of a... Agent: Ratnerprestia
20090161472 - Memory voltage control circuit: A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the... Agent: PCe Industry, Inc. Att. Steven Reiss
20090161473 - Method and apparatus for managing behavior of memory devices: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed... Agent: Dickstein Shapiro LLP
20090161471 - Power supply device: A power supply device is provided according to the present invention. The power supply device is applicable to electronic device, which has a non-volatile memory and a power supply circuit that provides power to the non-volatile memory. The power supply device includes: a power consuming unit for providing the non-volatile... Agent: Edwards Angell Palmer & Dodge LLP
20090161474 - Reversible-polarity decoder circuit and method: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)
20090161475 - System for providing read clock sharing between memory devices: A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an... Agent: Cantor Colburn LLP-ibm Poughkeepsie06/18/2009 > patent applications in patent subcategories.
20090154212 - Memory module: A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to... Agent: Lee & Morse, P.C.
20090154211 - Placement and routing of ecc memory devices for improved signal timing: Various exemplary embodiments are a printed circuit board and related method of manufacturing, the printed circuit board including a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at... Agent: Kramer & Amado, P.C.
20090154214 - Semiconductor memory: Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi, . . . , AAn, which extend on a memory cell array along the column length; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154213 - Semiconductor memory device with hierarchical bit line structure: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the... Agent: Volentine & Whitt PLLC
20090154215 - Reducing noise and disturbance between memory storage elements using angled wordlines: Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and... Agent: Amin, Turocy & Calvin, LLP
20090154216 - Semiconductor memory device and semiconductor device group: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090154217 - High speed otp sensing scheme: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090154218 - Memory arrays using nanotube articles with reprogrammable resistance: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device,... Agent: Wilmerhale/boston
20090154219 - Three-dimensional magnetic memory with multi-layer data storage layers: Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. The data storage layers are each formed from a multi-layer structure. At ambient temperatures, the multi-layer structures exhibit an antiparallel coupling state with a... Agent: Duft Bornsen & Fishman, LLP
20090154220 - Plateline driver for a ferroelectric memory: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage... Agent: Texas Instruments Incorporated
20090154221 - Non-volatile memory device using variable resistance element with an improved write performance: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first... Agent: Harness, Dickey & Pierce, P.L.C
20090154222 - Operation method for multi-level switching of metal-oxide based rram: Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090154223 - Method and device for demultiplexing a crossbar non-volatile memory: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping... Agent: Seed Intellectual Property Law Group PLLC
20090154224 - Magnetic random access memory and write method of the same: A spin transfer type magnetic random access memory includes a magnetoresistive effect element including a fixed layer, a recording layer, and a nonmagnetic layer, a source line connected to one terminal of the magnetoresistive effect element, a transistor having a current path whose one end is connected to the other... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154225 - Thin film magnetic memory device having a highly integrated memory array: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As... Agent: Mcdermott Will & Emery LLP
20090154227 - Integrated circuit including diode memory cells: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell... Agent: Dicke, Billig & Czaja
20090154226 - Integrated circuit including quench devices: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.... Agent: Dicke, Billig & Czaja
20090154228 - Random access memory employing read before write for resistance stabilization: An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.
20090154230 - Magnetic memory device and method: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode... Agent: Buchanan, Ingersoll & Rooney PC
20090154229 - Sensing and writing to magnetic random access memory (mram): A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Maryam Imam
20090154231 - Magnetic random access memory and operating method of the same: A magnetic random access memory of a spin transfer process, includes a plurality of magnetic memory cells 10, a current supply unit 43+20+30 and a control unit 41. The current supply unit 43+20+30 supplies a write current to the magnetic memory cell 10. The control unit controls a supply of... Agent: Mcginn Intellectual Property Law Group, PLLC
20090154232 - Disturb control circuits and methods to control memory disturbs among multiple layers of memory: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for controlling memory disturbs to and among multiple layers of memory that include, for example, third dimensional memory technology. Each layer of memory can include a plurality of non-volatile... Agent: Unity Semiconductor Corporation
20090154233 - Nand type memory and programming method thereof: A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090154237 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154239 - Nonvolatile semiconductor storage apparatus: A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154238 - Programming multilevel cell memory arrays: Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first... Agent: Leffert Jay & Polglaze, P.A.
20090154234 - Reading electronic memory utilizing relationships between cell state distributions: Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell.... Agent: Amin, Turocy & Calvin, LLP
20090154235 - Reduced state quadbit: A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in... Agent: Eschweiler & Associates, LLC National City Bank Building
20090154236 - Systems and methods for discrete channel decoding of ldpc codes for flash memory: Embodiments include systems and methods for soft encoding and decoding of data for flash memories using Log-Likelihood Ratios (LLRs). The LLRs are computed from statistics determined by observation of flash memory over time. In some embodiments, the write, retention and read transition probabilities are computed based on the observed statistics.... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global
20090154240 - Nand flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive... Agent: Myers Bigel Sibley & Sajovec
20090154241 - Nonvolatile semiconductor memory, method for reading out thereof, and memory card: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154242 - Flash memory with optimized write sector spares: In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090154243 - Nand-type flash memory and semiconductor memory device: A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154244 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154245 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device includes: a memory cell array in which electrically rewritable nonvolatile memory cells are arranged; and a register that holds good/bad information on a specific area that requires high reliability in a user accessible area of the memory cell array. An address conversion circuit internally accesses,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154246 - Programming in memory devices using source bitline voltage bias: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate... Agent: Amin, Turocy & Calvin, LLP
20090154247 - Programming memory devices: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory... Agent: Leffert Jay & Polglaze, P.A.
20090154248 - Nonvolatile memory device storing data based on change in transistor characteristics: A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials... Agent: Ladas & Parry LLP
20090154249 - Sense amplifier for low-supply-voltage nonvolatile memory cells: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the... Agent: Schwabe, Williamson & Wyatt, P.C.
20090154251 - Algorithm for charge loss reduction and vt distribution improvement: Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the... Agent: Eschweiler & Associates, LLC National City Bank Building
20090154250 - Method for reading nonvolatile memory at power-on stage: A method for reading data in a nonvolatile memory at a power-on stage is provided and includes the following steps. Firstly, the data are read through a reference voltage. Next, a failure number is counted when reading the data has a fail result. Next, the reference voltage is adjusted when... Agent: Volpe And Koenig, P.C.
20090154252 - Semiconductor memory device capable of shortening erase time: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154253 - semiconductor device: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090154254 - Cluster based non-volatile memory translation layer: An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to appear as a freely rewriteable device to a system or processor. Embodiments of... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20090154256 - Integrated circuit memory devices including delayed clock inputs for input/output buffers and related systems and methods: A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of... Agent: Myers Bigel Sibley & Sajovec
20090154257 - Memory system and control method for memory: The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control... Agent: Arent Fox LLP
20090154255 - Symmetrically operating single-ended input buffer devices and methods: Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090154258 - Floating body control in soi dram: A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied... Agent: Scully, Scott, Murphy & Presser, P.C.
20090154259 - Swapped-body ram architecture: A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation,... Agent: Baker Botts L.L.P.
20090154260 - Scan sensing method that improves sensing margins: Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory... Agent: Amin, Turocy & Calvin, LLP
20090154261 - Reference-free sampled sensing: Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory... Agent: Amin, Turocy & Calvin, LLP
20090154262 - Semiconductor device and method for writing data into memory: It is an object to provide memory and a semiconductor device in which falsification of data written thereinto is prevented. The memory includes a memory circuit, a writing circuit, and a reading circuit. The memory circuit has a memory cell array in which a plurality of memory cells where “0”... Agent: Nixon Peabody, LLP
20090154263 - Design structure for improving performance of sram cells, sram cell, sram array, and write circuit: A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to... Agent: International Business Machines Corporation Dept. 18g
20090154264 - Integrated circuits, memory controller, and memory modules: In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining... Agent: Slater & Matsil, L.L.P.
20090154265 - Semiconductor memory device with hierarchical bit line structure: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the... Agent: Volentine & Whitt PLLC
20090154266 - Semiconductor integrated circuit, memory system and electronic imaging device: A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105) for fetching the read data from the DDR-SDRAMs (110, 120), and transferring the read data, latch... Agent: Mcdermott Will & Emery LLP
20090154267 - Clock signal generating circuit and data output apparatus using the same: A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit... Agent: Cooper & Dunham, LLP
20090154268 - Dll circuit, imaging device, and memory device: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the... Agent: Mcdermott Will & Emery LLP
20090154269 - Managing redundant memory in a voltage island: An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power... Agent: Hoffman Warnick LLC
20090154270 - Failing address register and compare logic for multi-pass repair of memory arrays: An integrated circuit having an integrated circuit and method for moving a failing address into a next available FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. A method of is disclosed that includes: providing a set of FARs and an associated set of redundant elements,... Agent: Hoffman Warnick LLC
20090154272 - Fuse apparatus for controlling built-in self stress and control method thereof: A fuse apparatus for controlling a built-in self stress unit including a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record... Agent: Mannava & Kang, P.C.
20090154273 - Memory including a performance test circuit: A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory... Agent: Hogan & Hartson LLP
20090154271 - Semiconductor memory device and method for testing the same: Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and outputting the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090154274 - Memory read stability using selective precharge: A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between... Agent: Qualcomm Incorporated
20090154275 - Semiconductor device and testing method thereof: A semiconductor device includes a sense amplifier, a drive circuit that operatively supplies a predetermined potential to the sense amplifier, and disconnection transistors that are provided between the sense amplifier and the drive circuit. According to the present invention, the disconnection transistors can disconnect the sense amplifier from the drive... Agent: Mcdermott Will & Emery LLP
20090154276 - Auto-refresh controlling apparatus: An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated.... Agent: Cooper & Dunham, LLP
20090154278 - Memory device with self-refresh operations: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing... Agent: John P. O'banion O'banion & Ritchey LLP
20090154277 - Method of reducing current of memory in self-refreshing mode and related memory: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a... Agent: North America Intellectual Property Corporation
20090154279 - Refresh period signal generator with digital temperature information generation function: A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one... Agent: Baker & Mckenzie LLP Patent Department
20090154280 - Nonvolatile memory device: A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090154281 - Semiconductor device with reduced standby failures: A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for... Agent: Volentine & Whitt PLLC
20090154282 - Semiconductor device: A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data... Agent: Knobbe Martens Olson & Bear LLP
20090154283 - System for blocking multiple memory read port activation: A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity... Agent: Cantor Colburn LLP - IBM Research Triangle Park
20090154284 - Semiconductor memory device suitable for interconnection in a ring topology: A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set... Agent: Smart & Biggar
20090154285 - Memory controller with flexible data alignment to clock: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090154286 - N-bit shift register controller: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end... Agent: Hogan & Hartson LLP06/11/2009 > patent applications in patent subcategories.
20090147556 - Low power match-line sensing circuit: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low... Agent: Eaton Peabody Patent Group, LLC
20090147557 - 3d chip arrangement including memory manager: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface... Agent: Hollingsworth & Funk, LLC
20090147558 - Variable resistance element, method for producing the same, and nonvolatile semiconductor storage device: The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance... Agent: Birch Stewart Kolasch & Birch
20090147559 - Memory cell array and semiconductor memory device including the same: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second... Agent: Volentine & Whitt PLLC
20090147560 - Novel sram cell design to improve stability: A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell... Agent: Scully, Scott, Murphy & Presser, P.C.
20090147561 - Semiconductor storage device: A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any... Agent: Amin, Turocy & Calvin, LLP
20090147562 - Compound cell spin-torque magnetic random access memory: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20090147563 - Integrated circuit for programming a memory element: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted... Agent: Dicke, Billig & Czaja
20090147565 - Method and apparatus for accessing a phase-change memory: Fixed-voltage programming pulses are employed to program a phase change memory cell. A burst of incrementally widening fixed-voltage programming pulses may be employed to program a phase change memory to a target threshold voltage.... Agent: Ovonyx, Inc
20090147566 - Phase change memory and control method thereof: A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value... Agent: Wang Law Firm, Inc.
20090147564 - Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods: A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090147567 - Magnetic memory cell structure with thermal assistant and magnetic dynamic random access memory: A magnetic memory cell structure with thermal assistant includes a magnetic pinned layer, a barrier layer, a magnetic free layer, a perpendicular magnetic layer, and a heating layer sequentially stacked. The magnetic free layer has a longitudinal magnetization. The perpendicular magnetic layer has a perpendicular magnetization at a first temperature... Agent: Jianq Chyun Intellectual Property Office
20090147568 - Memory elements and methods of using the same: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20090147569 - Flash memory program inhibit scheme: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090147571 - Self-boosting system with suppression of high lateral electric fields: In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090147573 - Faster programming of multi-level non-volatile storage through reduced verify operations: Programming speed for multi-level non-volatile storage elements is increased by reducing the number of verify operations. In one approach, verify operations are initially performed for the highest state less frequently than for other, lower states based on a recognition that a wider threshold voltage distribution for the highest state can... Agent: Vierra Magen/sandisk Corporation
20090147574 - Flash memory device for determining most significant bit program: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming... Agent: F. Chau & Associates, LLC
20090147572 - Method, apparatus, and system for erasing memory: Methods, apparatus, and systems may operated such as to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. One such pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the... Agent: Schwegman, Lundberg & Woessner/micron
20090147575 - Nor flash memory device with a serial sensing operation and method of sensing data bits in a nor flash memory device: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially... Agent: Mills & Onello LLP
20090147576 - Floating gate with universal etch stop layer: Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example,... Agent: Vierra Magen/sandisk Corporation
20090147577 - Non-volatile semiconductor latch using hot-electron injection devices: The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a 0.6 m BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash EEPROM. Suggested is a bi-stable latch circuit having... Agent: Hunton & Williams LLP Intellectual Property Department
20090147578 - Combined volatile nonvolatile array: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.... Agent: Cypress Semiconductor Corporation
20090147579 - Non-volatile memory systems and methods including page read and/or configuration features: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment... Agent: Dla Piper LLP (us )
20090147580 - One-transistor floating-body dram cell device with non-volatile function: Disclosed herein is a one-transistor (1T) floating-body Dynamic Random Access Memory (DRAM) cell device with a non-volatile function for implementing the high integration/high performance DRAM. The 1T floating-body DRAM cell device includes a floating body for storing information of the DRAM cell device, a source and a drain formed on... Agent: The Nath Law Group
20090147581 - Nand flash memory and memory system: A NAND flash memory comprising blocks which are units of writing and deletion of data, the block comprising: memory cells from which data corresponding to values of held threshold voltages can be read by applying a reading voltage to control gates of the memory cells; source-side selection gate transistors connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090147582 - Adjusting program and erase voltages in a memory device: There is provided a method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a... Agent: Fletcher Yoder (micron Technology, Inc.)
20090147583 - Semiconductor memory device having mat structure: A semiconductor memory device having a mat structure. The semiconductor memory device may comprise a first mat having a plurality of first memory cells and a second mat having a plurality of second memory cells. The first and second mats are formed in a single well region. The first and... Agent: Marger Johnson & Mccollom, P.C.
20090147584 - Nand architecture memory devices and operation: Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20090147585 - Flexible word line boosting across vcc supply: Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up... Agent: Amin, Turocy & Calvin, LLP
20090147570 - Use of 8-bit or higher a/d for nand cell value: A system and method, including computer software, for storing digital information uses multiple NAND flash memory cells. Each memory cell is adapted to receive charge during a write operation to an analog voltage that corresponds to a data value having a binary representation of more than 4 bits. An analog-to-digital... Agent: Fish & Richardson P.C.
20090147586 - Non-volatile memory and method with improved sensing having bit-line lockout control: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090147587 - Circuit pre-charge to sense a memory line: Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement... Agent: Amin, Turocy & Calvin, LLP
20090147588 - Memory devices having reduced word line current and method of operating and manufacturing the same: There is provided a memory array and methods for manufacturing the same. In one embodiment, there is provided a string comprising a plurality of transistors. Each of the plurality of transistors includes: a charge storage node, a control gate, and at least one resistive element coupled to the string. The... Agent: Fletcher Yoder (micron Technology, Inc.)
20090147589 - Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time,... Agent: Amin, Turocy & Calvin, LLP
20090147590 - Apparatus for reducing leakage in global bit-line architectures: A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively... Agent: Cantor Colburn LLP - IBM Research Triangle Park
20090147592 - Memory circuit with decoupled read and write bit lines and improved write stability: In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line... Agent: Ryan, Mason & Lewis, LLP
20090147591 - Memory circuit with high reading speed and low switching noise: A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an... Agent: Volpe And Koenig, P.C.
20090147593 - Output driver of semiconductor memory apparatus: An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal... Agent: Baker & Mckenzie LLP Patent Department
20090147595 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090147594 - Voltage regulator for semiconductor memory: A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a... Agent: Jianq Chyun Intellectual Property Office
20090147596 - Method to improve the write speed for memory products: A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write... Agent: Saile Ackerman LLC
20090147597 - Semiconductor memory device: A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090147600 - Apparatus and method for repairing a semiconductor memory: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores... Agent: Trask Britt, P.C./ Micron Technology
20090147599 - Column/row redundancy architecture using latches programmed from a look up table: A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in... Agent: Dickstein Shapiro LLP
20090147598 - Integrated circuits and methods to compensate for defective memory in multiple layers of memory: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated... Agent: Unity Semiconductor Corporation
20090147601 - Non-volatile memory structure: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line... Agent: Rosenberg, Klein & Lee
20090147603 - Memory with low power mode for write: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode... Agent: Texas Instruments Incorporated
20090147602 - Sense amplifier for controlling flip error and drving method thereof: A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit line from a sense amplifying... Agent: Ladas & Parry LLP
20090147604 - Sense amplifier and driving method thereof, and semiconductor memory device having the sense amplifier: The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive... Agent: Ladas & Parry LLP
20090147605 - Novel high performance, area efficient direct bitline sensing circuit: In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference... Agent: Texas Instruments Incorporated
20090147606 - Memory refresh method and apparatus: An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits... Agent: Coats & Bennett/qimonda
20090147608 - Power management control and controlling memory refresh operations: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed... Agent: Thomas J. D'amico Dickstein Shapiro Morin & Oshinsky LLP
20090147607 - Random access memory and data refreshing method thereof: A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating... Agent: Jianq Chyun Intellectual Property Office
20090147609 - Techniques for configuring memory systems using accurate operating parameters: Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating... Agent: Fletcher Yoder (micron Technology, Inc.)
20090147611 - Bulk voltage detector: A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled... Agent: Baker & Mckenzie LLP Patent Department
20090147610 - Semiconductor device: A semiconductor device includes first and second memory circuits that are disposed in different power source blocks and operate in synchronization with a clock, first and second delay circuits that are connected between output terminals of one memory circuits and input terminals of the other memory circuits, and a determination... Agent: Arent Fox LLP
20090147612 - System for controlling memory power consumption in integrated devices: A method for reducing power consumption in integrated devices is provided. The method comprising: locating a plurality of unused blocks of memory and a plurality of used blocks of memory in a memory device tlhrough a tracking mechanism; performing a refresh operation on the plurality of used blocks of memory... Agent: Cantor Colburn LLP - IBM Tuscon Division
20090147613 - Device for protecting sram data: A device for protecting data stored in a static random access memory (SRAM) is provided. More particularly, a device for protecting SRAM data including an SRAM data erasing circuit, which erases memory stored in an SRAM at once when illegal separation from a system is detected. The device for protecting... Agent: Ladas & Parry LLP
20090147614 - Semiconductor memory apparatus: A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first... Agent: Baker & Mckenzie LLP Patent Department06/04/2009 > patent applications in patent subcategories.
20090141528 - Apparatus and method for implementing enhanced content addressable memory performance capability: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of... Agent: Cantor Colburn LLP-ibm Burlington
20090141527 - Apparatus and method for implementing matrix-based search capability in content addressable memory devices: A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array,... Agent: Cantor Colburn LLP-ibm Burlington
20090141531 - Associative memory and searching system using the same: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals... Agent: Foley & Lardner LLP
20090141529 - Design structure for implementing matrix-based search capability in content addressable memory devices: A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data... Agent: Cantor Colburn LLP-ibm Burlington
20090141530 - Structure for implementing enhanced content addressable memory performance capability: A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and... Agent: Cantor Colburn LLP-ibm Burlington
20090141532 - Semiconductor memory device: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090141534 - Detection apparatus and method for sequentially programming memory: A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory... Agent: Quintero Law Office, PC
20090141533 - Metal gate compatible electrical antifuse: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack.... Agent: Scully, Scott, Murphy & Presser, P.C.
20090141535 - Methods involving memory with high dielectric constant antifuses adapted for use at low voltage: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which... Agent: Dugan & Dugan, PC
20090141537 - Apparatus and method for implementing memory array device with built in computational capability: A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected... Agent: Cantor Colburn LLP-ibm Burlington
20090141536 - Structure for a configurable sram system and method: A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM... Agent: Downs Rachlin Martin PLLC
20090141538 - Voltage controlled static random access memory: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory... Agent: Downs Rachlin Martin PLLC
20090141539 - Radiation tolerant sram bit: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter.... Agent: Lewis And Roca LLP
20090141540 - Magnetic random access memory: MRAM includes a first wiring, a second wiring, and a memory cell. The first wiring extends to a first direction, and the second wiring extends to a second direction. The memory cell includes a free magnetic layer in which a plurality of magnetic layers coupled anti-ferromagnetically through non-magnetic layers are... Agent: Young & Thompson
20090141543 - Magnetic random access memory, manufacturing method and programming method thereof: A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090141541 - Magnetoresistive memory elements with separate read and write current paths: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer.... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20090141544 - Mram and operation method of the same: An operation method of an MRAM of the present invention is an operation method of the MRAM in which a data write operation is carried out in a toggle write. The operation method of the present invention includes: (A) reading a data from a data cell by using a reference... Agent: Mcginn Intellectual Property Law Group, PLLC
20090141542 - Mram design with local write conductors of reduced cross-sectional area: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a... Agent: Hahn And Moodley, LLP
20090141548 - Memory and method for dissipation caused by current leakage: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.... Agent: Quintero Law Office, PC
20090141546 - Method of operating a phase-change memory device: A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.... Agent: Harness, Dickey & Pierce, P.L.C
20090141547 - Non-volatile memory devices and methods of fabricating and using the same: Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode... Agent: Harness, Dickey & Pierce, P.L.C
20090141545 - Planar third dimensional memory with multi-port access: Embodiments of the invention relate generally to a planar third dimensional memory with multi-port access, the planar third dimensional memory including memory planes composed of a plurality of memory layers. The memory layers can include non-volatile memory elements. The planar third dimensional memory can also include insulation layers, each being... Agent: Unity Semiconductor Corporation
20090141549 - Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such... Agent: Harness, Dickey & Pierce, P.L.C
20090141550 - Memory array having a programmable word length, and method of operating same: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body... Agent: Neil Steinberg
20090141552 - Memory system: A memory system includes a nonvolatile memory including a plurality of memory cells, each memory cell being configured to store n levels (n is a natural number of not less than 3) in accordance with a threshold voltage, and a converter which encodes input data in the form of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090141553 - Semiconductor storage device provided with memory cell having charge accumulation layer and control gate: A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090141554 - Memory device having small array area: Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A... Agent: Fish & Richardson P.C.
20090141555 - Method of programming and erasing a p-channel be-sonos nand flash memory: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090141556 - Method of verifying programming of a nonvolatile memory device: A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first... Agent: Townsend And Townsend And Crew, LLP
20090141557 - Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090141551 - Method for performing erasing operation in nonvolatile memory device: A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected... Agent: Townsend And Townsend And Crew, LLP
20090141558 - Sensing memory cells: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at... Agent: Brooks, Cameron & Huebsch , PLLC
20090141560 - Flash memory device and programming method thereof: A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and... Agent: Townsend And Townsend And Crew, LLP
20090141561 - Method of operating a non-volatile memory device: In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.... Agent: Townsend And Townsend And Crew, LLP
20090141559 - Verifying an erase threshold in a memory device: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well... Agent: Leffert Jay & Polglaze, P.A.
20090141563 - Method for operating a non-volatile charge-trapping memory device and method for determining programming/erase conditions: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20090141562 - Non-volatile memory device, methods of fabricating and operating the same: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through... Agent: F. Chau & Associates, LLC
20090141565 - Semiconductor storage device: A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and... Agent: Mcdermott Will & Emery LLP
20090141564 - Memory register definition systems and methods: Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address... Agent: Schwegman, Lundberg & Woessner/micron
20090141567 - Semiconductor device having memory array, method of writing, and systems associated therewith: In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that... Agent: Harness, Dickey & Pierce, P.L.C
20090141566 - Structure for implementing memory array device with built in computation capability: A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for... Agent: Cantor Colburn LLP-ibm Burlington
20090141568 - No-disturb bit line write for improving speed of edram: A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and... Agent: Slater & Matsil, L.L.P.
20090141569 - Semiconductor memory device: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating... Agent: Mcdermott Will & Emery LLP
20090141570 - Controlling global bit line pre-charge time for high speed edram: A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the... Agent: Slater & Matsil, L.L.P.
20090141571 - Method and apparatus for initialization of read latency tracking circuit in high-speed dram: A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is... Agent: Jones Day
20090141572 - Voltage control apparatus and method of controlling voltage using the same: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either... Agent: Venable LLP
20090141573 - System and method for better testability of otp memory: A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of... Agent: K & L Gates LLP
20090141574 - Memory accessing circuit and method: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit comprises a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for... Agent: Bacon & Thomas, PLLC
20090141575 - Method and apparatus for idle cycle refresh request in dram: Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence... Agent: Ryan, Mason & Lewis, LLP
20090141576 - Method of refreshing data in a storage location: An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090141577 - Anti-fuse repair control circuit and semiconductor device including dram having the same: In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal... Agent: Ladas & Parry LLP
20090141578 - Fuse box and semiconductor memory device including the same: A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the... Agent: F. Chau & Associates, LLC
20090141579 - Power up/down sequence scheme for memory devices: A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been... Agent: K & L Gates LLP
20090141580 - Reduced leakage driver circuit and memory device employing same: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected... Agent: Ryan, Mason & Lewis, LLP
20090141581 - Semiconductor memory arrangement and system: A semiconductor memory arrangement includes a control device with a first port and a second port, the first and second port being adapted to receive command and address signals, a first buffer device being coupled to the first port, a second buffer device being coupled to the second port and... Agent: Slater & Matsil, L.L.P.
20090141582 - Method for recording data using non-volatile memory and electronic apparatus thereof: A method for recording data using a non-volatile memory and an electronic apparatus thereof are provided. In the present method, a set of input data is provided. Then, a data structure of the input data is transformed into a bitmapping data structure. Afterwards, the input data is written sequentially into... Agent: Jianq Chyun Intellectual Property OfficePrevious industry: Electric power conversion systems
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