|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
05/2009 | Recent | 14: | | | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval May archived by USPTO category 05/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/28/2009 > patent applications in patent subcategories. archived by USPTO category
20090135637 - Resistance change memory device: A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090135638 - Semiconductor memory device capable of identifying a plurality of memory chips stacked in the same package: A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090135639 - Semiconductor storage device: In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regionsOOD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of... Agent: Mcdermott Will & Emery LLP
20090135640 - Electromigration-programmable semiconductor device with bidirectional resistance change: An electromigration-programmable semiconductor device may be programmed to increase the resistance or to decrease the resistance by selecting the amount of current passed through the electromigration-programmable semiconductor device. The electromigration-programmable semiconductor device comprises an anode, a cathode, and a link, each having a semiconductor portion and a metal semiconductor alloy... Agent: Scully, Scott, Murphy & Presser, P.C.
20090135642 - Resistive memory devices including selected reference memory cells operating responsive to read operations: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.... Agent: Myers Bigel Sibley & Sajovec
20090135641 - Semiconductor memory device: A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit... Agent: Nixon & Vanderhye, PC
20090135643 - Seu hardening circuit and method: An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a... Agent: Texas Instruments Incorporated
20090135644 - Magnetoresistive element and magnetic random access memory: A magnetoresistive element includes a free layer a pinned layer; a nonmagnetic layer interposed between the free layer and the pinned layer; and two magnetic layers arranged adjacent to the free layer on an opposite side to the pinned layer. The free layer includes: a first magnetic layer, a second... Agent: Mcginn Intellectual Property Law Group, PLLC
20090135645 - Data programming circuits and memory programming methods: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the... Agent: Wang Law Firm, Inc.
20090135647 - Nand flash memory devices having shielding lines between wordlines and selection lines: A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program... Agent: Myers Bigel Sibley & Sajovec
20090135648 - Semiconductor memory device for storing multilevel data: In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090135649 - Scalable electrically eraseable and programmable memory (eeprom) cell array: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20090135650 - Compensation of back pattern effect in a memory device: In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090135651 - Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier: In a wire pair 120 including a first signal line 120a and a second signal line 120b, the first signal line 120a and the second signal line 120b are laid out so that they have substantially the same stray capacitance. Two output terminals of a measured device 1000 and an... Agent: Mcdermott Will & Emery LLP
20090135655 - Embedded flash memory devices on soi substrates and methods of manufacture thereof: Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer... Agent: Slater & Matsil LLP
20090135654 - Memory read methods, apparatus, and systems: Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number... Agent: Schwegman, Lundberg & Woessner/micron
20090135652 - Method for extracting the distribution of charge stored in a semiconductor device: The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20090135653 - Method for performing operations on a memory cell: A method for performing operations on a memory cell is disclosed. The memory cell includes a substrate, a first doping region and a second doping region. The first doping region and the second doping region are formed on the substrate with a channel region therebetween. A dielectric layer is formed... Agent: Jianq Chyun Intellectual Property Office
20090135656 - Non-volatile semiconductor memory device with dummy cells and method of programming the same: A nonvolatile semiconductor memory device includes a memory cell array, an erase controller and a dummy cell controller. The memory cell array includes multiple cell strings, each including at least two dummy cells having different threshold voltages and normal memory cells. The erase controller performs, in cell block units, an... Agent: Volentine & Whitt PLLC
20090135646 - Operation sequence and commands for measuring threshold voltage distribution in memory: A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using... Agent: Vierra Magen/sandisk Corporation
20090135657 - Semiconductor memory: A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090135658 - Flash memory device and read method thereof: A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection... Agent: Lee & Morse, P.C.
20090135659 - Room temperature drift suppression via soft program after erase: Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and... Agent: Amin, Turocy & Calvin, LLP
20090135660 - Apparatus, memory device and method of improving redundancy: An apparatus includes a memory device. The memory device includes a first memory cell column which includes a plurality of first memory cells, a second memory cell column including a plurality of second memory cells, a detector which detects a delay of a memory cell signal outputted from at least... Agent: Mcginn Intellectual Property Law Group, PLLC
20090135661 - Controlling power supply to memory cells: A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of... Agent: Nixon & Vanderhye, PC
20090135662 - Memory device: A memory device includes a power supply line, a memory cell, a memory cell power supply node provided between the memory cell and the power supply line, a first voltage generating circuit coupled to the memory cell power supply node for supplying the memory cell power supply node with a... Agent: Arent Fox LLP
20090135663 - Memory device and method of operating such a memory device: A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply... Agent: Nixon & Vanderhye, PC
20090135664 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman05/21/2009 > patent applications in patent subcategories. archived by USPTO category
20090129135 - Semiconductor devices having sense amplifiers and electronic systems employing the same: A semiconductor device having sense amplifiers and an electronic system employing the same are provided. The semiconductor device includes first sense amplifier blocks arranged in a row direction on a substrate and spaced apart from each other by a first distance. A second sense amplifier block spaced apart from the... Agent: Harness, Dickey & Pierce, P.L.C
20090129136 - Semiconductor memory device: s
20090129137 - Semiconductor storage device: A semiconductor storage device includes a memory array compartmentalized into first and second regions alternately arranged. The second regions are formed by odd and even columns alternately arranged. The semiconductor storage device includes: a memory mat array arranged in each first region; a sense amp array arranged in each second... Agent: Foley And Lardner LLP Suite 500
20090129138 - Semiconductor integrated circuit: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second... Agent: Steptoe & Johnson LLP
20090129139 - Nano-electro-mechanical memory cells and devices: A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and... Agent: John P. O'banion O'banion & Ritchey LLP
20090129140 - Nonvolatile semiconductor storage device and method for operating same: A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell... Agent: Nixon & Vanderhye, PC
20090129141 - Semiconductor memory device: A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129142 - Semiconductor memory: A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved.... Agent: Miles & Stockbridge PC
20090129143 - Spin transfer mram device with separated cpp assisted writing: A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in... Agent: Saile Ackerman LLC
20090129144 - Phase change memory and method discharging bitline: Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory... Agent: Volentine & Whitt PLLC
20090129145 - Memory cell array comprising floating body memory cells: A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically... Agent: Edell, Shapiro & Finnan, LLC
20090129146 - Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090129153 - M+n bit programming and m+l bit read for m bit memory cells: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.
20090129150 - Method for operating memory: A memory operating method includes the following steps. First, a memory including a charge storage structure is provided. Next, first type charges are injected into the charge storage structure such that a threshold level of the memory is higher than an erase level. Then, second type charges are injected into... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090129156 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129157 - Nonvolatile semiconductor memory device and method for controlling threshold value in nonvolatile semiconductor memory device: A method for controlling a threshold value in a nonvolatile semiconductor memory device, includes: performing writing at least once on at least one of the memory cells to be adjusted to a state other than an erased state with an applied voltage that does not cause excess writing, with verify... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129149 - Nonvolatile semiconductor memory device for writing multivalued data: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to... Agent: Myers Bigel Sibley & Sajovec
20090129158 - Nonvolatile semiconductor memory device including nand-type flash memory and the like: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129155 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129152 - Program and read method for mlc: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
20090129151 - Read method for mlc: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A.
20090129159 - Read operation for non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20090129160 - Read operation for non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20090129154 - Semiconductor memory device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129161 - Nonvolatile memory devices that support virtual page storage using odd-state memory cells: A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of... Agent: Myers Bigel Sibley & Sajovec
20090129162 - Method of making a non-volatile memory (nvm) cell structure and program biasing techniques for the nvm cell structure: A method of making a non-volatile memory (NVM) cell structure comprises the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node... Agent: National Semiconductor Corporation Counsels For Dergosits & Noah LLP
20090129163 - System, method, and computer program product for increasing a lifetime of a plurality of blocks of memory: A system, method, and computer program product are provided for increasing a lifetime of a plurality of blocks of memory. In operation, at least one factor that affects a lifetime of a plurality of blocks of memory is identified. Additionally, the plurality of blocks to write is selected, based on... Agent: Zilka-kotab, PC
20090129164 - Semiconductor non-volatile memory: A semiconductor non-volatile memory, wherein a memory cell can be read accurately without having to discharge bit lines before the read operation. When reading a memory cell, the first bit line connected to the drain thereof is connected to the voltage source to receive a predetermined voltage, and the second... Agent: Mcdermott Will & Emery LLP
20090129165 - Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which... Agent: Myers Bigel Sibley & Sajovec
20090129166 - Method, circuit and system for sensing a cell in a non-volatile memory array: Disclosed is a method, circuit and system for evaluating the status of a data storage area in a non-volatile memory cell within a non-volatile memory cell array. According to some embodiments of the present invention, leakage current in at least one other cell in proximity with the cell being evaluated... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090129167 - Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090129168 - Method of operating a flash memeory device: A method of operating a flash memory device wherein the width of threshold voltage distribution of memory cells is adjusted by setting different conditions of a program operation in accordance with levels of threshold voltages of the memory cells. As a result, width of the threshold voltage distribution of memory... Agent: Lowe Hauptman Ham & Berner, LLP
20090129147 - Multiple programming of spare memory region for nonvolatile memory: Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090129148 - Semiconductor memory: A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090129169 - Method and apparatus for reading data from flash memory: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a... Agent: Knobbe Martens Olson & Bear LLP
20090129170 - Method of programming non-volatile memory device: A method of programming a non-volatile memory device includes, a bit line, to which a program-inhibited cell is connected, being precharged. After precharging the bit line, a program voltage is applied to a first word line selected for program. When a memory cell connected to a second word line, which... Agent: Lowe Hauptman Ham & Berner, LLP
20090129171 - Nonvolatile semiconductor memory and method of driving the same: It is an object of the present invention to provide a nonvolatile semiconductor memory including memory cells using side walls of island semiconductor layers which avoid lowing of the writing speed and the reading speed. In the nonvolatile semiconductor memory having the nonvolatile semiconductor memory cells each having an island... Agent: Brinks Hofer Gilson & Lione
20090129172 - High reliable and low power static random access memory: Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in... Agent: Amin, Turocy & Calvin, LLP
20090129173 - Semiconductor integrated circuit device: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and... Agent: Miles & Stockbridge PC
20090129174 - Multi-port thin-film memory devices: In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first port to write data to a storage element;... Agent: Tran & Associates
20090129175 - Semiconductor storage device: A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit... Agent: Young & Thompson
20090129176 - High speed array pipeline architecture: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being... Agent: Jones Day
20090129177 - Sensing of memory cells in a solid state memory device by fixed discharge of a bit line: In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit... Agent: Leffert Jay & Polglaze, P.A.
20090129178 - Integrated circuit memory device having delayed write timing based on read response time: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the... Agent: Morgan Lewis & Bockius LLP/rambus Inc.
20090129180 - Apparatus for sensing data of semiconductor integrated circuit: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP
20090129179 - Variable delay circuit, memory control circuit, delay amount setting apparatus, delay amount setting method and computer-readable recording medium in which delay amount setting program is recorded: A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than... Agent: Staas & Halsey LLP
20090129182 - Memory module with failed memory cell repair function and method thereof: A memory module with failed memory cell repair function and method thereof are provided. The memory module comprises a programming interface, a mode register, a control signal generator, a fuse unit, a main memory array and a redundant memory array, wherein the programming interface is defined by selecting pins from... Agent: Rosenberg, Klein & Lee
20090129181 - System and method for implementing row redundancy with reduced access time and reduced device area: A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main subarrays including a set of support circuitry associated therewith. A discrete, redundant subarray is associated with the... Agent: Cantor Colburn LLP-ibm Burlington
20090129183 - Method and device for high speed testing of an integrated circuit: An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first memory circuit within the integrated circuit, at a... Agent: Freescale Semiconductor, Inc. Law Department
20090129184 - Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices: A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the... Agent: Smart & Biggar
20090129186 - Self-diagnostic scheme for detecting errors: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090129185 - Semiconductor circuits capable of self detecting defects: A digital circuit and a method for operating the same. The digital circuit includes (a) M×N regular cells electrically arranged in M rows and N columns, (b) N reference cells corresponding one-to-one to the N columns, and (c) N comparing circuits corresponding one-to-one to the N columns. Each regular cell... Agent: Schmeiser, Olsen & Watts
20090129187 - Internal voltage generator: An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by... Agent: Mcdermott Will & Emery LLP
20090129188 - Devices and methods for a threshold voltage difference compensated sense amplifier: Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090129189 - Method and apparatus for monitoring a memory device: A memory device comprising at least a plurality of memory cells and a memory control unit to read and write user data to said memory cells is provided. The memory device comprises further a monitoring unit for retrieving a plurality of data concerning the memory device and a comparing unit.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090129190 - Driving a memory matrix of resistance hysteresis elements: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090129192 - Design structure for low overhead switched header power savings apparatus: A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting... Agent: Cantor Colburn LLP-ibm Burlington
20090129191 - Structure for sram voltage control for improved operational margins: A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns... Agent: International Business Machines Corporation Dept. 18g
20090129193 - Energy efficient storage device using per-element selectable power supply voltages: An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.
20090129194 - Access collision within a multiport memory: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and... Agent: Nixon & Vanderhye, PC
20090129195 - Balanced and bi-directional bit line paths for memory arrays with programmable memory cells: Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090129196 - Semiconductor integrated circuit: A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal.... Agent: Young & Thompson05/14/2009 > patent applications in patent subcategories. archived by USPTO category
20090122587 - Memory system and data transmission method: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory... Agent: Scully Scott Murphy & Presser, PC
20090122586 - Method and apparatus for an integrated circuit with programmable memory cells, data system: A method and apparatus for an integrated circuit with programmable memory cells which are arranged between a first and a second conductor for supplying first and second voltage is provided. A control circuit is arranged between the memory cells and the second conductor. The control circuit controls a change time... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090122588 - Phase change memory cell including a thermal protect bottom electrode and manufacturing methods: Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090122589 - Electrical fuse self test and repair: A circuit for testing and repairing a fuse device having a plurality of fuse units and being able to serially input and output data is disclosed, the circuit comprises a first multiplexer configured to select either a true or an inverted data for being stored in the fuse device, a... Agent: K & L Gates LLP
20090122590 - Control of a memory matrix with resistance hysteresis elements: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090122592 - Non-volatile memory device and method of reading data therefrom: The present invention provides a method of reading data from a non-volatile memory device including word lines and bit lines that intersect each other and electrically rewritable memory cells that are arranged at intersections of the word lines and the bit lines and that respectively have variable resistive elements nonvolatily... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090122591 - Sense amplifier biasing method and apparatus: A memory device comprises sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to... Agent: Coats & Bennett/qimonda
20090122593 - Write driver circuit for phase-change memory, memory including the same, and associated methods: A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current... Agent: Lee & Morse, P.C.
20090122594 - Semiconductor memory device: A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power... Agent: Mannava & Kang, P.C.
20090122595 - Semiconductor integrated circuit: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance... Agent: Young & Thompson
20090122597 - Magnetic random access memory: An MRAM is provided with a memory main body (2) having at least one cell array, and a magnetic field detecting section (4) which detects a magnetic field in the vicinity of the memory main body (2) and outputs the detection signal to the memory main body (2). In the... Agent: Young & Thompson
20090122598 - Resistance change memory device: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090122596 - Semconductor memory device and method of programming the same: Provided are a semiconductor memory device and a method of programming the same. The semiconductor memory device includes a mode input value generating unit and a logic operating unit. The mode input value generating unit changes a connection state between input values of a current driving circuit so as to... Agent: Harness, Dickey & Pierce, P.L.C
20090122600 - Nonvolatile memory using resistance material: A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell... Agent: F. Chau & Associates, LLC
20090122601 - Power supplying circuit and phase-change random access memory including the same: Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured... Agent: Volentine & Whitt PLLC
20090122602 - Semiconductor integrated circuit device: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable... Agent: Miles & Stockbridge PC
20090122599 - Writing system and method for phase change momory: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090122607 - Erase operation in a flash drive memory: A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090122606 - Flash memory device having multi-level cell and reading and programming method thereof: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and... Agent: Marger Johnson & Mccollom, P.C.
20090122603 - Integrated circuit embedded with non-volatile programmable memory having variable coupling: A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state... Agent: J. Nicholas Gross, Attorney
20090122605 - Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling: A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through... Agent: J. Nicholas Gross, Attorney
20090122608 - Memory voltage cycle adjustment: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an... Agent: Brooks, Cameron & Huebsch , PLLC
20090122604 - Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data: A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through... Agent: J. Nicholas Gross, Attorney
20090122609 - Semiconductor device: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090122610 - Operation of a non-volatile memory array: A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090122611 - Nonvolatile semiconductor memory device and method of driving the same: This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090122612 - Wired-or typed page buffer having cache function in a nonvolatile memory device and related method of programming: Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory... Agent: Volentine & Whitt PLLC
20090122613 - Non-volatile memory device and method of operating the same: A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of... Agent: Harness, Dickey & Pierce, P.L.C
20090122615 - Non-volatile memory device and method of operating the same: Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile... Agent: Townsend And Townsend And Crew, LLP
20090122614 - Single poly eeprom allowing continuous adjustment of its threshold voltage: A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read... Agent: Texas Instruments Incorporated
20090122616 - Non-volatile memory device and method of controlling a bulk voltage thereof: A threshold voltage of a non-volatile memory device is compensated by a voltage supplier and a controller. The voltage supplier supplies a set voltage to a bulk of a memory cell array, including memory cells, at the time of a read operation of the memory cells. The controller controls the... Agent: Townsend And Townsend And Crew, LLP
20090122617 - Soft programming method of non-volatile memory device: A non-volatile memory device includes a first cell group including memory cells other than memory cells adjacent to a drain select transistor in a block, and a second cell group including the memory cells adjacent to the drain select transistor in the block. An erase operation is performed on the... Agent: Townsend And Townsend And Crew, LLP
20090122618 - Method for programming and erasing an array of nmos eeprom cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits: A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments... Agent: Attention Of : Paul N. Katz. Baker Botts L.L.P.
20090122619 - Enhanced dram with embedded registers: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20090122621 - Circuit for controlling signal line transmitting data and method of controlling the same: A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a... Agent: Baker & Mckenzie LLP Patent Department
20090122622 - Level shifter with reduced leakage current and block driver for nonvolatile semiconductor memory device: A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted... Agent: Volentine & Whitt PLLC
20090122620 - Systems and methods for low power, high yield memory: A system for low power, high yield memory is described. The system includes a memory cell configured to receive a memory supply voltage. The system further includes a memory supply voltage control circuit configured to modify the memory supply voltage from a first memory supply voltage level to a second... Agent: Qualcomm Incorporated
20090122623 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling... Agent: Mcdermott Will & Emery LLP
20090122624 - Semiconductor memory device: A word line activation circuit having a temporary memory circuit for storing word line inactivation information for inactivating a word line of a defective memory cell, and an inactivation address sensing circuit for determining whether or not a redundant memory cell is to be used in accordance with the word... Agent: Mcdermott Will & Emery LLP
20090122625 - Semiconductor memory device having test circuit: A semiconductor memory device including a test circuit capable of reducing test time includes a test circuit for generating leakage current in the semiconductor memory device in a standby state in response to a test mode signal and a standby signal that provides standby state information of the semiconductor memory... Agent: Baker & Mckenzie LLP Patent Department
20090122628 - Device with precharge/homogenize circuit: A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching... Agent: Dicke, Billig & Czaja
20090122627 - Memory with programmable strides: Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20090122626 - Method and apparatus for selectable guaranteed write through: A device maintains a state of a precharged dot line that is periodically precharged by a global precharge signal. The device includes a data input signal that can have a selected one of a first value and a second value. The first value is a value that would be reflected... Agent: Robert R. Williams IBM Corporation, Dept. 917
20090122629 - Sequential access memory method: A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a... Agent: Trask Britt, P.C./ Micron Technology
20090122630 - Semiconductor storage device and method of controlling the same: An exemplary aspect of the present invention is a sense amplifier having a power supply voltage of 1.2 V or lower and amplifying a potential difference between a bit line pair, a first transistor supplying the power supply voltage to the sense amplifier, a second transistor supplying a low potential... Agent: Young & Thompson
20090122631 - Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090122632 - Stack bank type semiconductor memory apparatus capable of improving alignment margin: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control... Agent: Baker & Mckenzie LLP Patent Department
20090122634 - Circuit and method for supplying a reference voltage in semiconductor memory apparatus: A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator... Agent: Baker & Mckenzie LLP Patent Department
20090122633 - Integrated circuit with controlled power supply: An integrated circuit comprises a main circuit, a supply circuit configured to provide a supply current to the main circuit, a sensing circuit configured to sense the supply current, and a control circuit configured to control the supply circuit based on the sensed current.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090122635 - Selective edge phase mixing: Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may... Agent: Schwegman, Lundberg & Woessner/micron05/07/2009 > patent applications in patent subcategories. archived by USPTO category
20090116270 - Floating body memory cell system and method of manufacture: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby... Agent: Dugan & Dugan, PC
20090116271 - Memory: A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are... Agent: Mcdermott Will & Emery LLP
20090116272 - Non-volatile memory device including diode-storage node and cross-point memory array including the non-volatile memory device: Provided are a non-volatile memory device and a cross-point memory array including the same which have a diode characteristic enabling the non-volatile memory device and the cross-point memory array including the same to operate in a simple structure, without requiring a switching device separately formed so as to embody a... Agent: Harness, Dickey & Pierce, P.L.C
20090116273 - Semiconductor memory device: This disclosure concerns a memory including: unit cells having ferroelectric capacitors and cell transistors; two depletion transistors and two enhancement transistors serially connected between two adjacent unit series configurations configured by serially connecting the unit cells; four selective lines respectively connected to the gates of the two enhancement transistors and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090116274 - Diode-less array for one-time programmable memory: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent... Agent: Jianq Chyun Intellectual Property Office
20090116275 - Conventionally printable non-volatile passive memory element and method of making thereof: A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems... Agent: Leydig Voit & Mayer, Ltd
20090116276 - Memory device, data recording method and ic tag: A memory device of the present invention is characterized by a memory device for storing information by making use of molecular alignment of a liquid crystal compound in a liquid crystalline state formed by spot irradiation with a laser beam to carry out a selective heat treatment on an electroconductive... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090116277 - Nano-electronic memory array: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assembling one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.... Agent: Bao Q. Tran
20090116278 - Semiconductor device: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode... Agent: Cook Alex Ltd
20090116279 - Semiconductor integrated circuit device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit... Agent: Stanley P. Fisher Reed Smith LLP
20090116280 - Accessing a phase change memory: A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient charge for an ensuing access. When a memory cell is accessed, charge stored on the capacitor is discharged through the phase change memory, supplying... Agent: Ovonyx, Inc
20090116281 - Reading phase change memories: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to... Agent: Trop, Pruner & Hu, P.C.
20090116282 - Semiconductor integrated circuit device: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090116284 - Memory apparatus and method thereof for operating memory: A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region... Agent: J C Patents, Inc.
20090116285 - Nonvolatile memory device and reading method thereof: A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each... Agent: Lowe Hauptman Ham & Berner, LLP
20090116288 - Method, device and apparatus for accessing a non-volatile memory array: A non-volatile memory (NVM) having an array of memory cells and a unidirectional multiplexer (UMUX), the UMUX may be comprised of two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch a supply... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090116286 - Operation methods for memory cell and array for reducing punch through leakage: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain... Agent: Townsend And Townsend And Crew, LLP
20090116287 - Operation methods for memory cell and array thereof immune to punchthrough leakage: An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a... Agent: Townsend And Townsend And Crew, LLP
20090116289 - Decoding system capable of reducing sector select area overhead for flash memory: Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods arc... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC
20090116290 - Methods and apparatuses relating to automatic cell threshold voltage measurement: Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a pre-charge bit line reference circuit. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely,... Agent: Trask Britt, P.C./ Micron Technology
20090116291 - Method of making integrated circuit embedded with non-volatile one-time - programmable and multiple-time programmable memory: A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device.... Agent: J. Nicholas Gross, Attorney
20090116283 - Controlling a memory device responsive to degradation: Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090116293 - Memory and method for charging a word line thereof: A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line... Agent: Bacon & Thomas, PLLC
20090116292 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. The memory cell unit includes a plurality of memory cells connected in series. Each of the memory cells includes a charge accumulation layer and a control gate. The word lines are connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090116295 - Method of operating integrated circuit embedded with non-volatile one-time - programmable and multiple-time programmable memory: A programmable non-volatile device is operated using a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The... Agent: J. Nicholas Gross, Attorney
20090116294 - Method of programming cell in memory and memory apparatus utilizing the method: A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells... Agent: J C Patents, Inc.
20090116296 - Flash memory device applying erase voltage: A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate... Agent: Volentine & Whitt PLLC
20090116297 - Redundancy program circuit and methods thereof: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control... Agent: Harness, Dickey & Pierce, P.L.C
20090116298 - Apparatus for implementing sram cell write performance evaluation: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and... Agent: Ibm Corporation RochesterIPLaw Dept 917
20090116301 - Internal data comparison for memory testing: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sensed data value to an... Agent: Leffert Jay & Polglaze, P.A.
20090116300 - Semiconductor memory device: A semiconductor memory device includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the semiconductor memory device,... Agent: Mannava & Kang, P.C.
20090116299 - Semiconductor memory device and method for operating the same: A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting CAS latency information on an external clock count value. The semiconductor memory device includes... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116302 - Semiconductor memory device: A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116303 - Semiconductor memory device: A semiconductor memory device can generate an under_drive voltage that maintains a predetermined level stably even in case of a change in the operation mode of the semiconductor memory device or the level of an external power supply voltage. The semiconductor memory device, which includes an external power supply voltage... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116306 - Delay locked loop circuit of semiconductor device: A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output... Agent: Mannava & Kang, P.C.
20090116305 - Word line driver and semiconductor memory device having the same: A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line... Agent: Volentine & Whitt PLLC
20090116304 - Wordline driving circuit of semiconductor memory device: Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116307 - Level shifter for boosting wordline voltage and memory cell performance: A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including... Agent: Keusey, Tutunjian & Bitetto, P.C.
20090116308 - Memory device and method of operating such a memory device: A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated... Agent: Nixon & Vanderhye, PC
20090116309 - Semiconductor device: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read... Agent: Miles & Stockbridge PC
20090116310 - Method and apparatus for write enable and inhibit for high density spin torque three dimensional (3d) memory arrays: A method and apparatus for write enable and write inhibit for high density spin torque three dimensional (3D) memory arrays.... Agent: Bracewell & Giuliani LLP
20090116311 - Semiconductor memory device: A semiconductor memory device includes data lines for transmitting one of data and a training data pattern, wherein the training data pattern is preset to a specific pattern, and training drivers for transmitting the training data pattern to the data lines in response to a training control signal which is... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116313 - Data output control circuit: A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to... Agent: Mannava & Kang, P.C.
20090116315 - Semiconductor memory device and method for operating the same: A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is... Agent: Mannava & Kang, P.C.
20090116314 - Semiconductor memory device and method of operating the same: A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling... Agent: Mannava & Kang, P.C.
20090116312 - Storage array including a local clock buffer with programmable timing: A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.
20090116316 - Semiconductor device and semiconductor memory device: Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.... Agent: Mannava & Kang, P.C.
20090116317 - Block repair apparatus and method thereof: A block repair apparatus includes a plurality of cell blocks, a block repair fuse, a block isolation control unit, and a block repair selector. The block repair fuse outputs a repair signal of the plurality of cell blocks. The block isolation control unit outputs a control signal for activating the... Agent: Cooper & Dunham, LLP
20090116319 - Redundancy program circuit and methods thereof: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control... Agent: Harness, Dickey & Pierce, P.L.C
20090116318 - Semiconductor storage device: In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic... Agent: Mcdermott Will & Emery LLP
20090116321 - Apparatus and method for detection of address decoder open faults: An apparatus and method are provided for performing a test sequence to detect address decoder open faults in a memory device. The apparatus comprises base address generation circuitry for generating a plurality of base addresses, and derived address generation circuitry, responsive to a base address portion of each base address,... Agent: Nixon & Vanderhye, PC
20090116320 - Methods and apparatus for screening bit line of a sram: Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and... Agent: Gibson & Dernier L.L.P.
20090116323 - Scanned memory testing of multi-port memory arrays: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC
20090116322 - Semiconductor memory device having wafer burn-in test mode: A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116324 - Apparatus for guaranteed write through in domino read sram's: In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first... Agent: Matthew C. Zehrer IBM Corporation
20090116325 - On-chip characterization of noise-margins for memory arrays: A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.
20090116326 - Semiconductor memory device capable of performing per-bank refresh: A semiconductor memory device is provided that can support a per-bank refresh as well as an all-bank refresh and a self refresh. The semiconductor memory device includes an address counting unit for counting a bank address signal of a specific bank and row address signals of the specific bank in... Agent: Cooper & Dunham, LLP
20090116327 - Redundancy program circuit and methods thereof: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control... Agent: Harness, Dickey & Pierce, P.L.C
20090116329 - Internal-voltage generating circuit and semiconductor device including the same: An internal-voltage generating circuit includes a plurality of generating units connected in cascade, out of the plurality of generating units, a generating unit of relatively lower level is activated by an output of a generating unit of relatively higher level. According to the present invention, because the plural voltage generating... Agent: Sughrue Mion, PLLC
20090116328 - Power-off apparatus, systems, and methods: Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to... Agent: Schwegman, Lundberg & Woessner/micron
20090116330 - Semiconductor memory device using bus inversion scheme: A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090116331 - Semiconductor memory device and method for operating the same: Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the... Agent: Blakely Sokoloff Taylor & Zafman LLPPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20141218:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 0.97423 seconds