|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval April category listing, related patent applications 04/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/30/2009 > patent applications in patent subcategories.
20090109719 - System and method for providing content-addressable magnetoresistive random access memory cells: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department
20090109720 - Memory structure: The subject matter of this specification can be embodied in, among other things, a method for manufacturing and a structure of a byte-addressable electrically erasable programmable read-only memory (EEPROM). In a first aspect, a byte-addressable EEPROM integrated circuit includes isolation means, in each of a plurality of memory bytes, for... Agent: Fish & Richardson P.C.
20090109721 - Nonvolatile memory array partitioning architecture and method to utilize single level cells and multi level cells within said architecture.: An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells... Agent: Amin, Turocy & Calvin, LLP
20090109725 - Data storage in circuit elements with changed resistance: A method of storing data in an array of circuit elements, said method comprising injecting a current into selected circuit elements, said current causing a persistent change in a resistance of said selected circuit elements from a first resistance to a second higher resistance indicative of a binary data bit,... Agent: Hewlett Packard Company
20090109724 - Differential latch-based one time programmable memory: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090109723 - Quad sram based one time programmable memory: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090109722 - Reprogrammable electrical fuse: The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares... Agent: Hoffman Warnick LLC
20090109726 - Non-linear conductor memory: A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that... Agent: Goodwin Procter LLP Patent Administrator
20090109727 - Erase, programming and leakage characteristics of a resistive memory device: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality... Agent: Paul J. Winters
20090109728 - Resistance change memory device: A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0<R1<R2) are selectively set, wherein resistance gaps ΔR1(=R1−R0) and ΔR2(=R2−R1)... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090109729 - Resistance change memory device and method for erasing the same: A resistance change memory device including a cell array with memory cells arranged therein to store a resistance value as data in a non-volatile manner, and an erase circuit configured to set the memory cells in the cell array in a reset state prior to data writing, wherein the erase... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090109730 - Resistance memory element: A resistance memory element includes an elementary body and opposing electrodes separated by at least a portion of the elementary body. The elementary body is preferably made of a strontium titanate-based semiconductor ceramic expressed by the formula: (Sr1-xAx)v(Ti1-yBy)wO3 (where A represents at least one element selected from the group consisting... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP
20090109731 - Dielectric layers and memory cells including metal-doped alumina: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.... Agent: Mueting, Raasch & Gebhardt, P.A.
20090109732 - Asymmetrical sram cell with separate word lines: An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The plurality of memory... Agent: Texas Instruments Incorporated
20090109733 - Design structure for sram active write assist for improved operational margins: A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory (“SRAM”), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily raise a voltage... Agent: International Business Machines Corporation Dept. 18g
20090109735 - Design structure for initializing reference cells of a toggle switched mram device: A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference... Agent: Cantor Colburn LLP-ibm Burlington
20090109736 - Magnetic random access memory and operation method thereof: The MRAM includes: a memory cell 10 including a magnetoresistance element 1, a current supply circuit and a controller. The current supply circuit supplies, to the magnetoresistance element 1, a write current IW in a direction corresponding to data to be written into the memory cell 10. The controller controls... Agent: Young & Thompson
20090109734 - Non-volatile sram cell: Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring data from a pair of static storage nodes of the SRAM to a pair of non-volatile storage nodes when the SRAM is placed in a standby mode. The... Agent: Brooks, Cameron & Huebsch , PLLC
20090109737 - Method of restoring variable resistance memory device: Methods of programming a phase-change memory device that remedy device failure. The methods includes applying a sequence of two or more electrical energy pulses to the device, where the sequence of pulses includes positive polarity pulses and negative polarity pulses. In one method, two or more pulses of an initial... Agent: Ovonyx, Inc
20090109738 - Phase-change memory device with error correction capability: A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for... Agent: Seed Intellectual Property Law Group PLLC
20090109739 - Low current switching magnetic tunnel junction design for magnetic memory using domain wall motion: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains... Agent: Maryam Imam
20090109740 - Semiconductor device using magnetic domain wall movement: Provided may be a semiconductor device using magnetic domain wall movement. The semiconductor device may include a magnetic track having a plurality of magnetic domains and a thermal conductive insulating layer configured to contact the magnetic track. The thermal conductive insulating layer may prevent or reduce the magnetic track from... Agent: Harness, Dickey & Pierce, P.L.C
20090109741 - Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI... Agent: Hoffman Warnick LLC
20090109748 - Apparatus and method of multi-bit programming: Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2N threshold voltage states to the N-bit data; a second control unit that spaces, by any one of a first interval and a second interval, adjacent threshold voltage... Agent: Harness, Dickey & Pierce, P.L.C
20090109747 - Fractional bits in memory cells: The present disclosure includes methods, devices, modules, and systems for programming memory cells. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. The method also includes storing a charge in a cell of the set,... Agent: Brooks, Cameron & Huebsch , PLLC
20090109746 - Memory cell programming: One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least... Agent: Brooks, Cameron & Huebsch , PLLC
20090109743 - Multilevel memory cell operation: One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a... Agent: Brooks, Cameron & Huebsch , PLLC
20090109751 - Non-volatile multilevel memory cell programming: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell... Agent: Brooks, Cameron & Huebsch , PLLC
20090109745 - Non-volatile multilevel memory cells: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a... Agent: Brooks, Cameron & Huebsch , PLLC
20090109749 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090109750 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile... Agent: Law Office Of Alan W. Cannon
20090109744 - Sensing memory cells: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to the... Agent: Brooks, Cameron & Huebsch , PLLC
20090109752 - Memory cell heights: Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number of semiconductor pillars having a number of charge storage nodes, each of the charge storage nodes being associated with a respective number of pillars and separated... Agent: Brooks, Cameron & Huebsch , PLLC
20090109753 - Nonvolatile semiconductor memory: A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090109755 - Neighbor block refresh for non-volatile memory: Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090109754 - Non-volatile memory array architecture with joined word lines: In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be... Agent: Schwegman, Lundberg & Woessner / Atmel
20090109756 - Memory device with variable trim setting: A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090109757 - Semiconductor device and method of controlling the same: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090109758 - Nonvolatile memory array partitioning architecture and method to utilize single level cells and multi level cells within said architecture: A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a... Agent: Amin, Turocy & Calvin, LLP
20090109760 - Deterministic programming algorithm that provides tighter cell distributions with a reduced number of programming pulses: Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied... Agent: Amin, Turocy & Calvin, LLP
20090109759 - Operating memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells... Agent: Brooks, Cameron & Huebsch , PLLC
20090109742 - Control of temperature slope for band gap reference voltage in a memory device: Systems and/or methods are presented that can facilitate regulating performance of operations in a memory device based on controlling an operating temperature slope associated with the memory device. A regulator component can facilitate controlling the operating temperature slope level and controlling a reference voltage(s) associated with a word-line(s) and/or bit-line(s)... Agent: Amin, Turocy & Calvin, LLP
20090109761 - Method of operating nonvolatile memory device: Provided is a method of operating a three-dimensional nonvolatile memory device which may increase the reliability and efficiency of the three-dimensional nonvolatile memory device. The method of operating a nonvolatile memory device may include: resetting the nonvolatile memory device by injecting charges into charge storage layers of a plurality of... Agent: Harness, Dickey & Pierce, P.L.C
20090109762 - Method for programming non-volatile memory: A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons... Agent: Jianq Chyun Intellectual Property Office
20090109765 - Single via structured ic device: A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable... Agent: Connolly Bove Lodge & Hutz LLP
20090109763 - Semiconductor memory device and method of defective cell test: A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the... Agent: Mcginn Intellectual Property Law Group, PLLC
20090109764 - Integrated circuit having supply voltage controller: An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable... Agent: Texas Instruments Incorporated
20090109766 - Efficient sense command generation: In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense... Agent: Haynes And Boone, LLPIPSection
20090109767 - Semiconductor memory device having biderectional buffer: A semiconductor memory device includes a memory cell array divided into a plurality of areas, a common data bus connected to an input/output circuit, a plurality of individual data buses connected to different areas of the memory cell array through different paths respectively, and a bidirectional buffer connected to the... Agent: Mcginn Intellectual Property Law Group, PLLC
20090109768 - Sram device with enhanced read/write operations: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for... Agent: K & L Gates LLP
20090109769 - Signal descrambling detector: Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component... Agent: Amin, Turocy & Calvin, LLP
20090109770 - Semiconductor device with ddr memory controller: In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive... Agent: Sughrue Mion, PLLC
20090109771 - Optimizing mode register set commands: In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed... Agent: Trop, Pruner & Hu, P.C.
20090109772 - Ram with independent local clock: In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion... Agent: Haynes And Boone, LLPIPSection
20090109773 - Semiconductor device and refresh method: In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the region by a replacement with a repair memory block included in a plate included in each region. Specifically, the... Agent: Sughrue Mion, PLLC
20090109774 - Test method and semiconductor device: A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from... Agent: Dicke, Billig & Czaja
20090109775 - Precharge voltage supply circuit and semiconductor memory device using the same: A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a... Agent: Cooper & Dunham, LLP
20090109778 - Low-power sense amplifier: In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch... Agent: Haynes And Boone, LLPIPSection
20090109779 - Sense amplifier controlling circuit and controlling method: A sense amplifier controlling circuit for controlling a sense amplifier in a semiconductor memory, which amplifies differential electric potential of a pair of bit lines to which memory cells are connected by sequentially operating a CMOS flip-flop and a preamplifier performing an amplification operation different from each other, controls the... Agent: Foley And Lardner LLP Suite 500
20090109776 - Sense amplifier driving circult and semiconductor device having the same: The semiconductor memory device blocks a power supply voltage, which is supplied to the sense amplifier, in a write operation, or pull-down drives first and second local I/O lines LIO and LIOB lest they reach the level of ground voltage Vss. Driving time of a write driver of the semiconductor... Agent: Cooper & Dunham, LLP
20090109777 - Sense amplifier power supply circuit: A sense amplifier power supply circuit includes an overdriving unit configured to apply a first voltage to a sense amplifier in response to a first enable signal, a sense amplifier driving unit configured to apply a second voltage to the sense amplifier in response to a second enable signal, and... Agent: Cooper & Dunham, LLP
20090109780 - Hybrid static and dynamic sensing for memory arrays: A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.... Agent: Michael Buchenhorner, P.A.
20090109781 - Determining relative amount of usage of data retaining device based on potential of charge storing device: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and... Agent: Hoffman Warnick LLC
20090109784 - Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same: An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety of a specified range of row addresses, along a direction of column addresses. Each of... Agent: Oliff & Berridge, PLC
20090109783 - Refresh controlling circuit: A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output... Agent: Cooper & Dunham, LLP
20090109782 - Temperature detector in an integrated circuit: A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of... Agent: Connolly Bove Lodge & Hutz LLP
20090109785 - Memory having circuitry controlling the voltage differential between the word line and array supply voltage: An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage... Agent: Texas Instruments Incorporated
20090109786 - Data management method for non-volatile memory device: A method of operating a non-volatile data storage device includes determining the type of the previous power off event when the non-volatile data storage device is rebooted; and selecting and performing a reboot sequence based upon the determined type of the power off event. Determining the type of the previous... Agent: F. Chau & Associates, LLC
20090109788 - Data management method and mapping table update method in non-volatile memory device: A data management method of a non-volatile memory device includes writing data and representing a state of the data. The state includes one of multiple possible states. A state of the multiple possible states corresponding to a final operation is determined as a valid state of the data.... Agent: Volentine & Whitt PLLC
20090109787 - Nonvolatile memory systems with embedded fast read and write memories: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.... Agent: Banowsky &levine, P.c
20090109789 - Decoder with memory: In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes: a pre-charge circuit adapted to pre-charge a dynamic NOR node and... Agent: Haynes And Boone, LLPIPSection
20090109790 - Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus,... Agent: Mcginn Intellectual Property Law Group, PLLC04/23/2009 > patent applications in patent subcategories.
20090103344 - Memory module, system and method of making same: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices.... Agent: Trask Britt, P.C./ Micron Technology
20090103343 - Semiconductor memory device comprising transistor having vertical channel structure: A semiconductor memory device including a transistor having a vertical channel structure is provided. The device comprises a first sub memory cell array comprising a first memory cell connected to a first bit lines and comprising a transistor having a vertical channel structure, a second sub memory cell array comprising... Agent: Volentine & Whitt PLLC
20090103345 - Three-dimensional memory module architectures: Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of... Agent: Hewlett Packard Company
20090103346 - Semiconductor device: There is provided a semiconductor storage device having a memory cell including a transfer transistor, a load transistor and a drive transistor, which includes a first transfer transistor to become conductive by a potential applied to a first word line placed in parallel with a pair of bit lines, a... Agent: Sughrue Mion, PLLC
20090103347 - Sequence of current pulses for depinning magnetic domain walls: A method and structure for depinning a domain wall that is in spatial confinement by a pinning potential to within a local region of a magnetic device. At least one current pulse applied to the domain has a pulse length sufficiently close to a precession period of the domain wall... Agent: Schmeiser, Olsen & Watts
20090103348 - 2t/2c ferroelectic random access memory with complementary bit-line loads: The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states. A ferroelectric memory array includes rows and columns of 2T/2C memory cells, wherein each column of the memory array includes a first memory subcell having a... Agent: Hogan & Hartson LLP
20090103349 - Semiconductor memory device: A first memory cell array includes a first bit line and a second bit line arranged to read data out of a memory cell containing a ferroelectric capacitor. A second memory cell array includes a third bit line and a fourth bit line arranged to read data out of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090103350 - Method of testing an integrated circuit, method of manufacturing an integrated circuit, and integrated circuit: According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a plurality of memory cell array subunits, each memory cell array subunit including a plurality of resistivity changing memory... Agent: Slater & Matsil, L.L.P.
20090103352 - Dram including a reduced storage capacitor: A reduced storage capacitor is used for shrinking a memory cell in DRAM, and local bit line is divided into short line for reducing parasitic capacitance. For reading, a first reduced swing amplifier as a local sense amp reads the memory cell through the local bit line, and a second... Agent: Juhan Kim
20090103351 - Integrated circuit, method of manufacturing an integrated circuit, and memory module: According to one embodiment of the present invention, an integrated circuit includes at least one memory device including: a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer being disposed between the reactive electrode layer and the inert electrode layer; at least one interface layer being disposed... Agent: Slater & Matsil, L.L.P.
20090103353 - Semiconductor memory device: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of... Agent: Mcdermott Will & Emery LLP
20090103354 - Ground level precharge bit line scheme for read operation in spin transfer torque magnetoresistive random access memory: Systems, circuits and methods for read operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A plurality of bit cells, each coupled to one of a plurality of bit lines, word lines and source lines are provided. A plurality of precharge transistors corresponding to one of the... Agent: Qualcomm Incorporated
20090103355 - Nonvolatile semiconductor memory and data programming/erasing method: A nonvolatile semiconductor memory comprises: a semiconductor substrate; a first gate electrode formed on a surface of the semiconductor substrate through a first gate insulating film; a second gate electrode formed on the surface of the semiconductor substrate through a second gate insulating film and being adjacent to the first... Agent: Mcginn Intellectual Property Law Group, PLLC
20090103356 - Non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages: A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at... Agent: Vierra Magen/sandisk Corporation
20090103359 - Apparatus and method of multi-bit programming: Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and... Agent: Harness, Dickey & Pierce, P.L.C
20090103357 - Fast single phase program algorithm for quadbit: Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC
20090103361 - Level verification and adjustment for multi-level cell (mlc) non-volatile memory (nvm): Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell... Agent: Macpherson Kwok Chen & Heid LLP
20090103360 - Multi-bit flash memory device and program and read methods thereof: The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped.... Agent: Myers Bigel Sibley & Sajovec
20090103358 - Reducing programming error in memory devices: A method for storing data in an array (28) of analog memory cells (32) includes defining a constellation of voltage levels (90A, 90B, 90C, 90D) to be used in storing the data. A part of the data is written to a first analog memory cell in the array by applying... Agent: Darby & Darby P.C.
20090103362 - System and method for setting access and modification for synchronous serial interface nand: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal... Agent: Fletcher Yoder (micron Technology, Inc.)
20090103363 - Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.... Agent: Baker & Mckenzie LLP Patent Department
20090103365 - Sensing of memory cells in nand flash: An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20090103364 - Serial interface nand: Embodiments are provided that include operating a NAND memory device via an SPI interface. One such method includes cache loading a NAND memory device including loading data into a cache of the NAND memory device, writing data from the cache of the NAND memory device to an address of a... Agent: Fletcher Yoder (micron Technology, Inc.)
20090103366 - Non-volatile memory device: A non-volatile memory device may include at least one string, at least one bit line corresponding to the at least one string, and/or a sensing transistor. The at least one string may include a plurality of memory cell transistors connected in series. The sensing transistor may include a gate configured... Agent: Harness, Dickey & Pierce, P.L.C
20090103367 - One-transistor cell semiconductor on insulator random access memory: Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090103369 - Non-volatile memory and method with shared processing for an aggregate of read/write circuits: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090103368 - Semiconductor memory device: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090103370 - Efficient erase algorithm for sonos-type nand flash: A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090103371 - Memory cell operation: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the... Agent: Brooks, Cameron & Huebsch , PLLC
20090103372 - High performance high capacity memory systems: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while... Agent: Jeng-jye Shau
20090103373 - High performance high capacity memory systems: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while... Agent: Jeng-jye Shau
20090103374 - Memory modules and memory systems having the same: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of... Agent: Marger Johnson & Mccollom, P.C.
20090103375 - Sram cell using separate read and write circuitry: The present invention provides circuitry for writing to and reading from an SRAM cell core (105), an SRAM cell (100), and an SRAM device (400). In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core (105) that includes at least one write transistor (150). The... Agent: Texas Instruments Incorporated
20090103376 - Semiconductor memory device: A semiconductor memory device related to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a first interface part having a predetermined number of pins, a second interface part having a smaller number of the pins than the first interface part, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090103377 - Access unit for a static random access memory: An access unit for a static random access memory (SRAM) is provided. The access unit comprises two inverters. Two different variable voltages are supplied to the two inverters via bitlines to cause an imbalance in the current strengths between the two inverters so that data can be written on the... Agent: Holland & Knight LLP
20090103378 - Single-strobe operation of memory devices: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted... Agent: Ridout & Maybee LLP
20090103379 - Integrated circuit memory having dynamically adjustable read margin and method therefor: A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes... Agent: Freescale Semiconductor, Inc. Law Department
20090103380 - System and method for data read of a synchronous serial interface nand: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals... Agent: Fletcher Yoder (micron Technology, Inc.)
20090103381 - Asynchronous sense amplifier for read only memory: The asynchronous sense amplifier for a ROM comprises a current-mirror circuit, a first negative feedback inverter, a second negative feedback inverter, a first transistor group, a second transistor group and a feedback transistor. The feedback transistor connects the junction of the first transistor group and the first set of the... Agent: Connolly Bove Lodge & Hutz LLP
20090103382 - Gated diode sense amplifiers: A sense amplifier for use in sensing a signal in an integrated circuit comprises an amplifier portion and an output portion. The amplifier portion comprises a gated diode having a gate terminal. The output portion comprises an output transistor in signal communication with the gate terminal of the gated diode... Agent: Ryan, Mason & Lewis, LLP
20090103384 - Apparatus and method for self-refreshing dynamic random access memory cells: A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090103383 - Dynamic random access memory with fully independent partial array refresh function: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing.... Agent: Smart & Biggar P.o. Box 2999, Station D
20090103385 - Motherboard for supporting different types of memories: An exemplary motherboard includes a driving module, at least two first slots arranged for mounting two first type of memories, at least two second slots arranged for mounting two second type of memories, and a voltage regulator. The driving module is electronically connected to the at least two first slots,... Agent: PCe Industry, Inc. Att. Steven Reiss
20090103386 - Selectively-powered memories: Embodiments provide methods, apparatuses and systems including a plurality of memory cells configured to store bit values while being powered at a power-saving voltage lower than a normal-operation voltage during operation of a host apparatus, and power circuitry coupled to the plurality of memory cells. The power circuitry is configured... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20090103387 - High performance high capacity memory systems: The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while... Agent: Jeng-jye Shau
20090103388 - Histogram generation with banks for improved memory access performance: Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be... Agent: Morrison & Foerster, LLP
20090103389 - Semiconductor memory device and method of providing product families of the same: Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of... Agent: Mcginn Intellectual Property Law Group, PLLC
20090103390 - Three dimensional twisted bitline architecture for multi-port memory: Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each... Agent: International Business Machines Corporation Dept. 18g
20090103391 - Memory clock generator having multiple clock modes: An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal... Agent: Nixon & Vanderhye, PC04/16/2009 > patent applications in patent subcategories.
20090097294 - Dual-ported and-type match-line circuit for content-addressable memories: A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected... Agent: Troxell Law Office PLLC
20090097297 - Memory module having star-type topology and method of fabricating the same: A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the... Agent: Mills & Onello LLP
20090097295 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device can prevent memory characteristics from deteriorating due to IR drop on word or bit lines in a cross-point type memory cell array. The device comprises a word line selection circuit selecting a selected word line from word lines and applying selected and unselected word line... Agent: Nixon & Vanderhye, PC
20090097296 - Reduced size semiconductor memory device: A semiconductor memory device is described that includes memory banks having memory cells and are laid out as a matrix on a semiconductor chip body. The semiconductor memory device includes a first pad group having first pads that are arranged in a line between two adjoining memory banks and a... Agent: Ladas & Parry LLP
20090097298 - Integrated circuit, memory cell, memory module, method of operating an integrated circuit, and method of manufacturing a memory cell: According to one embodiment of the present invention, an integrated circuit includes an arrangement of memory cells. Each memory cell is connected to a programming current path used for programming the memory cell, and a sensing current path used for sensing the memory state of the memory cell. The programming... Agent: Slater & Matsil, L.L.P.
20090097299 - Semiconductor memory device, method for fabricating the same and semiconductor switching device: A first electrode is formed on a stacked-layer film, which is formed of a ferroelectric layer and a semiconductor layer, at the ferroelectric layer and a plurality of second electrodes are formed on the stacked-layer film at the semiconductor layer side. Each of parts of the semiconductor layer located in... Agent: Mcdermott Will & Emery LLP
20090097300 - Variable resistance element, its manufacturing method and semiconductor memory device comprising the same: Provided is a variable resistance element capable of performing a stable resistance switching operation and having a favorable resistance value retention characteristics, comprising a variable resistor 2 sandwiched between a upper electrode 1 and lower electrode 3 and formed of titanium oxide or titanium oxynitride having a crystal grain diameter... Agent: Nixon & Vanderhye, PC
20090097301 - Semiconductor storage apparatus and semiconductor integrated circuit incorporating the same: An object is to provide a semiconductor memory device which can dynamically change the number of memory cells used as by-pass capacitors. In each memory block, one selector signal line is provided in parallel to one word line. In a pair of the word line and the selector signal line... Agent: Wenderoth, Lind & Ponack L.L.P.
20090097302 - Semiconductor device: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.... Agent: Miles & Stockbridge PC
20090097303 - Mram with resistive property adjustment: A magnetic random access memory (MRAM) and a method for reading an MRAM is described. The MRAM may include a magnetoresistive bit, a read architecture coupled to the magnetoresistive bit that forms a read path with the magnetoresistive bit for performing a read operation on the magnetoresistive bit, and a... Agent: Honeywell International Inc.
20090097305 - Method of forming phase change material layer using ge(ii) source, and method of fabricating phase change memory device: In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction... Agent: Volentine & Whitt PLLC
20090097304 - Nonvolatile memory using resistance material: Provided is a nonvolatile memory using a resistance material. In embodiments of the invention, a PRAM is configured to apply a step-down voltage to wordlines during a standby mode. Aspects of the present invention thus provide a nonvolatile memory with reduced standby current. Additionally, embodiments of the invention allow for... Agent: Volentine & Whitt PLLC
20090097306 - Phase-change random access memory device, system having the same, and associated methods: A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality... Agent: Lee & Morse, P.C.
20090097307 - Phase-change random access memory device, system having the same, and associated methods: A phase-change random access memory (PRAM) device includes a PRAM cell array having a first bank that includes first to mth sectors, where m is a positive integer of at least 2, and sense amplifiers disposed between an xth sector and an (x+1)th sector of the bank, where x is... Agent: Lee & Morse, P.C.
20090097308 - Multivalue memory storage with two gating transistors: Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel, having a first and a second node, respectively, coupled to a storage element, and sensing circuitry coupled to a... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20090097309 - Nonvolatile semiconductor storage device, and method for controlling nonvolatile semiconductor storage device: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090097310 - Memory cell storage node length: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage... Agent: Brooks, Cameron & Huebsch , PLLC
20090097312 - Controlled ramp rates for metal bitlines during write operations from high voltage driver for memory applications: Systems and methods that control the switching transition times or profile of a ramped voltage write signal used for programming or erasing at least a wordline of an array of multi-bit and/or multi-level flash memory cells are provided. In one embodiment, this goal is accomplished by applying a ramped or... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC
20090097311 - Non-equal threshold voltage ranges in mlc nand: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
20090097314 - Page buffer and multi-state nonvolatile memory device including the same: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth... Agent: Volentine & Whitt PLLC
20090097313 - Page buffer, memory device having the page buffer and method of operating the same: A page buffer includes a first latch coupled between a sensing node and a data input/output node for storing data to be programmed. The sensing node is coupled to a bit line corresponding to an MLC selected for programming. The data input/output node receives/outputs data. A second latch is coupled... Agent: Townsend And Townsend And Crew, LLP
20090097316 - Flash memory device: The flash memory device includes a block switch, first and second cell strings, first and second source lines, drain contacts, and first and second source contacts. The first cell string is connected to a first bit line and a second cell string is connected to a second bit line. The... Agent: Townsend And Townsend And Crew, LLP
20090097315 - Multibit electro-mechanical memory device and method of manufacturing the same: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench,... Agent: Mills & Onello LLP
20090097319 - Applying adaptive body bias to non-volatile storage based on number of programming cycles: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or... Agent: Vierra Magen/sandisk Corporation
20090097317 - Integrated circuit having nand memory cell strings: Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench,... Agent: Slater & Matsil, L.L.P.
20090097318 - Programming sequence in nand memory: An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source follower sensing by programming the cells in NAND memory cell strings to maintain the resistance presented by the unselected cells on the source-side of a given selected... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20090097320 - Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots.... Agent: Wells St. John P.s.
20090097321 - Non-volatile memory device, method of operating the same, and method of fabricating the same: A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The... Agent: Harness, Dickey & Pierce, P.L.C
20090097322 - Semiconductor memory device: A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to... Agent: Arent Fox LLP
20090097323 - Bitline current generator for a non-volatile memory array and a non-volatile memory array: A bitline current generator, for a non-volatile memory array which comprises a plurality of memory bitcells and bitlines, comprises a switching means for each bitline for coupling a bitline to a program voltage supply when the bitline is selected for programming and a variable current source for providing a programming... Agent: Freescale Semiconductor, Inc. Law Department
20090097324 - Non-volatile memory device and a programmable voltage reference for a non-volatile memory device: A non-volatile memory device includes a voltage reference generator comprising a programmable voltage reference for generating a voltage signal having a programmable voltage level. In an embodiment, the programmable voltage reference provides the voltage signals for a wordline driver and/or a bitline current generator of the non-volatile memory device. The... Agent: Freescale Semiconductor, Inc. Law Department
20090097326 - Nand flash memory device having dummy memory cells and methods of operating same: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality... Agent: Myers Bigel Sibley & Sajovec
20090097325 - Programming method of a non-volatile memory device: In a programming method of a non-volatile memory device, a program operation is performed by applying a program voltage to a selected word line and a first pass voltage to unselected word lines. The first pass voltage shifts to a second pass voltage having a level lower than that of... Agent: Townsend And Townsend And Crew, LLP
20090097327 - Systems and methods for reading data from a memory array: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by... Agent: Texas Instruments Incorporated
20090097330 - Fuse latch circuit and fuse latch method: A fuse latch circuit starts a precharge operation for reading out a state of a fuse element when receiving an external command which is a command to reset an operation mode register (MRS reset command) after power-on, and reads out and latches the state of the fuse element after completion... Agent: Foley And Lardner LLP Suite 500
20090097331 - Interleaved input signal path for multiplexed input: System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090097328 - Method of detecting a light attack against a memory device and memroy device employing a method of detecting a light attack: A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a... Agent: Volentine & Whitt PLLC
20090097329 - Semiconductor storage device and high-speed address-latching method: A semiconductor storage device includes: an input buffer that receives address data and command data; a first through-latch-type latch circuit that latches the command data in synchronism with a rising edge of a clock signal; and a second through-latch-type latch circuit that latches the address data in synchronism with a... Agent: Mcginn Intellectual Property Law Group, PLLC
20090097332 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured... Agent: Harness, Dickey & Pierce, P.L.C
20090097333 - Semiconductor memory device with internal voltage generating circuit and method for operating the same: Semiconductor memory device with internal voltage generating circuit and method for operating the same includes a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; a... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090097335 - Method and apparatus for redundant memory configuration in voltage island: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a... Agent: Shimokaji & Associates, P.C.
20090097334 - Semiconductor device: In a semiconductor device having a redundant memory, the area of the device is reduced and a time required to transfer relief information is reduced. Moreover, a transfer control of relief information is facilitated. A first relief information storing unit stores relief information for relieving a redundant memory having a... Agent: Mcdermott Will & Emery LLP
20090097336 - Phase change memory device with improved performance that minimizes cell degradation: A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data.... Agent: Ladas & Parry LLP
20090097337 - Semiconductor stroage device: This disclosure concerns a memory including: memory cells having sources, drains, gates and floating bodies; word lines connected to gates of the memory cells and arranged in a first direction; first bit lines and second bit lines connected to sources or drains of the memory cells and arranged alternately in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090097338 - Memory device receiver: A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.... Agent: Morgan Lewis & Bockius LLP/rambus Inc.
20090097339 - Integrated circuit memory devices having internal command generators therein that support extended command sets using independent and dependent commands: Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent... Agent: Myers Bigel Sibley & Sajovec
20090097340 - Read command triggered synchronization circuitry: A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting... Agent: Ropes & Gray LLP
20090097341 - Semiconductor memory apparatus and method of driving the same: A semiconductor memory apparatus according to an embodiment of the invention includes a delay enable unit that generates a delay enable signal in response to an external ODT signal and an idle signal, a delay selecting unit that outputs the idle signal or a delay idle signal, which is obtained... Agent: Baker & Mckenzie LLP Patent Department
20090097342 - Built-in self repair circuit for a multi-port memory and method thereof: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test... Agent: J C Patents, Inc.
20090097343 - Method and system for testing address lines: Method and systems are described for testing an address line inter- coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a second address in the memory, wherein each of the first and second addresses are addressable in... Agent: Ingrassia Fisher & Lorenz, P.C. (gm)
20090097345 - Method, device and system for regulating access to an integrated circuit (ic) device: A circuit block access module (ICAM) residing on an integrated circuit and adapted to access a circuit block on the integrated circuit, the module comprising control logic adapted to extract data from a serial data line into two or more parallel data lines, wherein at least one of the parallel... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090097344 - Semiconductor memory testing device and method of testing semiconductor using the same: The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in... Agent: Ladas & Parry LLP
20090097346 - Memory with independent access and precharge: Digital memory devices and systems, as well as methods of operating digital memory devices, that include access circuitry to access a first subset of a plurality of memory cells associated with a current access address during a current access cycle and precharge circuitry, disposed in parallel relative to the access... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900
20090097347 - Sense-amplifier circuit for a memory device with an open bit line architecture: A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a... Agent: Slater & Matsil, L.L.P.
20090097348 - Integrated circuit including a memory module having a plurality of memory banks: An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately... Agent: Dicke, Billig & Czaja
20090097349 - Row active time control circuit and a semiconductor memory device having the same: A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more... Agent: Harness, Dickey & Pierce, P.L.C04/09/2009 > patent applications in patent subcategories.
20090091962 - Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each... Agent: Volentine & Whitt PLLC
20090091963 - Memory device: A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the... Agent: Larson Newman Abel & Polansky, LLP
20090091964 - Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region: A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity... Agent: Mcginn Intellectual Property Law Group, PLLC
20090091965 - Nonvolatile programmable logic circuit: A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area... Agent: Townsend And Townsend And Crew, LLP
20090091966 - Nonvolatile programmable logic circuit: A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area... Agent: Townsend And Townsend And Crew, LLP
20090091967 - Nonvolatile programmable logic circuit: A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area... Agent: Townsend And Townsend And Crew, LLP
20090091968 - Integrated circuit including a memory having a data inversion circuit: An integrated circuit includes an array of resistivity changing memory cells. The integrated circuit includes a circuit configured to invert a data word to be written to the array in response to determining that writing the inverted data word would use less power than writing the non-inverted data word.... Agent: Dicke, Billig & Czaja
20090091969 - Resistance change memory: A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090091970 - Semiconductor memory device: Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting... Agent: Mcdermott Will & Emery LLP
20090091971 - Semiconductor phase change memory using multiple phase change layers: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved... Agent: Trop, Pruner & Hu, P.C.
20090091972 - Semiconductor memory device and driving method thereof: The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of the body; a first gate electrode provided on the first surface via the first gate dielectric; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090091973 - Reducing effects of program disturb in a memory device: The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive Vpass voltage. The selected word lines are biased with a programming voltage. In one embodiment, the programming voltage is preceded by... Agent: Leffert Jay & Polglaze, P.A.
20090091974 - Methods of programming non-volatile memory cells: A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed... Agent: Harness, Dickey & Pierce, P.L.C
20090091976 - Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling: An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having... Agent: Slater & Matsil, L.L.P.
20090091975 - Non-volatile memory device and operation method of the same: Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may... Agent: Harness, Dickey & Pierce, P.L.C
20090091977 - Method and system for updating a stored data value in a non-volatile memory: The invention provides a method of updating a stored data value in a non-volatile memory. The method includes reading the stored data value from the non-volatile memory; reading a stored differential value from a volatile memory; receiving an updated data value; calculating a calculated differential value from the difference between... Agent: Townsend And Townsend And Crew, LLP
20090091979 - Reliable data storage in analog memory cells in the presence of temperature variations: A method for data storage includes programming a first group of analog memory cells at a first time at a known first temperature, so as to cause the analog memory cells in the first group to assume respective first analog storage values. Respective second analog storage values are read from... Agent: D. Kligler I.p. Services Ltd
20090091978 - Wear leveling method and controller using the same: A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The... Agent: J C Patents, Inc.
20090091980 - Semiconductor integrated circuit: In the semiconductor integrated circuit incorporating non-volatile memory that is not electrically rewritable, updating stored data and reusing the non-volatile memory are made possible. The data stored in the non-volatile memory can be updated and the non-volatile memory can be reused by dividing the non-volatile memory into a plurality of... Agent: Morrison & Foerster LLP
20090091981 - Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same: A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent... Agent: Volentine & Whitt PLLC
20090091982 - External clock tracking pipelined latch scheme: A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second... Agent: Schwegman, Lundberg & Woessner/micron
20090091984 - Memory configuration of a composite memory device: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite... Agent: Cooper & Dunham, LLP
20090091983 - Non-volatile memory structure and array thereof: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage... Agent: J C Patents, Inc.
20090091990 - Apparatus and method of multi-bit programming: Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2N threshold voltage states based on a target bit error rate (BER) of each of the page programming operations, a second control unit that may assign... Agent: Harness, Dickey & Pierce, P.L.C
20090091985 - Input circuit of semiconductor memory apparatus and control method of the same: An input circuit of a semiconductor memory apparatus includes a first frequency control unit which receives a first signal and a second frequency control unit which receives a second signal. The first frequency control unit outputs the first signal to the second frequency control unit in response to a test... Agent: Baker & Mckenzie LLP Patent Department
20090091986 - Circuits, devices, systems, and methods of operation for a linear output driver: Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current paths that either source currents to or sink currents from... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090091987 - Multiple memory standard physical layer macro function: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the... Agent: Christopher P Maiorana, PC Lsi Corporation
20090091989 - Semiconductor memory device and biasing method thereof: The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method thereof. The semiconductor memory device includes: a dummy bit line disposed in a cell array; and a switching unit... Agent: Ladas & Parry LLP
20090091988 - Writing bit alterable memories: A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply... Agent: Trop, Pruner & Hu, P.C.
20090091991 - Apparatuses and methods for multi-bit programming: Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a... Agent: Harness, Dickey & Pierce, P.L.C
20090091992 - Semiconductor memory apparatus: A semiconductor memory apparatus include an internal tuning unit that can tune a generation timing of a data input strobe signal according to input timings of an input data and a data strobe clock signal, and a data input sense amplifier that can transmit data bits to a global line... Agent: Baker & Mckenzie LLP Patent Department
20090091993 - Semiconductor storage device and memory cell test method: A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is... Agent: Young & Thompson
20090091994 - System and method for initiating a bad block disable process in a non-volatile memory: A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to executing the initial valid command.... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP
20090091995 - Sense amplifier circuit having current mirror architecture: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage... Agent: North America Intellectual Property Corporation
20090091996 - Solid state semiconductor storage device with temperature control function, application system thereof and control element thereof: A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing element is used for sensing the operation temperature of the solid state semiconductor storage device so as to provide a temperature sensing signal to... Agent: Rosenberg, Klein & Lee
20090091997 - Semiconductor memory device suitable for mounting on portable terminal: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal,... Agent: Buchanan, Ingersoll & Rooney PC
20090091999 - Leakage optimized memory: A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing only padding... Agent: Christopher P Maiorana, PC Lsi Corporation
20090091998 - Power saving method and circuit thereof for a semiconductor memory: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first... Agent: Volpe And Koenig, P.C.
20090092000 - Semiconductor memory device with reduced current consumption: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory... Agent: Arent Fox LLP04/02/2009 > patent applications in patent subcategories.
20090086522 - Address line wiring structure and printed wiring board having same: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A... Agent: Young & Thompson
20090086521 - Multiple antifuse memory cells and methods to form, program, and sense the same: Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both.... Agent: Dugan & Dugan, PC
20090086523 - Integrated circuit and method of forming an integrated circuit: An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of... Agent: Fay Kaplun & Marcin, LLP
20090086525 - Multi-layered memory devices: A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes... Agent: Harness, Dickey & Pierce, P.L.C
20090086524 - Programmable rom using two bonded strata and method of operation: A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in... Agent: Freescale Semiconductor, Inc. Law Department
20090086526 - Apparatus, embedded memory, address decoder, method of reading out data and method of configuring a memory: Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only... Agent: Infineon Technologies Ag Patent Department
20090086527 - Non-volatile memory device having threshold switching resistor, memory array including the non-volatile memory device and methods of manufacturing the same: Provided are a non-volatile memory device having a threshold switching resistor, a memory array including the non-volatile memory device, and methods of manufacturing the same. A non-volatile memory device having a threshold switching resistor may include a first resistor having threshold switching characteristics, an intermediate electrode on the first resistor,... Agent: Harness, Dickey & Pierce, P.L.C
20090086528 - Back gated sram cell: Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The... Agent: Brooks, Cameron & Huebsch , PLLC
20090086529 - Semiconductor storage device: In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semiconductor storage device according... Agent: Sughrue Mion, PLLC
20090086532 - Magnetic random access memory: A magnetic random access memory includes a memory cell having a first magnetoresistive effect element, a reference cell having a second magnetoresistive effect element set in a low-resistance state, a first bit line connected to the memory cell, and set at a first bias potential in a read operation, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090086531 - Method and implementation of stress test for mram: Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS)... Agent: Saile Ackerman LLC
20090086530 - System and method for reading multiple magnetic tunnel junctions with a single select transistor: A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the... Agent: K & L Gates LLP
20090086533 - Superconducting circuit for high-speed lookup table: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory... Agent: Milde & Hoffberg, LLP
20090086534 - Apparatus and method for implementing precise sensing of pcram devices: A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to... Agent: Cantor Colburn LLP-ibm Burlington
20090086535 - Semiconductor array: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled... Agent: Seed Intellectual Property Law Group PLLC
20090086536 - Semiconductor device: A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of... Agent: Rader Fishman & Grauer PLLC
20090086537 - Semiconductor device: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and... Agent: Rader Fishman & Grauer PLLC
20090086538 - Method and apparatus for programming memory cell array: Disclosed are a method and device for programming an array of memory cells.... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP
20090086539 - Non-volatile memory with both single and multiple level cells: Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices... Agent: Brooks, Cameron & Huebsch , PLLC
20090086540 - Method of operating non-volatile memory array: A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method... Agent: Jianq Chyun Intellectual Property Office
20090086541 - Column redundancy ram for dynamic bit replacement in flash memory: A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for... Agent: Schwegman, Lundberg & Woessner / Atmel
20090086542 - High voltage generation and control in source-side injection programming of non-volatile memory: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent... Agent: Vierra Magen/sandisk Corporation
20090086543 - Highly compact non-volatile memory and method thereof: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090086544 - Compensation of non-volatile memory chip non-idealities by program pulse adjustment: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse... Agent: Vierra Magen/sandisk Corporation
20090086545 - Non-volatile memory device and method of operating the same: The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a... Agent: Marshall, Gerstein & Borun LLP
20090086546 - Nonvolatile semiconductor memory device and method of writing data into the same: In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the... Agent: Sughrue Mion, PLLC
20090086547 - Circuit for performing read operation in nand flash memory and method thereof: A circuit for performing a read operation in a NAND flash memory is disclosed. The NAND flash memory includes an array of bit lines grouped into first group of bit lines and second group of bit lines. The circuit includes a plurality of pre-charging and reading circuitries connected at first... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC
20090086548 - Flash memory: A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate,... Agent: Schmeiser, Olsen & Watts
20090086549 - Method for driving a nonvolatile semiconductor memory device: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090086550 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks a plurality of banks stacked in a column direction, a global data line corresponding to the plurality of banks and a common global data line driving unit for multiplexing data on a plurality of local data lines corresponding to each of... Agent: Mannava & Kang, P.C.
20090086551 - Semiconductor device: Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin... Agent: Foley And Lardner LLP Suite 500
20090086552 - Semiconductor memory device and its driving method: A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from... Agent: Mannava & Kang, P.C.
20090086553 - Semiconductor memory device and method of inputting and outputting data in the semiconductor memory device: A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semiconductor memory device is operated in a read mode.... Agent: Lee & Morse, P.C.
20090086554 - System and method for operating a semiconductor memory: A method for operating a semiconductor memory cell is disclosed. A first voltage is applied to the memory cell. The first voltage is dependent on temperature and semiconductor process variation in a manner that keeps the memory cell in a stable region of operation.... Agent: Slater & Matsil LLP
20090086555 - Voltage supply circuit and semiconductor memory: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the... Agent: Arent Fox LLP
20090086556 - Methods and apparatuses for operating memory: A low voltage memory apparatus is disclosed. The memory apparatus can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and a bit cell isolator to isolate... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC
20090086557 - Synchronous semiconductor memory device and method for driving the same: A synchronous semiconductor memory device including a data alignment reference pulse generating unit configured to generate a data alignment reference pulse in response to a data strobe signal (DQS), an alignment hold signal generating unit configured to generate an alignment hold signal, which is activated during a period corresponding to... Agent: Mcdermott Will & Emery LLP
20090086558 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090086559 - Semiconductor memory device and driving method thereof: This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090086560 - Memory device with self refresh cycle control function: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent... Agent: Mcdermott Will & Emery LLP
20090086561 - Motherboard for supporting different types of memories: An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second... Agent: PCe Industry, Inc. Att. Steven Reiss
20090086562 - Devices, systems, and methods for independent output drive strengths: Methods, apparatuses and systems are disclosed for independently configurable data and strobe drivers within a memory device. A memory device may include at least one data driver, at least one strobe driver, and an extended mode register operably coupled to the at least one data driver and the at least... Agent: Trask Britt, P.C./ Micron Technology
20090086563 - Memory word line driver featuring reduced power consumption: Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line... Agent: Courtney Staniford & Gregory LLP
20090086564 - Semiconductor memory device: A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array.... Agent: Mannava & Kang, P.C.
20090086565 - System and method for processing signals in high speed dram: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at... Agent: Fletcher Yoder (micron Technology, Inc.)
20090086566 - Semiconductor memory device capable of performing page mode operation: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit... Agent: Volentine & Whitt PLLCPrevious industry: Electric power conversion systems
Next industry: Agitating
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