|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrieval March listing by industry category 03/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 03/26/2009 > patent applications in patent subcategories.
20090080230 - Edram hierarchical differential sense amp: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of... Agent: Cantor Colburn LLP-ibm Yorktown
20090080229 - Single-layer metal conductors with multiple thicknesses: A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are... Agent: Vierra Magen/sandisk Corporation
20090080231 - Semiconductor memory device: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and... Agent: Mcdermott Will & Emery LLP
20090080232 - Area efficient programmable read only memory (prom) array: A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse... Agent: Intel Corporation C/o Intellevate, LLC
20090080233 - Method and apparatus for printed resistive read only memory: A printed read only memory (ROM) device that consists of an array of memory resistors, a reference resistor, and analog-to-digital circuit is disclosed. Resistance values are dependent on the data to be stored in the read only memory. During read operation, a resistor in the array is powered, activating a... Agent: Prass LLP
20090080235 - Compact and highly efficient dram cell: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a... Agent: Mcandrews Held & Malloy, Ltd
20090080234 - Semiconductor device and dram controller: According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply potential (VCC-GND) so as to improve resistance against degradation of hold characteristics. Further, low power consumption can be realized... Agent: Young & Thompson
20090080236 - Semiconductor memory device and method for manufacturing same: Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second... Agent: Sonnenschein Nath & Rosenthal LLP
20090080237 - Sram memory with reference bias cell: A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second... Agent: Pearne & Gordon LLP
20090080239 - Magnetoresistive element and magnetic memory: A magnetoresistive element includes a first reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization, a recording layer having a stacked structure formed by alternately stacking magnetic layers and nonmagnetic layers, magnetic anisotropy perpendicular to a film surface, and a variable magnetization, and an intermediate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090080238 - Magnetoresistive element and magnetoresistive random access memory including the same: The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090080240 - Method for production of mram elements: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied... Agent: Dickstein Shapiro LLP
20090080243 - Device controlling phase change storage element and method thereof: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation... Agent: Quintero Law Office, PC
20090080242 - Programming a multilevel phase change memory cell: Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are... Agent: Trop, Pruner & Hu, P.C.
20090080241 - Programming a phase change memory: A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled to the controllable current generator for stepwise modifying the programming pulse. The internal control unit, in turn, includes a control signal generator to provide the... Agent: Trop, Pruner & Hu, P.C.
20090080244 - Refreshing data of memory cells with electrically floating body transistors: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored... Agent: Courtney Staniford & Gregory LLP
20090080246 - Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory: A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP
20090080245 - Offset non-volatile storage: A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.... Agent: Vierra Magen/sandisk Corporation
20090080248 - Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt: A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell.... Agent: Kacvinsky LLC C/o Intellevate
20090080251 - Nand flash memory devices and methods of lsb/msb programming the same: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main... Agent: Myers Bigel Sibley & Sajovec
20090080249 - Non-volatile memory cell endurance using data encoding: A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block.... Agent: Brinks Hofer Gilson & Lione/sandisk
20090080250 - Nonvolatile semiconductor storage device and operation method thereof: A multi-valued nonvolatile semiconductor storage device and an operation method thereof capable of setting a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages for storing information in a charge storage layer is provided. According to one aspect, there is provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090080252 - Semiconductor memory device: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA , and a storage block is selected with external address... Agent: Mcdermott Will & Emery LLP
20090080247 - Using mlc flash as slc by writing dummy data: A method for storing data includes designating, in a memory array including cells configured for writing a first number of bits per cell, a group of the cells to which input data are to be written at a second number of bits per cell, smaller than the first number. Dummy... Agent: Sandisk C/o Darby & Darby PC
20090080253 - Device, system, and method of bit line selection of a flash memory: Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line... Agent: Empk & Shiloh ,llp
20090080254 - Gated diode nonvolatile memory cell array: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090080255 - Nonvolatile semiconductor memory device: A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging whether an input address matches the address information in the address storage section and outputting a result of the judgment, and a write or erase voltage generation... Agent: Mcdermott Will & Emery LLP
20090080256 - Flash memory device and programming method: Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump,... Agent: Volentine & Whitt PLLC
20090080257 - Semiconductor device: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active... Agent: Miles & Stockbridge PC
20090080258 - Erase method in thin film nonvolatile memory: An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any source-to-body short; (b) flexible erase which erases any number of memory cells in a block (i.e., from none to all cells); (c)... Agent: Macpherson Kwok Chen & Heid LLP
20090080262 - Method of programming a nand flash memory device: A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided... Agent: Townsend And Townsend And Crew, LLP
20090080261 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090080259 - Post-facto correction for cross coupling in a flash memory: A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that... Agent: Mark M. Friedman
20090080260 - Programmable csonos logic element: A complementary SONOS-type (CSONOS) logic device is programmed and erased with a common voltage. The CSONOS device retains data integrity over extended read endurance cycles.... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP
20090080263 - Reducing programming voltage differential nonlinearity in non-volatile storage: A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which... Agent: Vierra Magen/sandisk Corporation
20090080264 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090080265 - Multiple bit line voltages based on distance: An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a... Agent: Vierra Magen/sandisk Corporation
20090080266 - Double data rate (ddr) low power idle mode through reference offset: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a double data rate (DDR) low power idle mode through reference offset. In some embodiments, a host offsets a reference voltage from a termination voltage of a command/address interconnect when the interconnect is tri-stated. Other embodiments are... Agent: Intel Corporation C/o Intellevate, LLC
20090080267 - Generating reference currents compensated for process variation in non-volatile memories: In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage... Agent: Trop, Pruner & Hu, P.C.
20090080268 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090080269 - Semiconductor memory device: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with... Agent: Mcdermott Will & Emery LLP
20090080270 - Memory device having terminals for transferring multiple types of data: A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and... Agent: Schwegman, Lundberg & Woessner/micron
20090080271 - Memory cell, memory device, device and method of accessing a memory cell: Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell.... Agent: Infineon Technologies Ag Patent Department
20090080272 - Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a... Agent: F. Chau & Associates, LLC
20090080273 - Semiconductor memory device having redundancy memory block and cell array structure thereof: A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of... Agent: F. Chau & Associates, LLC
20090080274 - Memory control circuit and semiconductor device: A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation,... Agent: Dickstein Shapiro LLP
20090080275 - Reducing bit line leakage current in non-volatile memories: In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example... Agent: Schwegman, Lundberg & Woessner, P.A.
20090080276 - Temperature dependent bias for minimal stand-by power in cmos circuits: A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which... Agent: Innovation Interface, LLC
20090080277 - Memory cell fuse circuit and controlling method thereof: A controlling method of a memory cell fuse circuit is provided. The memory cell fuse circuit at least includes a reference cell fuse circuit and a plurality of normal cell fuse circuit. The reference cell fuse circuit includes a reference fuse cell and each the normal cell fuse circuit includes... Agent: Volpe And Koenig, P.C.
20090080278 - Circuit and method for reducing power in a memory device during standby modes: A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes... Agent: Trask Britt, P.C./ Micron Technology
20090080279 - Structure to share internally generated voltages between chips in mcp: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090080280 - Electronic memory device: An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090080281 - Negative voltage detection circuit and semiconductor integrated circuit: A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.03/19/2009 > patent applications in patent subcategories.
20090073736 - Semiconductor device having storage nodes on active regions and method of fabricating the same: A semiconductor device includes an active region in a semiconductor substrate, having first, second and third regions sequentially arranged in the active region. An inactive region in the semiconductor substrate defines the active region. Gate patterns, partially buried in the active and inactive regions, are positioned between the first and... Agent: Volentine & Whitt PLLC
20090073738 - Active shielding for a circuit comprising magnetically sensitive materials: The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device allows shielding for strong disturbing magnetic fields.... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090073737 - Integrated circuits; methods for manufacturing an integrating circuit; memory modules: Embodiments of the invention relate generally to integrated circuits, to methods for manufacturing an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit is provided having a memory cell. The memory cell may include a first magnetic layer structure, a tunnel barrier layer structure... Agent: Slater & Matsil, L.L.P.
20090073739 - Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces: Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20090073740 - Nonvolatile semiconductor memory device: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters... Agent: The Marbury Law Group, PLLC
20090073741 - Nand-structured series variable-resistance material memories, processes of forming same, and methods of using same: A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells is in parallel with a corresponding series of control gates. A select gate is also in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory... Agent: Schwegman, Lundberg & Woessner/micron
20090073742 - Semiconductor storage device and operating method of the same: A semiconductor storage device includes: reading blocks; third wirings; reading switches; a control circuit; and evaluating circuits. The reading blocks includes first and second wirings extended in a first and second direction, respectively, and resistive storage elements arranged at points where the first and second wirings intersect. The third wirings... Agent: Young & Thompson
20090073743 - Method of manufacturing a memory cell, memory cell, integrated circuit, and memory module: A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the... Agent: Slater & Matsil, L.L.P.
20090073744 - Semiconductor storage device: A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the... Agent: Mcginn Intellectual Property Law Group, PLLC
20090073745 - Semiconductor integrated circuit: During a write cycle, a selected write-word-line driver drives the corresponding write word line such that the potential of the corresponding write word line is lower in a first period as a predetermined period after an initiation of the write cycle than in a second period as a predetermined period... Agent: Mcdermott Will & Emery LLP
20090073746 - Static random access memory cell: A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bitline-bar (BLB). A second pass-gate FET (T1) is coupled between a second node (B) and a bitline (BL). The second node (B)... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090073749 - Integrated circuit, cell arrangement, method of operating an integrated circuit, memory module: An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line... Agent: Slater & Matsil, L.L.P.
20090073748 - Integrated circuits; methods for operating an integrating circuit; memory modules: Embodiments of the invention relate generally to integrated circuits, to methods for operating an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit having a magnetic random access memory cell is provided. The magnetic random access memory cell may include a reference layer structure... Agent: Slater & Matsil, L.L.P.
20090073747 - Magnetoresistive sensor memory with multiferroic material: A memory cell includes a magnetoresistive sensor that comprises layers that include a free layer. The magnetoresistive sensor conducts a read current representative of data stored in the memory cell during a read interval. A first write conductor carries a write current that writes data in the free layer. At... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20090073750 - Method for programming an integrated circuit, methods for programming a plurality of cells, integrated circuit, cell arrangement: Embodiment of the invention provide a method for programming an integrated circuit, methods for programming a plurality of cells, an integrated circuit, and a cell arrangement. An embodiment of the invention provides a method for programming an integrated circuit having a plurality of cells. The method includes grouping the plurality... Agent: Slater & Matsil, L.L.P.
20090073752 - Adaptive wordline programming bias of a phase change memory: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused... Agent: Trop, Pruner & Hu, P.C.
20090073751 - Interleaved array architecture: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of... Agent: Trop, Pruner & Hu, P.C.
20090073754 - Multi-level phase change memory device, program method thereof, and method and system including the same: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set... Agent: Mills & Onello LLP
20090073753 - Semiconductor device: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and... Agent: Miles & Stockbridge PC
20090073756 - Boosted gate voltage programming for spin-torque mram array: A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that... Agent: Saile Ackerman LLC
20090073755 - Mram read bit with askew fixed layer: A new read scheme is provided for an MRAM bit having a reference layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. The reference layer has a magnetization direction that is tilted with respect to an easy axis of the storage layer. By applying a magnetic field... Agent: Honeywell International Inc.
20090073757 - Double density mram with planar processing: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated magnetic memory structures. In one aspect, the present teachings relate to magnetic memory structure fabrication techniques... Agent: Knobbe Martens Olson & Bear LLP
20090073758 - Sram cells with asymmetric floating-body pass-gate transistors: The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090073761 - Self-boosting system for flash memory cells: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090073763 - Method for controlling a non-volatile semiconductor memory device: A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090073762 - Methods of operating multi-bit flash memory devices and related systems: Methods of operating a non-volatile multi-bit memory device can include programming multi-bit memory cells included in one page of the device with page data including an error detection code based on the page data and determining the validity of the page data using the error detection code read from the... Agent: Myers Bigel Sibley & Sajovec
20090073765 - Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling: A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090073764 - Nonvolatile semiconductor storage device capable of high-speed writing: A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090073766 - Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages: A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090073767 - Control gate line architecture: A non-volatile storage system that includes less word line drivers than word lines by having a limited set of individually controllable drivers for a subset of unselected word lines requiring word line by word line control, and have the remaining word lines connected to a common source.... Agent: Vierra Magen/sandisk Corporation
20090073768 - Memory with output control: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090073769 - Method and system for optimizing reliability and performance of programming data in non-volatile memory devices: Methods of managing memory devices, and devices so managed. A value of a parameter, that is used to program one or more memory cells, is adapted to a monitored condition of the cell(s). Either the number of bits per cell is held fixed or the monitored condition is an intrinsic... Agent: Mark M. Friedman
20090073759 - Device for protecting a memory against attacks by error injection: A memory is secured against an error injection during the reading of a datum. The memory includes: means for reading a reference datum in the memory during a phase of reading a datum stored in the memory; means for comparing the reference datum read with an expected value; and means... Agent: Seed Intellectual Property Law Group PLLC
20090073760 - Minimizing read disturb in an array flash cell: A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090073770 - Independent bi-directional margin control per level and independently expandable reference cell levels for flash memory sensing: A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels.... Agent: Dla Piper LLP (us )
20090073771 - Non-volatile memory and method for biasing adjacent word line for verify during programming: Various programming techniques for nonvolatile memory involve programming a memory cell relative to a target threshold level. The process includes initially programming relative to a first verify level short of the target threshold level by a predetermined offset. Later, the programming is completed relative to the target verify level. For... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090073772 - Program method with optimized voltage level for flash memory: A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster... Agent: Leffert Jay & Polglaze, P.A. Att: Andrew C. Walseth
20090073773 - Memory circuit, drive circuit for a memory and method for writing write data into a memory: A first and second non-volatile memory transistor each have a floating gate electrode and a gate terminal. A first switch is connected between a first drain terminal and a bit line for reading out information, and a second switch is connected between a second drain terminal and the bit line.... Agent: Eschweiler & Associates LLC
20090073775 - Bit line setup and discharge circuit for programming non-volatile memory: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines... Agent: Harness, Dickey & Pierce, P.L.C
20090073774 - Pre-charge sensing scheme for non-volatile memory (nvm): The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.
20090073776 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device is provided in which stable transistor characteristics with little variation can be obtained, and sufficient threshold voltage and ON current fluctuations can be obtained. A source 2 and a drain 3 formed on a surface of a semiconductor substrate 1, and a gate electrode 5... Agent: Young & Thompson
20090073783 - Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell... Agent: Law Office Of Ido Tuchman (yor)
20090073784 - Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being... Agent: Law Office Of Ido Tuchman (yor)
20090073785 - Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target... Agent: Law Office Of Ido Tuchman (yor)
20090073778 - Semiconductor memory device: A semiconductor memory device comprises a plurality of submacros mutually connected via global data lines. Each of the submacros includes a first and a second memory block, and a memory block control circuit arranged between the first and second memory blocks. The memory block control circuit includes a DQ buffer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090073779 - Semiconductor storage device including counter noise generator and method of controlling the same: A semiconductor storage device according to one aspect of the present invention includes a reference voltage source connected to a capacitor of a cell included in a memory, a buffer circuit holding data to be written in the cell, and a counter noise generator outputting a counter noise current canceling... Agent: Foley And Lardner LLP Suite 500
20090073777 - Signal transfer apparatus and methods: Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes... Agent: Schwegman, Lundberg & Woessner/micron
20090073780 - Memory device for detecting bit line leakage current and method thereof: A memory device may include a plurality of bit line pairs, at least one local data line pair, and/or a bit line leakage current measurement unit. The at least one local data line pair may be connected to the bit line pairs in response to a column selection signal. The... Agent: Harness, Dickey & Pierce, P.L.C
20090073781 - Sense amplifier: A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation.... Agent: Fish & Richardson P.C.
20090073782 - System, apparatus, and method to increase read and write stability of scaled sram memory cells: Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias... Agent: Trask Britt, P.C./ Micron Technology
20090073786 - Early write with data masking technique for integrated circuit dynamic random access memory (dram) devices and those incorporating embedded dram: An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability.... Agent: Hogan & Hartson LLP
20090073787 - Method for controlling time point for data output in synchronous memory device: Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous... Agent: Ladas & Parry LLP
20090073788 - Repairing advanced-memory buffer (amb) with redundant memory buffer for repairing dram on a fully-buffered memory-module: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access... Agent: Stuart T Auvinen
20090073789 - Method and apparatus for testing a memory device: Disclosed is a method for testing a memory device with a long-term clock signal by automatically performing precharge only after activation. In this method, a signal for precharging the banks of the memory device is automatically generated only at the falling edge of an external signal when a signal for... Agent: Ladas & Parry LLP
20090073791 - Low voltage data path and current sense amplifier: Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the... Agent: Brooks, Cameron & Huebsch , PLLC
20090073790 - Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition: A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage.... Agent: Law Office Of Ido Tuchman (yor)
20090073792 - Wide databus architecture: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
20090073794 - Method for hiding a refresh in a pseudo-static memory: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i≠j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20090073793 - Semiconductor memory device and refresh method for the same: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even... Agent: Arent Fox LLP
20090073795 - Dynamic random access memory and boosted voltage producer therefor: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump... Agent: Mosaid Technologies Incorporated
20090073797 - semiconductor memory device with control block sharing row decoders: A semiconductor memory device comprises a plurality of banks including a plurality of mat rows, respectively, wherein the mat row includes a plurality of mats disposed in a same row, row decoder groups disposed between the banks and including row decoders that correspond to the mat rows, respectively, and common... Agent: Baker & Mckenzie LLP Patent Department
20090073796 - Memory array peripheral structures and use: A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.... Agent: Schmeiser, Olsen & Watts03/12/2009 > patent applications in patent subcategories.
20090067209 - Low-power content-addressable-memory device: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067210 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
20090067211 - Electronic fuse system and methods: An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller... Agent: Texas Instruments Incorporated
20090067214 - Electric element, memory device, and semiconductor integrated circuit: An electric element includes a first terminal (1), a second terminal (3), and a variable-resistance film (2). The variable-resistance film (2) is connected between the first terminal (1) and the second terminal (3). The variable-resistance film (2) includes Fe3O4 crystal phase and Fe2O3 crystal phase.... Agent: Mcdermott Will & Emery LLP
20090067215 - Electric element, memory device, and semiconductor integrated circuit: An electric element comprises: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one... Agent: Mcdermott Will & Emery LLP
20090067212 - Magnetic random access memory and data read method of the same: A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067213 - Method of forming controllably conductive oxide: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is... Agent: Paul J. Winters
20090067216 - Resistive memory devices including selected reference memory cells: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source... Agent: Myers Bigel Sibley & Sajovec
20090067217 - Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same: In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied... Agent: Harness, Dickey & Pierce, P.L.C
20090067218 - Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) and (ii) sense amplifier circuitry, coupled to the memory cell array, to sense a data state... Agent: Neil Steinberg
20090067220 - Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor: A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor provided between the output terminal of the first inverter and one line of a bit line pair, a transmission transistor provided... Agent: Mcginn Intellectual Property Law Group, PLLC
20090067219 - Semiconductor memory device including sram cell having well power potential supply region provided therein: A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer... Agent: Mcginn Intellectual Property Law Group, PLLC
20090067223 - Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect... Agent: Ryan, Mason & Lewis, LLP
20090067221 - High density 45nm sram using small-signal non-strobed regenerative sensing: A memory device includes a plurality of cells comprising CMOS structures. A non-strobed regenerative sense-amplifier (NSR-SA) is coupled to the cells and employs offset compensation and avoids strobe timing uncertainty to increase read-access speeds.... Agent: Gauthier & Connors, LLP
20090067222 - Semiconductor memory device: SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067224 - Magnetoresistive element, particularly memory element or logic element, and method for writing information to such an element: A magnetoresistive element, in particular a memory element or a logic element and a method for writing information to such an element are disclosed. The element comprises a first contact of ferromagnetic material and a corresponding layer of magnetoelectric or ferromagnetic material, whereby the first contact is magnetically polarized, depending... Agent: Jason H. Vick Sheridan Ross, PC
20090067225 - Modular magnetoresistive memory: A magnetoresistive memory element has a read module with a first pinned layer that has a magnetoresistance that is readable by a read current received from an external circuit. The element has a write module that receives a write current from the external circuit. A coupling module adjacent both the... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20090067226 - Integrated circuit with phase-change memory cells and method for addressing phase-change memory cells: The present invention relates to integrated circuit comprising a plurality of bitlines (b1) and a plurality of word-lines (w1) as well as a plurality of memory-cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (b1) and wordlines (w1) for storing data in the memory cell. Each... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090067230 - Multi-level memory devices and methods of operating the same: The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.... Agent: Mills & Onello LLP
20090067227 - Phase change memory device having a plurality of reference currents and operating method thereof: A phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A plurality of sense amplifiers sense and amplify data of the phase change resistance cell selected using a plurality of reference currents.... Agent: Ladas & Parry LLP
20090067228 - Phase change memory device, manufacturing method thereof and operating method thereof: A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM... Agent: Ladas & Parry LLP
20090067229 - Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells... Agent: Ladas & Parry LLP
20090067231 - Magnetic memory cell based on a magnetic tunnel junction(mtj) with independent storage and read layers: Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing.... Agent: Hahn And Moodley, LLP
20090067232 - Multiple magneto-resistance devices based on doped magnesium oxide: The present invention provides a low resistance high magnetoresistance (MR) device comprised of a junction of two magnetic elements separated by a magnesium oxide (MgO) layer doped with such metals as Al and Li. Such device can be used as a sensor of magnetic field in magnetic recording or as... Agent: Foley And Lardner LLP Suite 500
20090067233 - Magnetic random access memory and method of reading data from the same: A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel... Agent: Lee & Morse, P.C.
20090067234 - Flash memory device and fabrication method thereof: The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence... Agent: Marshall, Gerstein & Borun LLP
20090067239 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper LLP (us )
20090067237 - Multi-bit data memory system and read operation: Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if... Agent: Volentine & Whitt PLLC
20090067238 - Non-volatile memory cell read failure reduction: The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method... Agent: Brooks, Cameron & Huebsch , PLLC
20090067236 - Nonvolatile semiconductor memory device: A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067240 - Programming a memory with varying bits per cell: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals... Agent: Leffert Jay & Polglaze, P.A. Att: Kenneth W. Bolvin
20090067235 - Test circuit and method for multilevel cell flash memory: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.... Agent: Dla Piper LLP (us )
20090067241 - Data protection for write abort: A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data.... Agent: Weaver Austin Villeneuve Sampson LLP
20090067243 - Nonvolatile semiconductor memory device and method of driving the same: This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067242 - Programming method of flash memory device: A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select... Agent: Townsend And Townsend And Crew, LLP
20090067244 - Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages: Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090067245 - Semiconductor memory device provided with mos transistor having charge accumulation layer and control gate and data write method of nand flash memory: A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067247 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell... Agent: Harness, Dickey & Pierce, P.L.C
20090067246 - Methods to prevent program disturb in nonvolatile memory: Methods are provided to be used individually or in any combination that reduce program disturb in a non-volatile memory consisting of dual-gate memory cells. These methods counteract the effect of a leakage current in reducing a boosted voltage in a non-selected dual-gate memory string. According to one approach, a voltage... Agent: Macpherson Kwok Chen & Heid LLP
20090067250 - Memory devices with page buffer having dual registers and method of using the same: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the... Agent: Marger Johnson & Mccollom, P.C.
20090067249 - Memory with multi-page read: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.... Agent: Schwegman, Lundberg & Woessner/micron
20090067248 - Program method of flash memory device: In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string... Agent: Townsend And Townsend And Crew, LLP
20090067252 - Fuse data acquisition: One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing... Agent: Brooks, Cameron & Huebsch , PLLC
20090067251 - Reducing noise in semiconductor devices: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the... Agent: Brooks, Cameron & Huebsch , PLLC
20090067253 - Method for non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090067254 - Non-volatile memory device and a method of programming a multi level cell in the same: A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator... Agent: Townsend And Townsend And Crew, LLP
20090067255 - Nonvolatile semiconductor memory including memory cell for storing multilevel data having two or more values: A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090067256 - Thin gate stack structure for non-volatile memory cells and methods for forming the same: Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090067257 - Flash memory device and method of operating the same: A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number... Agent: Lowe Hauptman Ham & Berner, LLP
20090067259 - Semiconductor memory device configured to reduce current consumption associated with critical evaluating of data write operations: A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a... Agent: Ladas & Parry LLP
20090067258 - Semiconductor memory device having a current consumption reduction in a data write path: The present invention describes a semiconductor memory device that can reduce current consumption occurring in a data write path. The semiconductor memory device includes a write path over which any one of general data and representative data corresponding to a particular mode is transferred in correspondence with a prescribed pad.... Agent: Ladas & Parry LLP
20090067260 - Buffer control circuit of memory device: Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090067261 - Multi-port memory device: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090067262 - Voltage generating unit of semiconductor memory device: A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference... Agent: Rabin & Berdo, PC
20090067263 - Core voltage discharge driver: A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal... Agent: Rabin & Berdo, PC
20090067264 - Semiconductor memory device with normal and over-drive operations: A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and... Agent: Ladas & Parry LLP
20090067265 - Semiconductor storage device: A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the... Agent: Mcdermott Will & Emery LLP
20090067266 - Memory controller self-calibration for removing systemic influence: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as,... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090067267 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090067268 - Apparatus and method for controlling data strobe signal: Provided are an apparatus and method for controlling a data strobe signal. The apparatus includes a period measurement unit measuring a period of an input clock signal or data strobe signal; a controller determining a read delay time, a setup margin delay time, and a hold margin delay time of... Agent: Sughrue Mion, PLLC
20090067269 - Memory column redundancy scheme: A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the... Agent: Cantor Colburn LLP-ibm Burlington
20090067270 - Structure for improved memory column redundancy scheme: A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry... Agent: Cantor Colburn LLP-ibm Burlington
20090067272 - Memory compiler redundancy: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on... Agent: Stolowitz Ford Cowger LLP
20090067271 - Semiconductor device: A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is... Agent: Sughrue Mion, PLLC
20090067273 - Semiconductor storage device: A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply... Agent: Mcdermott Will & Emery LLP
20090067274 - Memory device having an evaluation circuit: A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090067275 - Projection display apparatus: A projector 100 includes an image projection unit 6 that projects an image using light from a discharge lamp 1, a ballast 2 that controls a supply voltage supplied to the discharge lamp 1, a system controller 3 that controls a command signal outputted to the ballast 2, a volatile... Agent: Morgan & Finnegan, L.L.P.
20090067276 - Storing operational information in an array of memory cells: The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a... Agent: Brooks, Cameron & Huebsch , PLLC
20090067278 - data output circuit for semiconductor memory apparatus: A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal... Agent: Baker & Mckenzie LLP Patent Department
20090067277 - Memory device command decoding system and memory device and processor-based system using same: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power... Agent: Dorsey & Whitney LLP Intellectual Property Department03/05/2009 > patent applications in patent subcategories.
20090059639 - Tree-style and-type match circuit device applied to content addressable memory: A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The tree-style AND-type match circuit increases the parallelism of the... Agent: Rosenberg, Klein & Lee
20090059640 - Semiconductor device having multiport memory: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20090059642 - Memory controller with multi-modal reference pad: A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are... Agent: Silicon Edge Law Group, LLP
20090059641 - Memory device interface methods, apparatus, and systems: Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality... Agent: Schwegman, Lundberg & Woessner/micron
20090059643 - Semiconductor memory device: A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output... Agent: Mcdermott Will & Emery LLP
20090059644 - Semiconductor memory device having vertical transistors: A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory... Agent: Mcginn Intellectual Property Law Group, PLLC
20090059645 - One time programmable memory: A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20090059648 - Ferroelectric semiconductor storage device: This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059646 - Semiconductor integrated circuit: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059649 - Semiconductor memory device and electronic apparatus: A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal,... Agent: Harness, Dickey & Pierce, P.L.C
20090059647 - Semiconductor storage device: A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059650 - Memory device, semiconductor device, and electronic device: To provide a memory device which can maintain data accurately even when memory characteristics of a memory element deteriorate over time. The memory device includes a memory cell 100, a reading circuit 103, a power supply line 104, a first signal line 105, a second signal line 102, and an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.
20090059652 - Resistive memory cell array with common plate: In the present method of changing the state of a resistive memory device which is capable of adopting an erased, relatively higher resistance state and a programmed, relatively lower resistance state, the resistive memory device having first and second electrodes and an active layer between the first and second electrodes,... Agent: Paul J. Winters
20090059651 - Semiconductor memory device and method of writing into the same: A method of writing into a semiconductor memory device, which includes a resistance memory element 14 which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage; a transistor 12 including a... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090059653 - Multi-port dynamic memory methods: A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to... Agent: Ryan, Mason & Lewis, LLP
20090059654 - High density magnetic memory based on nanotubes: A novel magnetic memory cell utilizing nanotubes as conducting leads is disclosed. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access... Agent: Hahn And Moodley, LLP
20090059655 - Memory cell and semiconductor memory device having thereof memory cell: Conventional semiconductor memory devices have a problem of a data read failure caused by a leak current. To address this problem, a semiconductor memory device of the present invention including memory cells each formed of a transfer transistor, a load transistor and a drive transistor. Each of the memory cells... Agent: Mcginn Intellectual Property Law Group, PLLC
20090059656 - Method and structure for improved lithographic alignment to magnetic tunnel junctions in the integration of magnetic random access memories: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over... Agent: Graham S. Jones, Ii
20090059657 - Cmos storage devices configurable in high performance mode or radiation tolerant mode: A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline... Agent: Schmeiser, Olsen & Watts
20090059658 - Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory: An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a... Agent: F. Chau & Associates, LLC
20090059659 - Spin transistor and magnetic memory: A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059660 - Reducing the impact of interference during programming: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior... Agent: Vierra Magen/sandisk Corporation
20090059662 - Multi-level cell memory devices and methods using sequential writing of pages to cells sharing bit buffers: An apparatus includes a nonvolatile memory including a plurality of memory cells, each configured to store data having at least two bits and a control circuit configured to write data to a first memory cell connected to a wordline of the nonvolatile memory and to then write data to a... Agent: Myers Bigel Sibley & Sajovec
20090059664 - Electrically erasable programmable read-only memory (eeprom) cell and methods for forming and reading the same: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first... Agent: F. Chau & Associates, LLC
20090059665 - Semiconductor memory: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating... Agent: Buchanan, Ingersoll & Rooney PC
20090059666 - Memory cell array and non-volatile memory device: A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell... Agent: Volentine & Whitt PLLC
20090059667 - Memory cell array and non-volatile memory device: A memory cell array is disclosed which includes a plurality of memory banks, each memory bank including a plurality of logical sectors. The memory cell array includes a plurality of sub-memory banks, wherein each one of the plurality of sub-memory banks includes a plurality of physical sectors, and each one... Agent: Volentine & Whitt PLLC
20090059668 - Virtual ground array memory and programming method thereof: A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell... Agent: Bacon & Thomas, PLLC
20090059669 - Nand type nonvolatile semiconductor memory device having sideface electrode shared by memory cells: An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is disclosed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059670 - Nonvolatile semiconductor memory device: There is provided a nonvolatile semiconductor memory device which can read and verify a cell with a negative threshold voltage by biasing voltages of a source line and well line to a positive voltage. The nonvolatile semiconductor memory device includes a voltage control circuit which applies a select gate voltage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090059671 - Method of programming non-volatile memory device: A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in... Agent: Harness, Dickey & Pierce, P.L.C
20090059661 - Sequence detection for flash memory with inter-cell interference: A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module... Agent: Harness, Dickey & Pierce P.L.C
20090059673 - Method of operating an integrated circuit for reading the logical state of a memory cell: In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.... Agent: Slater & Matsil, L.L.P.
20090059672 - Self-timed integrating differential current sense amplifier: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell.... Agent: Schwegman, Lundberg & Woessner / Infineon
20090059674 - Storage apparatus, controller and control method: Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20090059675 - Radiation hardened multi-bit sonos non-volatile memory: In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+... Agent: Andrews Kurth LLP
20090059676 - High-k capped blocking dielectric bandgap engineered sonos and monos: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric comprising a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090059677 - Semiconductor device: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other.... Agent: Miles & Stockbridge PC
20090059679 - Erasing method of non-volatile memory: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a... Agent: Jianq Chyun Intellectual Property Office
20090059678 - Memory cell arrangement, method for controlling a memory cell, memory array and electronic device: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged... Agent: Slater & Matsil LLP
20090059663 - Method for preventing memory from generating leakage current and memory thereof: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell... Agent: Rabin & Berdo, PC
20090059680 - Integrated circuit memory devices that support selective mode register set commands: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address... Agent: Myers Bigel Sibley & Sajovec
20090059684 - Method and apparatus for storing data in a write-once non-volatile memory: An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of... Agent: Ryan, Mason & Lewis, LLP
20090059681 - Semiconductor memory device: Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage.... Agent: Rabin & Berdo, PC
20090059683 - Semiconductor memory device: A semiconductor memory device that includes a first high voltage oscillator configured to generate a first control pulse in response to a first enable signal, a level shifter configured to generate a high voltage control pulse by boosting a level of the first control pulse using a source high voltage,... Agent: Mcdermott Will & Emery LLP
20090059682 - Semiconductor memory device having antifuse circuitry: A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators,... Agent: F. Chau & Associates, LLC
20090059685 - Sram bias for read and write: An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines and bit lines for accessing rows and columns of cells. A power supply controller has an input operable for receiving an operation... Agent: Texas Instruments Incorporated
20090059687 - Semiconductor memory device and layout method thereof: Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and... Agent: Harness, Dickey & Pierce, P.L.C
20090059686 - Sensing scheme for the semiconductor memory: The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell... Agent: Chih-ta Star Sung
20090059688 - Single-ended read and differential write scheme: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a... Agent: Ibm Corporation
20090059689 - Apparatus and method for transmitting/receiving signals at high speed: A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data... Agent: Mcdermott Will & Emery LLP
20090059690 - Methods and apparatuses for operating memory: In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC
20090059691 - Semiconductor integrated circuit and multi test method thereof: A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi... Agent: Baker & Mckenzie LLP Patent Department
20090059693 - Semiconductor memory device: A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090059692 - Semiconductor memory device and operation method of the same: A semiconductor memory device has a timing margin for internal operations. The semiconductor memory device can activate an internal control signal for controlling an external address sooner than an internal control signal for controlling an external command to secure a sufficient time for data access. The semiconductor memory device includes... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090059694 - Semiconductor memory device: A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090059696 - Multi-port memory device: There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090059695 - Semiconductor memory device and block management method of the same: A semiconductor memory device includes adjacent planes and a control module. The adjacent planes include a reserve field and a data field having multiple blocks. The blocks of each of the reserve and data fields are successively arranged over the adjacent planes to form a multi-plane operation group. The control... Agent: Volentine & Whitt PLLC
20090059697 - Method and apparatus for implementing sram cell write performance evaluation: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and... Agent: Ibm Corporation RochesterIPLaw Dept 917
20090059698 - Method for testing memory: A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090059699 - Semiconductor memory device and its test method: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090059700 - Precharge control circuit in semiconductor memory apparatus: A precharge circuit in a semiconductor memory apparatus includes a burst setting unit for controlling a state of a burst setting signal using delay elements in response to a burst start signal, wherein the delay elements operate in synchronization with a clock signal when the burst setting signal is deactivated,... Agent: Baker & Mckenzie LLP Patent Department
20090059701 - Core voltage discharger and semiconductor memory device with the same: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090059702 - Sense amplifier for semiconductor memory device: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a... Agent: Stanley P. Fisher Reed Smith LLP
20090059703 - Receiver circuit of semiconductor memory apparatus: A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a... Agent: Baker & Mckenzie LLP Patent Department
20090059704 - Calibration circuit and semiconductor memory device with the same: A calibration circuit is capable of correcting an error of a calibration operation by adjusting a calibration code generated thereby. The calibration circuit of a semiconductor memory device includes a code generator, a calibration resistor unit, and a variable resistor unit. The code generator is configured to generate a calibration... Agent: Rabin & Berdo, PC
20090059706 - Sram active write assist method for improved operational margins: A method is provided for controlling a voltage level supplied to a static random access memory (“SRAM”). In such method, when a column of the SRAM is selected for writing, a first p-type field effect transistor (“PFET”) and a second PFET can be operated to supply the power at a... Agent: International Business Machines Corporation Dept. 18g
20090059705 - Sram having active write assist for improved operational margins: A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected for a write operation. The... Agent: International Business Machines Corporation Dept. 18g
20090059707 - Power saving sensing scheme for solid state memory: Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of... Agent: Knobbe Martens Olson & Bear LLP
20090059709 - Address replacing circuit and semiconductor memory apparatus having the same: An address replacing circuit includes a sub-bank region selecting unit that allows a first sub-bank region or a second sub-bank region to be selectively activated, in response to a row address and first and second bits of a column address in accordance with operation modes a first column region activating... Agent: Baker & Mckenzie LLP Patent Department
20090059708 - Semiconductor integrated circuit including bank selection control block: A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up... Agent: Baker & Mckenzie LLP Patent Department
20090059710 - Semiconductor memory device: A semiconductor memory device having banks includes an address input path selection circuit in each of the banks, the address input path selection circuit including a signal input unit configured to selectively activate a Y-address input enable signal in response to a bank-specific read/write signal, and a latch unit configured... Agent: Rabin & Berdo, PC
20090059711 - Routing access with minimized bus area in multi-port memory device: A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set... Agent: Law Office Of Monica H Choi
20090059712 - Output driver: An output driver is applicable to two or more interface standards. The output driver includes a pre-driver configured to generate pull-up control signals and pull-down control signals according to a logic value of data to be output and a target resistance, and adjust slew rates of the pull-up control signals... Agent: Rabin & Berdo, PC
20090059713 - Ram macro and timing generating circuit thereof: A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to... Agent: Staas & Halsey LLPPrevious industry: Electric power conversion systems
Next industry: Agitating
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