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Static information storage and retrieval February patent applications/inventions, industry category 02/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/26/2009 > patent applications in patent subcategories.
20090052219 - Memory circuit arrangement and method for the production thereof: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the... Agent: Brinks Hofer Gilson & Lione/infineon Infineon
20090052218 - Semiconductor package having memory devices stacked on logic device: A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic... Agent: Volentine & Whitt PLLC
20090052220 - One-time programmable non-volatile memory: An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of... Agent: Edouard Garcia Attorney At Law
20090052221 - Semiconductor device including antifuse element: An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric... Agent: Sughrue Mion, PLLC
20090052222 - Memory element with thermoelectric pulse: A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell.... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20090052223 - Switching element, method of manufacturing the switching element, and memory element array: Disclosed is a switching element including: an insulative substrate; a first electrode and a second electrode provided to the insulative substrate; an interelectrode gap between the first electrode and the second electrode, comprising a gap of a nanometer order which causes switching phenomenon of resistance by applying a predetermined voltage... Agent: Crowell & Moring LLP Intellectual Property Group
20090052224 - Ferroelectric random access memory apparatus and method of driving the same: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a... Agent: Mills & Onello LLP
20090052227 - Non-volatile memory device and method for writing data thereto: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090052225 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device capable of suppressing parasitic currents in unselected memory cells, in cross-point array including memory cells comprising a two-terminal circuit having a variable resistor storing information according to electric resistance change due to electric stress. The memory cell comprises a series circuit of the variable resistive... Agent: Nixon & Vanderhye, PC
20090052228 - Operating process of organic device: An operating process of an organic device includes performing a programming process and an erasing process. The programming process includes steps of applying a first positive bias from the first electrode to the second electrode on the organic device so that a conductive state of the organic device is switched... Agent: Jianq Chyun Intellectual Property Office
20090052226 - Resistive random access memory device: Provided is a resistive random access memory device that includes a storage node connected to a switching device. The resistive random access memory device includes a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked, wherein a diffusion blocking layer is formed between the first... Agent: Harness, Dickey & Pierce, P.L.C
20090052229 - Mis-transistor-based nonvolatile memory device with verify function: A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a... Agent: Ladas & Parry
20090052230 - Integrated circuit including silicide region to inhibit parasitic currents: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.... Agent: Dicke, Billig & Czaja
20090052232 - Method for fabricating an integrated circuit including memory element with spatially stable material: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the... Agent: Edell, Shapiro & Finnan, LLC
20090052234 - Phase-change random access memory device and semiconductor memory device: A semiconductor memory device includes: first and second wiring layers extending in substantially parallel to each other in a first direction; a first semiconductor region formed in a part of a portion between the first and second wiring layers; a second semiconductor region formed on an opposite side to the... Agent: Mcginn Intellectual Property Law Group, PLLC
20090052236 - Resistance variable memory device and operating method thereof: Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the... Agent: Mills & Onello LLP
20090052235 - Resistance variable memory device and programming method thereof: Provided is a method of programming a resistance variable memory device. The resistance variable memory device includes a memory cell having multi states and a write driver outputting a program pulse for programming the memory cell into one of the multi states. The method of programming the resistance variable memory... Agent: Mills & Onello LLP
20090052231 - Semiconductor device: A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20090052233 - Semiconductor memory device and writing control method thereof: A semiconductor memory device includes: a plurality of write control circuits; a plurality of memory cells grouped in the write control circuits; a plurality of write drivers that write data to a corresponding memory cell when the write control circuit is activated; and a main control circuit that causes the... Agent: Sughrue Mion, PLLC
20090052237 - Magnetic memory device and magnetic memory apparatus: A magnetic memory element includes a laminated construction of a first electrode, a first pinned layer, a first intermediate layer, a memory layer, a second intermediate layer, a second pinned layer and a second electrode, and a third electrode coupled to the first intermediate layer and not directly coupled to... Agent: Nixon & Vanderhye, PC
20090052238 - Semiconductor integrated circuit: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold... Agent: Miles & Stockbridge PC
20090052240 - Flash memory device and method of programming the same: A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element... Agent: Marshall, Gerstein & Borun LLP
20090052243 - Method of controlling a memory cell of non-volatile memory device: A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to... Agent: Lee & Morse, P.C.
20090052241 - Method of operating a non-volatile memory device: In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage... Agent: Townsend And Townsend And Crew, LLP
20090052244 - Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data... Agent: Mcdermott Will & Emery LLP
20090052242 - Nand type nonvolatile semiconductor memory: A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090052245 - Cmos logic compatible non-volatile memory cell structure, operation, and array configuration: The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with... Agent: Perkins Coie LLP
20090052246 - Non-volatile shadow latch using a nanotube switch: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory... Agent: Wilmerhale/boston
20090052248 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper LLP (us )
20090052247 - Fuse circuit and flash memory device having the same: A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program... Agent: Townsend And Townsend And Crew, LLP
20090052249 - Semiconductor memory device having memory block configuration: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the... Agent: Mcdermott Will & Emery LLP
20090052250 - Semiconductor memory device and its manufacturing method: A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines... Agent: Mcdermott Will & Emery LLP
20090052251 - Integrated circuit memory devices including memory cells on adjacent pedestals having different heights, and methods of fabricating same: Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated... Agent: Myers Bigel Sibley & Sajovec
20090052252 - Methods of applying read voltages in nand flash memory arrays: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series,... Agent: Myers Bigel Sibley & Sajovec
20090052253 - Memory device and method reducing fluctuation of read voltage generated during read while write operation: Provided is a device and method for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation. A semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality... Agent: Harness, Dickey & Pierce, P.L.C
20090052254 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20090052255 - Program and erase methods for nonvolatile memory: Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying at least one programming pulse, at least one erasing pulse, at least one time delay, at least one... Agent: Harness, Dickey & Pierce, P.L.C
20090052256 - Threshold voltage digitizer for array of programmable threshold transistors: A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1.... Agent: Harness, Dickey & Pierce P.L.C
20090052239 - Nonvolatile memory devices and data reading methods: Methods of reading memory cell data and nonvolatile memory devices, which apply a low voltage to memory cells adjacent to a memory cell from which data may be read are provided. Methods of reading memory cell data of nonvolatile memory device include applying a first voltage to a control gate... Agent: Harness, Dickey & Pierce, P.L.C
20090052257 - Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof: A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is... Agent: Marger Johnson & Mccollom, P.C.
20090052258 - Systems, methods and devices for a memory having a buried select line: Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090052259 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing... Agent: Miles & Stockbridge PC
20090052260 - Semiconductor memory device: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.... Agent: Rabin & Berdo, PC
20090052261 - Data strobe buffer and memory system including the same: A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during... Agent: Volentine & Whitt PLLC
20090052262 - Semiconductor memory device: A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word... Agent: Mcdermott Will & Emery LLP
20090052264 - Refresh characteristic testing circuit and method for testing refresh using the same: A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic. The refresh characteristic test circuit includes a select signal generating unit for... Agent: Cooper & Dunham, LLP
20090052263 - Write driving circuit: A write driving circuit is provided to drive a global input/output line to write same data to memory cells according to a combination of a first test data signal and a second test data signal in a test mode, regardless of input data signals.... Agent: Cooper & Dunham, LLP
20090052265 - Semiconductor memory device changing refresh interval depending on temperature: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to... Agent: Arent Fox LLP
20090052266 - Temperature throttling mechanism for ddr3 memory: A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20090052267 - Method of simple chip select for memory subsystems: Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090052268 - System and method for providing temperature data from a memory device having a temperature sensor: A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP
20090052269 - Charge loss compensation methods and apparatus: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and... Agent: Attn: Daniel J. Polglaze Leffert Jay & Polglaze, P.A.
20090052270 - Method of flexible memory segment assignment using a single chip select: Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda
20090052271 - Semiconductor memory device: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an... Agent: Mcdermott Will & Emery LLP02/19/2009 > patent applications in patent subcategories.
20090046493 - Method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices: In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the... Agent: Patterson & Sheridan, LLP Suite 100
20090046494 - Semiconductor memory device: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory... Agent: Studebaker & Brackett PC
20090046496 - Nonvolatile memory device: A variable resistance element (1) whose resistance changes with application of a voltage pulse is brought to a low resistance state by applying an erase pulse to a path shown by the broken line through selection of selection transistors. An erase pulse limiting resistance (2) is inserted in the broken-line... Agent: Mcdermott Will & Emery LLP
20090046495 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell selecting circuit which selects a selected memory cell (M0) from a memory cell array (3); and a programming voltage applying circuit, which applies a row programming voltage and a column programming voltage to a selected word line and a selected bit... Agent: Nixon & Vanderhye, PC
20090046497 - System and method for reducing critical current or magnetic random access memory: A system and a method for reducing critical current of magnetic random access memory (MRAM) are disclosed. The magnetic device includes at least a pinned layer, a spacer layer and a free layer, and the material of the pinned layer and the free layer is perpendicularly anisotropic ferrimagnetic. The spacer... Agent: Rosenberg, Klein & Lee
20090046500 - Apparatus and method of nonvolatile memory device having three-level nonvolatile memory cells: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method... Agent: Volentine & Whitt PLLC
20090046499 - Integrated circuit including memory having limited read: An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.... Agent: Dicke, Billig & Czaja
20090046498 - Integrated circuit including memory having reduced cross talk: An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater... Agent: Dicke, Billig & Czaja
20090046501 - Low-cost non-volatile flash-ram memory: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.... Agent: Maryam Imam
20090046502 - Metal magnetic memory cell: A magnetic memory cell is provided. The memory cell includes a metal device, a first word line, and a second word line. The metal device includes a first magnetic layer having a first dipole; a second magnetic layer having a second dipole; and an conductive layer located between the first... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090046503 - Enhanced gated diode memory cells: A memory cell for use in an integrated circuit comprises a read transistor and a gated diode. The read transistor has a source terminal. The gated diode has a gate terminal in signal communication with the read transistor. A variable source voltage acts on the source terminal of the read... Agent: Ryan, Mason & Lewis, LLP
20090046504 - Dram tunneling access transistor: In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090046506 - Method and apparatus for programming nonvolatile memory: A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090046507 - Reducing effects of program disturb in a memory device: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage.... Agent: Leffert Jay & Polglaze, P.A.
20090046510 - Apparatus and method for multi-bit programming: Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit... Agent: Harness, Dickey & Pierce, P.L.C
20090046508 - Programming methods for multi-level flash eeproms: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into... Agent: Knobbe Martens Olson & Bear LLP
20090046509 - Technique to improve and extend endurance and reliability of multi-level memory cells in a memory device: A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating... Agent: Intel Corporation C/o Intellevate, LLC
20090046511 - Regulation of boost-strap node ramp rate using capacitance to counter parasitic elements in channel: Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of... Agent: Amin, Turocy & Calvin, LLP
20090046512 - Reliability system for use with non-volatile memory devices: A system and method which provides a non-volatile memory management system with the ability to monitor the health of a corresponding non-volatile memory and to safeguard data stored within the non-volatile memory when data integrity is at risk. The monitoring and safeguarding is provided via a crisis reliability mode module... Agent: Hamilton & Terrile, LLP
20090046513 - Enhanced erase for flash storage device: A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash controller interface receives a command for erasing the flash storage device and provides an erase command to... Agent: Stec, Inc. C/oIPLaw Dept.
20090046514 - Semiconductor memory device: A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of... Agent: Morrison & Foerster LLP
20090046515 - Nor flash memory device and method for fabricating the same: Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090046505 - Flash memory devices and operating methods that concurrently apply different predetermined bias voltages to dummy flash memory cells than to regular memory cells during erase: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than... Agent: Myers Bigel Sibley & Sajovec
20090046516 - Data writing method for flash memories: A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave... Agent: J C Patents, Inc.
20090046517 - Semiconductor device: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input... Agent: Miles & Stockbridge PC
20090046518 - Write voltage generating circuit and method: Provided are a write voltage generating circuit of a non-volatile memory cell and a write voltage generating method. The write voltage generating circuit includes a voltage generating unit providing a preliminary write voltage at a level below a defined target level, a voltage sensing unit receiving the preliminary write voltage... Agent: Volentine & Whitt PLLC
20090046519 - Method, device and system for configuring a static random access memory cell for improved performance: A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a... Agent: Texas Instruments Incorporated
20090046521 - Memory structure, programming method and reading method therefor, and memory control circuit thereof: The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates... Agent: Rabin & Berdo, PC
20090046520 - Semiconductor memory device having low power consumption type column decoder and read operation method thereof: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder... Agent: Lowe Hauptman Ham & Berner, LLP
20090046522 - Method for writing data in a non volatile memory unit: A method for writing data in a non volatile memory unit having memory pages includes a predetermined number of memory cells storing a memory word being a predetermined sequence of digital values. An erase operation erases the memory words in the memory page, setting the predetermined sequence of digital values... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20090046523 - Semiconductor memory device and control method thereof: A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and to which a third power supply voltage is supplied, a redundant cell array that includes a redundant... Agent: Arent Fox LLP
20090046524 - Multi-column decoder stress test circuit: The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column... Agent: Baker & Mckenzie LLP Patent Department
20090046525 - Wafer burn-in test circuit: A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among... Agent: Baker & Mckenzie LLP Patent Department
20090046526 - Word line driving circuit and method of testing a word line using the word line driving circuit: A method of testing a word line using a word line driving circuit comprising: activating a word line by activating a word line driving signal; floating the word line by activating a test mode signal after the activating of the word line; recording data having a predetermined logic value into... Agent: Baker & Mckenzie LLP Patent Department
20090046527 - Auto precharge circuit sharing a write auto precharge signal generating unit: In the auto precharge circuit, a plurality of read auto precharge signal generating units and a plurality of auto precharge signal output units share a single write auto precharge signal generating unit. Each read auto precharge signal generating unit logically combines an internal CAS command signal, an internal address signal... Agent: Ladas & Parry LLP
20090046528 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.... Agent: Baker & Mckenzie LLP Patent Department
20090046529 - Biasing and shielding circuit for source side sensing memory: A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge device, first and second biasing units, first and second voltage pull-down units, and a connection units. The pre-discharge device is for setting the voltage... Agent: Bacon & Thomas, PLLC
20090046530 - Resettable memory apparatuses and design: Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information... Agent: Synopsys, Inc./bstz Blakely Sokoloff Taylor & Zafman LLP
20090046531 - Circuit and method for controlling refresh periods in semiconductor memory devices: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh... Agent: Myers Bigel Sibley & Sajovec
20090046532 - Supply voltage for memory device: A device is provided including a memory cell, a first supply voltage generator, passively coupled to the memory cell, to provide the memory cell with a first supply voltage, and a second supply voltage generator, coupled to the memory cell, to provide the memory cell with a second supply voltage.... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052
20090046534 - Method of operating a memory apparatus, memory device and memory apparatus: A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information... Agent: Edell, Shapiro & Finnan, LLC
20090046533 - Multichip system and method of transferring data therein: Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data... Agent: Volentine & Whitt PLLC02/12/2009 > patent applications in patent subcategories.
20090040801 - Content addressable memory: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set... Agent: Qualcomm Incorporated
20090040803 - Semiconductor memory and method for operating a semiconductor memory: A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips... Agent: Slater & Matsil, L.L.P.
20090040802 - Semiconductor memory device, memory-mounted lsi and fabrication method for semiconductor memory device: The semiconductor memory device includes a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of... Agent: Mcdermott Will & Emery LLP
20090040804 - Fuse circuit: A fuse circuit in accordance with one embodiment of the present invention includes a first power supply liner a second power supply liner a current source connected between the first power supply line and an output terminal, a first transistor having a drain or a collector connected to the output... Agent: Young & Thompson
20090040805 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein... Agent: Townsend And Townsend And Crew, LLP
20090040806 - Reading circuit and method in a data-storage system: A reading circuit for reading a datum stored in a storage material. In the reading circuit, a generating stage generates a read electrical quantity to be applied to the storage material, and a sensing stage is configured to generate an output electrical quantity that is indicative of a charge variation... Agent: Graybeal Jackson LLP
20090040807 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090040809 - Storage device: A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP
20090040810 - Switched capacitor dram sense amplifier with immunity to mismatch and offsets: A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random... Agent: Schwegman, Lundberg & Woessner/micron
20090040816 - Method for driving a phase change memory device using various write conditions: A phase change memory device includes a phase change resistor configured to sense a change in crystallization state due to current flow in order to store data that corresponds to the crystallization state. The phase change memory device is driven by reading cell data of a selected unit cell using... Agent: Ladas & Parry LLP
20090040814 - Method for driving multi-level data to a phase change memory device: A phase change memory device including a phase change resistor senses a crystallization state that is changed according to supplied currents to store data corresponding to the crystallization state. The phase change memory device may receive and store multi-level data. The multi-level data is driven to the phase change memory... Agent: Ladas & Parry LLP
20090040817 - Method for efficiently driving a phase change memory device: A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state.... Agent: Ladas & Parry LLP
20090040819 - Nonvolatile memory device using resistive elements and an associated driving method: A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and... Agent: Volentine & Whitt PLLC
20090040820 - Phase change memory: A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary... Agent: Wang Law Firm, Inc.
20090040813 - Phase change memory device and operating method thereof: A phase change memory device and operation is described where the phase change memory device includes a phase change resistance cell storing data corresponding to a sensed crystallization state. The phase change memory device operates by reading data of a selected phase change resistance cell when in a write mode.... Agent: Ladas & Parry LLP
20090040811 - Phase change memory device having multiple reset signals and operating method thereof: A phase change memory device includes a cell array unit having a phase change resistance cell positioned at an intersection of a word line and a bit line. A write driving unit is configured to generate a single write voltage to the cell array unit when data to be written... Agent: Ladas & Parry LLP
20090040812 - Phase change memory device having write driving control signal corresponding to set/reset write time: A phase change memory device includes a phase change resistance cell configured to sense a crystallization state that changes in response to a current so that data corresponding to the crystallization state can be stored in the phase change resistance cell. A write driving control signal generating unit outputs a... Agent: Ladas & Parry LLP
20090040815 - Phase change memory device using a multiple level write voltage: A phase change memory device using a multiple level write voltage is described. The phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A voltage selection adjusting unit is configured to select... Agent: Ladas & Parry LLP
20090040818 - Time efficient phase change memory data storage device: A phase change memory device is presented that includes a phase change resistance cell array and a cache register. The phase change resistance cell array includes a phase change resistor configured to sense crystallization changed depending on currents so as to store data corresponding to resistance change. The cache register... Agent: Ladas & Parry LLP
20090040822 - Flash memory device having single page buffer structure and related programming operations: A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register... Agent: Volentine & Whitt PLLC
20090040821 - Low power multiple bit sense amplifier: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference... Agent: Leffert Jay & Polglaze, P.A.
20090040823 - Flash memory: A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash... Agent: North America Intellectual Property Corporation
20090040824 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end region to a second end region through the cell region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090040826 - Flash memory device and method of operating the same: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in... Agent: Townsend And Townsend And Crew, LLP
20090040827 - Flash memory device for remapping bad blocks and bad block remapping method: Provided are a flash memory device and a bad block remapping method thereof. The flash memory device includes: an address storage block detecting whether a block address provided from the outside is identical to an already stored block address, and then generating a repair signal according to a detection result;... Agent: Harness, Dickey & Pierce, P.L.C
20090040825 - Novel row redundancy scheme in a multichip integrated memory: Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects... Agent: Schwegman, Lundberg & Woessner / Atmel
20090040828 - Semiconductor memory device: A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first... Agent: Townsend And Townsend And Crew, LLP
20090040830 - Block decoder and semiconductor memory device including the same: A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device... Agent: Townsend And Townsend And Crew, LLP
20090040829 - Lateral pocket implant charge trapping devices: A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090040831 - Method of programming in a flash memory device: A method of programming in a flash memory device is disclosed. The method includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, verifying whether or not the first memory cell is programmed through a first verifying voltage,... Agent: Townsend And Townsend And Crew, LLP
20090040833 - Non-volatile memory device and programming method: Provided are a non-volatile memory device and a programming method. The programming method includes applying a program voltage to a selected word line, applying an elevated pass voltage to word lines adjacent to the selected word line in a plurality of word lines, and applying a pass voltage to remaining... Agent: Volentine & Whitt PLLC
20090040832 - Soft program method in a non-volatile memory device: A soft program method in a non-volatile memory device for performing a soft program step so as to improve threshold voltage distribution of an erased cell is disclosed. The soft program method in a non-volatile memory device includes performing a soft program for increasing threshold voltages of memory cells by... Agent: Townsend And Townsend And Crew, LLP
20090040834 - Semiconductor memory device: A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090040835 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090040836 - Nand flash memory device and method of programming the same: Provided are a NAND flash memory device and a method of programming the same. The NAND flash memory device may include a cell array including a plurality of pages; a page buffer storing program data of the pages; a data storage circuit providing program verification data to the page buffer;... Agent: Harness, Dickey & Pierce, P.L.C
20090040839 - Reading multi-cell memory devices utilizing complementary bit information: Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memory cells, non-overlapped. System components can measure distributions rendered non-overlapped to... Agent: Amin, Turocy & Calvin, LLP
20090040837 - System and method for reducing pin-count of memory devices, and memory device testers for same: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090040838 - Delay locked operation in semiconductor memory device: A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling... Agent: Mcdermott Will & Emery LLP
20090040840 - Semiconductor memory device and method of compensating for signal interference thereof: A semiconductor memory device includes a memory cell array including a plurality of memory cell array blocks, a plurality of pairs of first data lines for transceiving data with corresponding memory cell array blocks, a plurality of column selection signal lines disposed in an orthogonal direction to the pairs of... Agent: F. Chau & Associates, LLC
20090040842 - Enhanced write abort mechanism for non-volatile memory: In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage... Agent: Brinks Hofer Gilson & Lione/sandisk
20090040843 - Enhanced write abort mechanism for non-volatile memory: In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage... Agent: Brinks Hofer Gilson & Lione/sandisk
20090040841 - Method of operating an integrated circuit having at least one memory cell: Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one... Agent: Slater & Matsil, L.L.P.
20090040844 - Output control device: An output controller includes a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe... Agent: Mcdermott Will & Emery LLP
20090040845 - Column path circuit: A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal... Agent: Marshall, Gerstein & Borun LLP
20090040847 - Output enable signal generating circuit and method of semiconductor memory apparatus: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output... Agent: Baker & Mckenzie LLP Patent Department
20090040846 - Programmable control block for dual port sram application: A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that... Agent: Townsend And Townsend And Crew LLP/ 015114
20090040848 - Semiconductor memory device: A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to... Agent: Mcdermott Will & Emery LLP
20090040852 - Semiconductor device and system: First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and... Agent: Arent Fox LLP
20090040849 - Semiconductor memory, test method of semiconductor memory and system: Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output... Agent: Arent Fox LLP
20090040850 - Semiconductor memory, test method of semiconductor memory and system: An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column... Agent: Arent Fox LLP
20090040851 - Semiconductor memory, test method of semiconductor memory and system: Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples... Agent: Arent Fox LLP
20090040853 - Method of precharging local input/output line and semiconductor memory device using the method: A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The... Agent: Marger Johnson & Mccollom, P.C.
20090040854 - Sense amplifier circuit: The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to... Agent: Fletcher Yoder (micron Technology, Inc.)
20090040855 - Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory: A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic... Agent: Strategic Patent Group, P.C.
20090040856 - Semiconductor memory device changing refresh interval depending on temperature: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to... Agent: Arent Fox LLP
20090040857 - Integrated circuit including decoupling capacitors that can be disabled: An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in response to the decoupling capacitor increasing the standby current of the integrated circuit.... Agent: Dicke, Billig & Czaja
20090040858 - Sram device with a power saving module controlled by word line signals: An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage... Agent: K & L Gates LLP
20090040859 - Backup for volatile state retention in the absence of primary circuit power: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power... Agent: North Weber & Baugh LLP
20090040861 - Method of operating a memory apparatus, memory device and memory apparatus: A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating... Agent: Edell, Shapiro & Finnan, LLC
20090040860 - Semiconductor memory apparatus capable of selectively providing decoded row address: A semiconductor memory apparatus includes a first bank block including a first bank group, a second bank block including a second bank group, and an address control unit that receives an address signal to selectively provide a decoded row address signal to the first bank block or the second bank... Agent: Baker & Mckenzie LLP Patent Department02/05/2009 > patent applications in patent subcategories.
20090034311 - Low power ternary content-addressable memory (tcam): An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a plurality of ternary content addressable memory (TCAM) bitcells (100). The plurality of TCAM bitcells (100) each include bit storage including a pair of memory cells (102-0, 102-1)... Agent: Texas Instruments Incorporated
20090034315 - Memory core and semiconductor memory device having the same: A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line... Agent: Mills & Onello LLP
20090034314 - Semiconductor memory device: To secure a sufficient read-out voltage even when lines are arranged at a fine pitch, a semiconductor memory device including: a memory array in which a plurality of memory cells are arranged in rows and columns; and a plurality of bit lines associated with the respective columns of the memory... Agent: Mcdermott Will & Emery LLP
20090034313 - Semiconductor memory device and layout structure of sub-word line control signal generator: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At... Agent: Marger Johnson & Mccollom, P.C.
20090034312 - Single-event upset immune static random access memory cell circuit, system, and method: A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain... Agent: Graybeal Jackson LLP
20090034316 - Memory: A memory includes a plurality of word lines, a plurality of bit lines so arranged as to intersect with the plurality of word lines, a plurality of memory cells arranged on positions where the word lines and the bit lines intersect with each other respectively and selection circuits connected to... Agent: Mcdermott Will & Emery LLP
20090034317 - Semiconductor storage device and method of fabricating the same: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first... Agent: Mcdermott Will & Emery LLP
20090034318 - Switching device, rewritable logic integrated circuit, and memory device: A switching device according to the present invention includes ion conductive layer 23 containing titanium oxide, first electrode 21 provided in contact with ion conductive layer 23, and second electrode 22 provided in contact with ion conductive layer 23 and which can supply metal ions to ion conductive layer 23.... Agent: Sughrue Mion, PLLC
20090034319 - Phase change memory device having schottky diode and method of fabricating the same: A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change... Agent: Marger Johnson & Mccollom, P.C.
20090034320 - Resistance change memory and write method of the same: A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090034322 - Magnetic random access memory and operation method: A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic... Agent: Jianq Chyun Intellectual Property Office
20090034321 - Magnetoresistive element with a biasing layer: An improved magnetoresistive element may include a pinned magnetic structure, a free magnetic structure, and a spacer layer coupled between the pinned magnetic structure and the free magnetic structure, where the free magnetic structure includes (i) a synthetic anti-ferromagnetic structure (SAF) including two or more anti-ferromagnetically coupled ferromagnetic layers, and... Agent: Honeywell International Inc.
20090034324 - Nonvolatile memory devices that include a write circuit that writes data over multiple write periods using pulses whose peaks do not coincide with each other: Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the... Agent: Myers Bigel Sibley & Sajovec
20090034323 - Phase change memory with dual word lines and source lines and method of operating same: A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090034325 - Programmable matrix array with chalcogenide material: A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a... Agent: Ovonyx, Inc
20090034326 - Methods and apparatus for thermally assisted programming of a magnetic memory device: A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so... Agent: Baker & Mckenzie LLP Patent Department
20090034327 - Thermal-emitting memory module, thermal-emitting module socket, and computer system: The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module socket. An embodiment of the thermal-emitting module includes: a module substrate having electrically-conductive traces; and a semiconductor device disposed on the module substrate and coupled to... Agent: Volentine & Whitt PLLC
20090034328 - Memory system protected from errors due to read disturbance and reading method thereof: A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, and copying... Agent: F. Chau & Associates, LLC
20090034331 - Nand memory device column charging: Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read... Agent: Schwegman, Lundberg & Woessner/micron
20090034329 - Semiconductor memory device capable of suppressing peak current: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090034330 - Word line voltage generator and flash memory device including the same, and method of generating word line voltage thereof: A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a... Agent: Lowe Hauptman Ham & Berner, LLP
20090034332 - Semiconductor memory device: A reference cell outputs a reference current of a data reading current of a memory cell. A trimming data in accordance with the reference current is memorized in a non-volatile memory cell. A standard current generator outputs a standard current whose current quantity is adjusted in accordance with the trimming... Agent: Mcdermott Will & Emery LLP
20090034333 - Method for managing a non-volatile memory in a smart card: The invention concerns a method for managing access to a non-volatile memory (VNVM), characterized in that said non-volatile memory (VNVM) results from the association of a non-volatile memory of a first type (NVMA) comprising first characteristics of capacity and granularity, with a non-volatile memory of a second type (NVMB) comprising... Agent: Buchanan, Ingersoll & Rooney PC
20090034334 - Nonvolatile memory device having a plurality of memory blocks: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided... Agent: Ingrassia Fisher & Lorenz, P.C.
20090034335 - Semiconductor device and its control method: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the... Agent: Paul J. Winters
20090034336 - Flash memory device having improved bit-line layout and layout method for the flash memory device: Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including... Agent: Harness, Dickey & Pierce, P.L.C
20090034337 - Method, apparatus, and system for improved read operation in memory: Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline... Agent: Schwegman, Lundberg & Woessner, P.A.
20090034338 - System and method for reading memory: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a... Agent: Texas Instruments Incorporated
20090034340 - Non-volatile memory control device: A memory controller outputs an additional writing instruction to one of a plurality of non-volatile memories arbitrarily selected via a writing instruction output unit when a signal which rejects a writing operation is not outputted from writing controllers of the plurality of non-volatile memories for a certain period of time,... Agent: Mcdermott Will & Emery LLP
20090034339 - Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor: An erase operation in a non-volatile memory includes selecting a block on which to perform an erase operation, erasing the selected block, receiving test data corresponding to the selected block, determining a soft program verify voltage level based on the test data, and soft programming the erased selected block using... Agent: Freescale Semiconductor, Inc. Law Department
20090034341 - Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers: Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first... Agent: Harness, Dickey & Pierce, P.L.C
20090034343 - Data retention monitor: A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read... Agent: Dickstein Shapiro LLP
20090034344 - Methods and apparatus for strobe signaling and edge detection thereof: A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions... Agent: Rambus Lerner, David, Et Al.
20090034345 - Eight transistor sram cell with improved stability requiring only one word line: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a... Agent: International Business Machines Corporation
20090034347 - High speed dram architecture with uniform access latency: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device... Agent: Borden Ladner Gervais LLP Anne Kinsman
20090034346 - Memory read control circuit: A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of... Agent: Mcginn Intellectual Property Law Group, PLLC
20090034348 - Write driver circuit of an unmuxed bit line scheme: A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in... Agent: Stanzione & Kim, LLP
20090034349 - Semiconductor device: A memory module fast in random accesses, large in capacity, and low in fabricating cost. And the memory module can assure high security. The memory module consists of a flash memory, a dynamic random access memory, and a control circuit. The control circuit enables data transfer between the flash memory... Agent: Miles & Stockbridge PC
20090034342 - Memory device, control method for the same, control program for the same, memory card, circuit board and electronic equipment: A memory device includes a single or a plurality of memory chips. In the memory device (memory module), the single memory chip or each of the plurality of memory chips has a memory part storing control data such as specification data and function data, and control data stored on the... Agent: Staas & Halsey LLP
20090034350 - Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same: There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the... Agent: Neil Steinberg
20090034351 - Non-volatile memory device and method of handling a datum read from a memory cell: A memory device includes a pre-charge transistor for connecting/disconnecting the input line of a global data line driver to a supply voltage line. To reduce the flow of current through the pre-charge transistor even in a stand-by state, the pre-charge transistor is turned on when, at a same time, an... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20090034352 - Method and circuit for preventing high voltage memory disturb: A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The... Agent: Freescale Semiconductor, Inc. Law Department
20090034353 - Semiconductor memory device: A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is... Agent: Mcginn Intellectual Property Law Group, PLLC
20090034354 - Method, system, and apparatus for voltage sensing and reporting: A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is configured to sense and compare a reference voltage and an operating voltage. In one or more embodiments we voltage sensor is also configured to generate... Agent: Trask Britt, P.C./ Micron Technology
20090034355 - Integrated circuit including memory cells with tunnel fet as selection transistor: An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore... Agent: Dicke, Billig & Czaja
20090034356 - Dual-port memory: A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing... Agent: Ryan, Mason & Lewis, LLPPrevious industry: Electric power conversion systems
Next industry: Agitating
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