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Static information storage and retrieval January recently filed with US Patent Office 01/09

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/29/2009 > patent applications in patent subcategories. recently filed with US Patent Office

20090027940 - Memory module: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each.... Agent: Slater & Matsil, L.L.P.

20090027938 - Method and apparatus providing multi-planed array memory device: A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for... Agent: Dickstein Shapiro LLP

20090027939 - Multi-chip package reducing power-up peak current: Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read... Agent: Volentine & Whitt PLLC

20090027941 - Semiconductor memory device with power supply wiring on the most upper layer: A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090027942 - Semiconductor memory unit and array: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel... Agent: Wpat, PC

20090027944 - Increased switching cycle resistive memory element: An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of... Agent: Slater & Matsil, L.L.P.

20090027943 - Resistive memory including bidirectional write operation: A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to... Agent: Dicke, Billig & Czaja

20090027945 - Method and apparatus for implementing enhanced sram read performance sort ring oscillator (psro): A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell.... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090027946 - Method and apparatus for implementing enhanced sram read performance sort ring oscillator (psro): A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090027947 - Semiconductor memory device and driving method thereof: In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading... Agent: Sughrue Mion, PLLC

20090027948 - Integrated circuits, method of programming a cell, thermal select magnetoresistive element, memory module: An embodiment of the invention includes an integrated circuit that has a cell. The cell includes a first magnetic layer arrangement having a magnetization which corresponds to a predefined ground state magnetization, a non-magnetic spacer layer coupled to the first layer arrangement, a second magnetic layer arrangement disposed on the... Agent: Slater & Matsil, L.L.P.

20090027949 - Magnetic storage device: A magnetic storage device is provided which has significantly reduced power consumption. In the magnetic storage device, a yoke is arranged so as to circumferentially surround part of a line extending in an arbitrary direction, and a magneto-resistive element to which information can be written by utilizing a magnetic field... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20090027950 - Block erase for phase change memory: An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all... Agent: Ryan, Mason & Lewis, LLP

20090027955 - Non-volatile memory devices including stacked nand-type resistive memory cell strings and methods of fabricating the same: A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality... Agent: Myers Bigel Sibley & Sajovec

20090027953 - Phase change memory device: A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block... Agent: Ladas & Parry LLP

20090027954 - Phase change memory device with bit line discharge path: A phase change memory device includes a cell array. The cell array includes a phase change resistance cell formed at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a bit line discharge signal in a... Agent: Ladas & Parry LLP

20090027952 - Phase change memory device with reference cell array: A phase change memory device includes a plurality of bit lines and a reference bit line intersecting a plurality of word lines. A cell array block has a phase change resistance cell arranged where a word line and a bit line intersect. A reference cell array block is configured to... Agent: Ladas & Parry LLP

20090027951 - Reading phase change memories with select devices: A phase change memory including a threshold device, such as an ovonic threshold switch, and a storage device may be read. Reading the cell may involve applying a first voltage to a selected cell and then a second voltage, lower than the first voltage. The first voltage may be sufficient... Agent: Trop Pruner & Hu, PC

20090027956 - Resistance variable memory device reducing word line voltage: A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and... Agent: Volentine & Whitt PLLC

20090027960 - Cell deterioration warning apparatus and method: Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20090027963 - High performance multi-level non-volatile memory device: Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20090027962 - Multiple level cell memory device with single bit per cell, re-mappable memory block: A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode.... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20090027961 - Non-volatile memory cell programming method: A non-volatile memory cell programming method is provided. A memory cell programming method of programming 2-bit data in a memory cell having 4 threshold voltage distributions may comprise: a first program operation of programming a first bit of the 2-bit data in the memory cell by applying a first programming... Agent: Harness, Dickey & Pierce, P.L.C

20090027959 - Programming multilevel cell memory arrays: Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20090027965 - Row selector circuit for electrically programmable and erasable non volatile memories: The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity... Agent: Graybeal Jackson LLP

20090027964 - Semiconductor memory device having plural word lines arranged at narrow pitch and manufacturing method thereof: A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090027966 - Flash memory device: A bad block address of a flash memory device is stored through a fuse circuit and then compared with an input address in order to disable bad blocks. The flash memory device includes a bad block information unit for storing an address of a bad block, a comparator for comparing... Agent: Townsend And Townsend And Crew, LLP

20090027967 - Non-volatile memory device programming selection transistor and method of programming the same: A memory system includes a flash memory device and a memory controller for controlling the flash memory device. The flash memory device includes a cell string and a selection transistor connected in series to the cell string. The cell string includes multiple series-connected memory cells. The selection transistor has the... Agent: Volentine & Whitt PLLC

20090027968 - Nand flash memory device and method of operating the same: A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit... Agent: Townsend And Townsend And Crew, LLP

20090027969 - Method of using hot-carrier-injection degradation as a programmable fuse/switch: Method and apparatus for providing nonvolatile storage with a programmable transistor. The method includes receiving a data value to be stored in the programmable transistor and programming the programmable transistor to store the received data value. Programming includes applying a selected voltage to the programmable transistor. The selected voltage is... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090027970 - Programming based on controller performance requirements: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20090027958 - Voltage converter circuit and flash memory device having the same: A voltage conversion circuit includes a reference voltage generation unit for generating a reference voltage having a uniform level regardless of a level of an input voltage varying according to an operation mode; and a driver unit for generating and outputting an active voltage or a standby voltage using the... Agent: Townsend And Townsend And Crew, LLP

20090027957 - Voltage supply circuit and flash memory device including the same, and method of supplying operating voltage: A voltage supply circuit includes a voltage generator and a controller. The voltage generator is configured to pump an externally input voltage and store the pumped external voltage as a first voltage having a set voltage level, before power-up begins, or pump the external voltage, add the pumped voltage to... Agent: Townsend And Townsend And Crew, LLP

20090027971 - Apparatuses, computer program products and methods for reading data from memory cells: In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage... Agent: Harness, Dickey & Pierce, P.L.C

20090027972 - Wordline driver for a non-volatile memory device, a non-volatile memory device and method: A wordline driver, for a non-volatile memory device, comprises a wordline driver output, a first power source, adapted to provide an erase level voltage for erasing portions of the non-volatile memory device, a second power source, adapted to provide read and program level voltages for reading and programming portions of... Agent: Freescale Semiconductor, Inc. Law Department

20090027974 - Memory control method and memory control circuit: A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate... Agent: North America Intellectual Property Corporation

20090027973 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier... Agent: Amin, Turocy & Calvin, LLP

20090027975 - Method for driving phase change memory device: A method is disclosed for driving a phase change memory device including a phase change resistor. The method includes applying a trigger voltage to the phase change resistor for a first write time to preheat the phase change resistor, applying a first write voltage to the phase change resistor for... Agent: Ladas & Parry LLP

20090027976 - Threshold device for a memory array: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold... Agent: Unity Semiconductor Corporation

20090027977 - Low read current architecture for memory: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.... Agent: Unity Semiconductor Corporation

20090027978 - Semiconductor device and semiconductor signal processing apparatus: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred... Agent: Mcdermott Will & Emery LLP

20090027979 - Semiconductor memory device and data sensing method thereof: A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals.... Agent: Lee & Morse, P.C.

20090027980 - Semiconductor memory: Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and... Agent: Arent Fox LLP

20090027981 - Method of testing data paths in an electronic circuit: A method of testing a complex electronic circuit, comprising a plurality of transfer operators DMA—0, DMA—1, UDMA, Software routines executed by the processor, and a plurality of memory resources (M1, M2, M3, M4) forming a shared memory space 1 on which the various operators can work, comprises an initialization of... Agent: Lowe Hauptman & Berner, LLP

20090027982 - Semiconductor memory and test system: A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal... Agent: Arent Fox LLP

20090027983 - Half-select compliant memory cell precharge circuit: A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation.... Agent: Keusey, Tutunjian & Bitetto, P.C.

20090027984 - Semiconductor device: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large... Agent: Miles & Stockbridge PC

20090027985 - Semiconductor storage device: The semiconductor storage device according to the present invention comprises a switch provided to a bit line between a memory cells and a sense amplifier and capable of continuously varying a degree of conduction; and a switch control circuit for varying the degree of conduction of the switch in accordance... Agent: Studebaker & Brackett PC

20090027986 - Semiconductor memory device: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read... Agent: Stanley P. Fisher Reed Smith LLP

20090027987 - Memory device and testing: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20090027988 - Memory device, memory controller and memory system: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of... Agent: Arent Fox LLP

20090027989 - System and method to reduce dynamic ram power consumption via the use of valid data indicators: A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain... Agent: Qualcomm Incorporated

20090027990 - Adaptive voltage control for sram: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array,... Agent: Texas Instruments Incorporated

20090027991 - Information processing apparatus, memory unit erroneous write preventing method, and information processing system: To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage into a first operable voltage with which... Agent: Staas & Halsey LLP

20090027992 - Psram and method for operating thereof: Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090027993 - Semiconductor memory device and data storage method: According to an aspect of the present invention, there is provided a semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, including: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting... Agent: Mcginn Intellectual Property Law Group, PLLC

  
01/22/2009 > patent applications in patent subcategories. recently filed with US Patent Office

20090021972 - Memory array using mechanical switch and method for operating thereof: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word... Agent: Buchanan, Ingersoll & Rooney Pc

20090021974 - Semiconductor device: A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated... Agent: Miles & Stockbridge Pc

20090021973 - Semiconductor memory device: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each... Agent: Dickinson Wright Pllc James E. Ledbetter, Esq.

20090021975 - Method and media for improving ferroelectric domain stability in an information storage device: A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric... Agent: Fliesler Meyer LLP

20090021976 - Method of operating an integrated circuit, integrated circuit, and memory module: A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of... Agent: Slater & Matsil, L.l.p.

20090021977 - Phase change material containing carbon, memory device including the phase change material, and method of operating the memory device: Provided are a phase change material containing carbon (C), a memory device including the phase change material, and a method of operating the memory device. The phase change material contains a main compound and an additive, wherein the main compound is In—Sb—Te and the additive includes carbon (C). A content... Agent: Harness, Dickey & Pierce, P.L.C

20090021979 - Gate stack, capacitorless dynamic random access memory including the gate stack and methods of manufacturing and operating the same: Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer,... Agent: Harness, Dickey & Pierce, P.L.C

20090021978 - Multi-bit flash memory and reading method thereof: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then,... Agent: Rabin & Berdo, Pc

20090021981 - Nonvolatile memory device including circuit formed of thin film transistors: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.... Agent: Mcdermott Will & Emery LLP

20090021982 - Semiconductor memory device and data erase method thereof: A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090021983 - Word line compensation in non-volatile memory erase operations: Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one... Agent: Vierra Magen/sandisk Corporation

20090021985 - Internal voltage generator and control method thereof, and semiconductor memory device and system including the same: An internal voltage of a semiconductor memory device is controlled, where the internal voltage is set according to a reference voltage. The reference voltage is controlled according to first control data to increase the internal voltage to be higher than a target voltage in a power-up operation, and second control... Agent: Volentine & Whitt Pllc

20090021984 - Methods and structures for highly efficient hot carrier injection programming for non-volatile memories: Methods and structures for highly efficient Hot Carrier Injection (HCI) programming for Non-Volatile Memories (NVM) apply the main positive supply voltage Vcc to, the drain electrode of the NVM cell from the chip main voltage supply in contrast to the conventional method using a higher voltage than Vcc. The source... Agent: Macpherson Kwok Chen & Heid LLP

20090021986 - Operating method of non-volatile memory device: An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive... Agent: J C Patents, Inc.

20090021980 - Non-volatile memory and operating method thereof: A non-volatile memory and an operating method thereof. The non-volatile memory includes a memory cell array, a first dummy cell array, an address decoding unit and a synchronous programming circuit. The memory cell array includes a first memory cell, and the first dummy cell array includes a first dummy cell.... Agent: Bacon & Thomas, Pllc

20090021987 - Analog sensing of memory cells in a solid state memory device: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20090021988 - Nonvolatile memory device and method of operating fabricating the same: Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be... Agent: Harness, Dickey & Pierce, P.L.C

20090021991 - Memory device, control method for the same, control program for the same, memory card, circuit board and electronic equipment: A memory device having a single or a plurality of memory chips includes a memory part (control register, SPD memory unit) inside each memory chip, which memory part stores control data concerning the memory chip. The memory device enables writing-in or readout of the control data stored on the memory... Agent: Staas & Halsey LLP

20090021989 - Programmable bias for a memory array: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values... Agent: Freescale Semiconductor, Inc. Law Department

20090021990 - Memory with level shifting word line driver and method thereof: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having... Agent: Larson Newman Abel Polansky & White, LLP

20090021992 - Memory with data control: In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, Llc

20090021993 - Semiconductor memory device: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input... Agent: Katten Muchin Rosenman LLP

20090021995 - Early write method and apparatus: A write operation is performed in a memory device. During a first stage of the write operation, a signal is applied to gating circuitry at a first voltage level for coupling a data bus line to a bit line when the data bus line is unmasked and for decoupling the... Agent: Coats & Bennett/qimonda

20090021994 - Memory and method for programming the same: A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090021996 - Memory circuit, memory component, data processing system and method of testing a memory circuit: A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a... Agent: Slater & Matsil, L.l.p.

20090021997 - Methods and apparatus for improved write characteristics in a low voltage sram: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level... Agent: Gibson & Dernier L.l.p.

20090021998 - Memory system having incorrupted strobe signals: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input,... Agent: Mosaid Technologies Incorporated

20090021999 - Semiconductor device: Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area... Agent: Sughrue Mion, Pllc

20090022000 - Semiconductor storage device and test method therefor: Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation circuit unit which generates a signal... Agent: Young & Thompson

20090022001 - Semiconductor memory device: By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing... Agent: Mcdermott Will & Emery LLP

20090022002 - Semiconductor memory device: A semiconductor memory device is provided for minutely changing a refresh interval according to a detected temperature and thereby lowering its power consumption. A temperature detector detects a temperature of a chip and outputs the corresponding temperature signal. A reference temperature signal output unit outputs the corresponding reference temperature signal... Agent: Arent Fox LLP

20090022003 - Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same: Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.... Agent: Harness, Dickey & Pierce, P.L.C

20090022004 - Charge recycling method and driving circuit and low power memory using the same: A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second terminal of... Agent: Bacon & Thomas, Pllc

20090022005 - Apparatus and method of controlling bank of semiconductor memory: An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control... Agent: Venable LLP

20090022006 - Integrated logic circuit and method for producing an integrated logic circuit: An integrated logic circuit comprises a memory area, wherein the memory area comprises a plurality of groups of memory cells, each group of memory cells assigned an address. The memory area further comprises an address decoder having a plurality of address inputs for receiving an address and for selecting a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

  
01/15/2009 > patent applications in patent subcategories. recently filed with US Patent Office

20090016092 - Semiconductor memory device and local input/output division method: A semiconductor memory device includes: a memory cell array that is arrayed on a plurality of mats; an even number of redundancy Y-switch (YS) signal lines that are provided in three mat units and arranged in the bit line direction on the mat that is positioned in the middle among... Agent: Sughrue Mion, PLLC

20090016093 - Memory system and semiconductor integrated circuit: A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that... Agent: Mcdermott Will & Emery LLP

20090016094 - Selection device for re-writable memory: A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not... Agent: Unity Semiconductor Corporation

20090016095 - Non-volatile sram memory cell equipped with mobile gate transistors and piezoelectric operation: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090016096 - Integrated circuits; method for manufacturing an integrated circuit; method for decreasing the influence of magnetic fields; memory module: Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic... Agent: Slater & Matsil, L.L.P.

20090016097 - Magnetoelectric device and method for writing non-volatile information into said magnetoelectric device: This invention relates to a device comprising at least a first ferromagnetic layer (202) and an element (204) exchange-bias coupled to this layer in at least one place through an interface (208), for controlling the magnetic state of the ferromagnetic layer (202) in the coupling place with an electrical field... Agent: Moore & Van Allen PLLC

20090016098 - Magnetoresistive device: A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090016100 - Multi-level phase change memory device and related methods: Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively... Agent: Harness, Dickey & Pierce, P.L.C

20090016099 - Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices: In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification... Agent: Mills & Onello LLP

20090016101 - Reading technique for memory cell with electrically floating body transistor: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region.... Agent: Courtney Staniford & Gregory LLP

20090016103 - Msb-based error correction for flash memory system: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data... Agent: Myers Bigel Sibley & Sajovec

20090016104 - Nonvolatile semiconductor memory device and programming method thereof: A programming method of a multi-bit flash memory device includes programming multi-bit data into selected memory cells through pluralities of programming loops. In each programming loop, an increment of a programming voltage applied to the selected memory cells is varied in accordance with a result of program-verification for each data... Agent: Lee & Morse, P.C.

20090016102 - Nonvolatile semiconductor memory device which stores multi-value information: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit)... Agent: Myers Bigel Sibley & Sajovec

20090016107 - Methods of operating nonvolatile memory devices: Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is... Agent: Harness, Dickey & Pierce, P.L.C

20090016105 - Nonvolatile memory utilizing mis memory transistors capable of multiple store operations: A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to... Agent: Ladas & Parry LLP

20090016108 - Nonvolatile semiconductor memory: A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090016106 - Sub volt flash memory system: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other... Agent: Dla Piper US LLP

20090016109 - Semiconductor device and its control method: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the... Agent: Paul J. Winters

20090016111 - Flash memory device and program recovery method thereof: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the... Agent: Lee & Morse, P.C.

20090016112 - Method of programming a flash memory device: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is... Agent: Myers Bigel Sibley & Sajovec

20090016110 - Methods of reading data from non-volatile semiconductor memory device: A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage... Agent: Volentine & Whitt PLLC

20090016114 - Circuit and method of generating high voltage for programming operation of flash memory device: Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program voltage, a voltage distributor... Agent: Marger Johnson & Mccollom, P.C.

20090016113 - Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from... Agent: Dla Piper US LLP

20090016115 - Testing non-volatile memory devices for charge leakage: A method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to... Agent: Freescale Semiconductor, Inc. Law Department

20090016117 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090016116 - Method of programming and erasing a non-volatile memory array: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090016118 - Non-volatile dram with floating gate and method of operation: A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from... Agent: Dla Piper US LLP

20090016119 - Memory device performing write leveling operation: A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe... Agent: Mcdermott Will & Emery LLP

20090016120 - Synchronous semiconductor device and data processing system including the same: A synchronous semiconductor device includes: input buffers; a latch-signal generating circuit that generates a latch signal based on a clock signal; latch circuits that latch an address signal in response to the latch signal; delay circuits that supply the latch circuits with the address signal in synchronism with the latch... Agent: Mcginn Intellectual Property Law Group, PLLC

20090016121 - Semiconductor memory device and test method thereof: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used... Agent: Sughrue Mion, PLLC

20090016122 - Dual word line or floating bit line low power sram: Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in... Agent: Gibson & Dernier L.L.P.

20090016123 - Semiconductor device and method of controlling the same: A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main... Agent: Young & Thompson

20090016127 - Duty detection circuit, dll circuit using the same, semiconductor memory circuit, and data processing system: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle.... Agent: Sughrue Mion, PLLC

20090016128 - Semiconductor integrated circuits and non-volatile memory devices including semiconductor integrated circuits: A semiconductor integrated circuit may include: a mode register and a clock delay control circuit. The mode register may store latency information corresponding to a plurality of frequencies. The clock delay control circuit may generate a delay clock signal using an external clock signal and the latency information. The delay... Agent: Harness, Dickey & Pierce, P.L.C

20090016125 - Semiconductor memory device: A semiconductor memory device can determine whether control for supplying termination resistances is normally performed or not by applying a test signal. The device includes a termination resistance driving controller configured to receive a plurality of termination resistance setting signals in synchronization with an external clock and a delay locked... Agent: Rabin & Berdo, PC

20090016126 - Semiconductor memory device: A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on... Agent: Young & Thompson

20090016124 - Semiconductor memory device having on-die-termination device and operation method thereof: A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090016129 - Design structure for increasing fuse programming yield: A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the... Agent: Anthony England Suite A. Pmb 334

20090016130 - Memory device and method of testing a memory device: In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090016131 - Bit line sense amplifier of semiconductor memory device and control method thereof: A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing... Agent: F. Chau & Associates, LLC

20090016133 - Semiconductor memory and system: A first precharge circuit couples a bit line pair to a precharge voltage line in a standby period, and separates at least an access side of the bit line pair from the precharge voltage line in accordance with operation start of a word line driving circuit. A sense amplifier amplifies... Agent: Arent Fox LLP

20090016132 - Semiconductor memory devices, memory systems and computing systems including the same: A semiconductor memory device includes a reference current generating circuit configured to generate a bias signal in response to a precharge signal during a precharge operation. Each of a plurality of sense amplifier circuits is connected to a corresponding one of a plurality of bit lines. Each sense amplifier is... Agent: Harness, Dickey & Pierce, P.L.C

20090016135 - Oscillating device, method of adjusting the same and memory: An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference... Agent: Arent Fox LLP

20090016136 - Oscillation device, method of oscillation, and memory device: An oscillation device includes a first setting unit that outputs an oscillation period designation signal, a calculating unit that performs an arithmetic operation on the oscillation period designation signal, and an oscillating unit that generates an oscillation signal having a period based on the oscillation period designation signal subjected to... Agent: Arent Fox LLP

20090016134 - Semiconductor memory device: This disclosure concerns a semiconductor memory comprising memory cells; word lines connected to gates of the cells; n bit lines connected to the memory cells; sense amplifiers connected to the bit lines; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090016138 - Memory cells with power switch circuit for improved low voltage operation: Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source... Agent: Ajay Bhatia

20090016137 - Memory controller with programmable regression model for power control: A memory controller uses a throttling mechanism which estimates a throttling delay for achieving a target power consumption, and periodically blocks all memory commands for a number of clock cycles corresponding to the throttling delay. Idle memory ranks of the memory device are powered down while the memory commands are... Agent: Ibm Corporation (jvm)

20090016139 - Semiconductor storage device: A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply... Agent: Young & Thompson

20090016140 - Dynamic voltage adjustment for memory: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory... Agent: Freescale Semiconductor, Inc. Law Department

20090016141 - Methods and arrangements for enhancing power management systems in integrated circuits: Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC

20090016142 - Semiconductor memory device, and method of controlling the same: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage... Agent: Arent Fox LLP

20090016143 - Word line activation in memory devices: Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20090016144 - Semiconductor memory device: In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a... Agent: Mcdermott Will & Emery LLP

20090016145 - Integrated circuit device with a rom matrix: A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input coupled to... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090016146 - Latency counter, semiconductor memory device including the same, and data processing system: A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks... Agent: Mcginn Intellectual Property Law Group, PLLC

  
01/08/2009 > patent applications in patent subcategories. recently filed with US Patent Office

20090010036 - Semiconductor memory: A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010038 - Low resistance plate line bus architecture: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the... Agent: Texas Instruments Incorporated

20090010037 - Semiconductor memory device with ferroelectric device: A semiconductor memory device comprises a one-transistor (1-T) field effect transistor (FET) type ferroelectric device connected between a pair of bit lines and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer; a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090010039 - Non-volatile memory device: According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010040 - Resistance change memory device: A resistance change memory device includes: a memory chip having memory cells of a resistance change type; and a heater so attached to the memory chip as to apply a temperature bias to the memory chip.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010041 - Hybrid dram: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier... Agent: Macpherson Kwok Chen & Heid LLP

20090010042 - Semiconductor integrated circuit device: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090010043 - Configurable sram system and method: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example,... Agent: Downs Rachlin Martin PLLC

20090010046 - magnetic memory device with non-rectangular cross section current carrying conductors: Embodiments of the invention magnetic memory device, comprising: a plurality of magnetic memory cells, each comprising: a magnetic memory element capable of being flipped between two stable spin orientations under the influence of an applied magnetic field; and current-carrying conductors proximate the magnetic element to carry a current that induces... Agent: Hahn And Moodley, LLP

20090010045 - Magnetoresistive random access memory: A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010044 - Toggle magnetic random access memory and write method of toggle magnetic random access memory: A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the... Agent: Dickstein Shapiro LLP

20090010050 - Calibration system for writing and reading multiple states into phase change memory: A memory system includes phase change memory cells. A control module causes one of the phase change memory cells to be written using a write parameter, causes a resistance value of the one of the phase change memory cells to be read back, adjusts the write parameter, and causes the... Agent: Harness, Dickey & Pierce P.L.C

20090010048 - Memory device including a programmable resistance element: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times... Agent: Sughrue Mion, PLLC

20090010049 - Phase change memory device: A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage... Agent: Foley And Lardner LLP Suite 500

20090010051 - Reading a phase change memory: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some... Agent: Trop Pruner & Hu, PC

20090010047 - Writing circuit for a phase change memory: A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source... Agent: Quintero Law Office, PC

20090010052 - One-transistor type dram: A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090010053 - Combo memory cell: A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090010055 - One-transistor type dram: A one-transistor type DRAM comprises a floating body storage element configured to store data in a floating body in a SOI wafer, a plurality of access transistors each connected between a bit line and one end of the floating body storage element, a word line configured to control the floating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090010054 - Semiconductor memory device with ferroelectric device: A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090010056 - Method and apparatus for capacitorless double-gate storage: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.... Agent: Michaelson & Associates

20090010058 - Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same: A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be... Agent: Buchanan, Ingersoll & Rooney PC

20090010057 - Semiconductor memory device with memory cell having charge accumulation layer and control gate and memory system: A semiconductor memory device includes first memory cell transistors, a memory block, and word lines. Each of the first memory cell transistors has a stacked gate including a charge accumulation layer and a control gate and is capable of holding M bits (M≠2i, where i is a natural number and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010060 - Bit line decoder architecture for nor-type memory array: A bit line decoder for sensing states of memory cells of a memory array includes D control devices and a control module. The D control devices selectively communicate with (D−1) bit lines of the memory array and are arranged in first and second levels of the bit line decoder. (D−2)... Agent: Harness, Dickey & Pierce P.L.C

20090010061 - Bit line decoder architecture for nor-type memory array: A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder, a control module, and an isolation circuit. The first sub-decoder is adjacent to the memory array and includes D control devices arranged in a first of two levels of the bit line... Agent: Harness, Dickey & Pierce P.L.C

20090010062 - Bit line decoder architecture for nor-type memory array: A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders, R isolation circuits, a second sub-decoder, and a sensing circuit. The R first sub-decoders communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1.... Agent: Harness, Dickey & Pierce P.L.C

20090010059 - Memory arrangement, particularly for the non-volatile storage of uncompressed video and/or audio data: When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be fitted directly on the video camera without a long external cable connection and which is also able to be... Agent: Joseph J. Laks Thomson Licensing LLC

20090010063 - Nand type flash memory and write method of the same: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010064 - Nand flash cell structure: NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rds resistance and decreased “narrow width” effect, allowing for increased scaling of... Agent: Leffert Jay & Polglaze, P.A.

20090010065 - Non-volatile memory using multiple boosting modes for reduced program disturb: A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode.... Agent: Vierra Magen/sandisk Corporation

20090010066 - Flash memory device and method in which trim information is stored in memory cell array: A flash memory device which includes a memory cell array which stores data and trim information, and control logic which controls programming, erasing, and reading modes of the memory cell array. The control logic is operative to receive the trim information from the memory cell array in a power-up mode,... Agent: Volentine & Whitt PLLC

20090010067 - Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing: Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for... Agent: Vierra Magen/sandisk Corporation

20090010068 - Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing: Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for... Agent: Vierra Magen/sandisk Corporation

20090010069 - Semiconductor device and method for controlling a semiconductor device: The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the... Agent: Ingrassia Fisher & Lorenz, P.C.

20090010070 - Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low... Agent: Mcdermott Will & Emery LLP

20090010071 - Nonvolatile memory device and erasing method: Disclosed is an erasing method for a nonvolatile memory device that includes erasing selected memory cells and erase-verifying the selected memory cells after increasing their threshold voltage by application of a negative bulk bias voltage.... Agent: Volentine & Whitt PLLC

20090010073 - Non-volatile memory system including spare array and method of erasing a block in the same: Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This... Agent: Myers Bigel Sibley & Sajovec

20090010072 - Semiconductor device: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit... Agent: Miles & Stockbridge PC

20090010074 - Semiconductor memory device: A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090010075 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20090010076 - Semiconductor device and controlling method for the same: A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile... Agent: Ingrassia Fisher & Lorenz, P.C.

20090010077 - Shift register latch with embedded dynamic random access memory scan only cell: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090010079 - One-transistor type dram: A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090010078 - Semiconductor memory device: A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage;... Agent: Mcdermott Will & Emery LLP

20090010080 - Semiconductor memory device, and method of controlling the same: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage... Agent: Arent Fox LLP

20090010081 - Overdrive write method, write amplifier power generating circuit, and semiconductor memory device including the same: A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is... Agent: Sughrue Mion, PLLC

20090010082 - Data transfer apparatus in semiconductor memory device and method of controlling the same: A data transfer apparatus in a semiconductor memory device includes a DQ pad, a DQS pad, a DQ driver for transferring the data signal to the DQ pad according to a driver select signal, and a DQS driver for transferring data strobe signal to the DQS pad according to the... Agent: Marshall, Gerstein & Borun LLP

20090010083 - Clock circuitry for ddr-sdram memory controller: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information,... Agent: Schwegman, Lundberg & Woessner / Atmel

20090010084 - Apparatus for controlling activation of semiconductor integrated circuit: An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks... Agent: Venable LLP

20090010085 - Semiconductor integrated circuit device and redundancy method thereof: A semiconductor integrated circuit device includes a first fuse circuit, a second fuse circuit, and a control signal generating circuit which sends a first control signal and executes program such that the resistance value of the first fuse circuit becomes greater than the resistance value of the second fuse circuit,... Agent: Amin, Turocy & Calvin, LLP

20090010086 - Sense amplifier and semiconductor memory device having the same: A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled... Agent: F. Chau & Associates, LLC

20090010088 - Data reading circuit of toggle magnetic memory: A data reading circuit of a magnetic memory applicable for reading data of a magnetic memory includes a first transistor, a second transistor connected to the first transistor in series, a third transistor, a fourth transistor connected to the third transistor in series, a first transmission gate electrically connected to... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090010087 - Data write in control circuit for toggle magnetic random access memory: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090010089 - Apparatus and method to store information in a holographic data storage medium: A method is disclosed to store information in a holographic data storage medium. The method supplies a holographic data storage medium and provides information. The method defines an Active storage portion for the holographic data storage medium and establishes a threshold access interval. The method determines if the information was... Agent: Dale F. Regelman Quarles & Brady, LLP

20090010090 - Bucket brigade address decoding architecture for classical and quantum random access memories: In an address signal decoder for a RAM memory, address signals are decoded in a “bucket brigade” address decoding architecture in which the address signals or bits are sequentially sent along the same address decoding path. The inventive architecture comprises a set of node switches linked into a binary tree.... Agent: Law Offices Of Paul E. Kudirka

20090010091 - Address counter, semiconductor memory device having the same, and data processing system: An address counter includes FIFO units and first to third command counters that controls the groups. In the FIFO units, latch circuits including input gates and output gates are connected in parallel. The first command counter conducts any one of the input gates in response to a first internal command;... Agent: Sughrue Mion, PLLC

20090010092 - Address counter, semiconductor memory device having the same, and data processing system: An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurality of input... Agent: Sughrue Mion, PLLC

  
01/01/2009 > patent applications in patent subcategories. recently filed with US Patent Office

20090003025 - Dual bit line metal layers for non-volatile memory: Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are... Agent: Vierra Magen/sandisk Corporation

20090003027 - Production method for semiconductor storage device and semiconductor storage device: A pair of power supply lines that are orthogonal to the border with the cell array are placed, for each one-bit processing circuit of the data processing unit, in a semiconductor storage device such as SRAM or the like comprising a data processing unit for writing data to memory cells... Agent: Staas & Halsey LLP

20090003026 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively... Agent: Young & Thompson

20090003028 - Carbon nanotube fuse element: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low... Agent: Trop Pruner & Hu, PC

20090003029 - Semiconductor integrated circuit device: In a semiconductor integrated circuit device having a volatile memory therein, high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lines, and a memory cell that is... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090003031 - Computation processing circuit using ferroelectric capacitor: A computation processing device executes logic computation based upon input data X(t) and data X(t−1) stored in memory. A ferroelectric capacitor includes a first terminal and a second terminal, and provides a function as memory. A bit line driver switches the voltage to be applied to the first terminal or... Agent: Cantor Colburn, LLP

20090003030 - Methods for ferroelectric domain reading: Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20090003035 - Conditioning operations for memory cells: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20090003032 - Integrated circuit including resistivity changing material having a planarized surface: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode... Agent: Dicke, Billig & Czaja

20090003037 - Integrated circuit with memory having a current limiting switch: An integrated circuit with memory having a current limiting switch. One embodiment provides a memory cell having a programmable resistivity layer and a writing line. A switch is arranged between the resistivity layer and the writing line. The switch includes a control input connected to a select line. The switch... Agent: Dicke, Billig & Czaja

20090003036 - Method of making 3d r/w cell with reduced reverse leakage: A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element.... Agent: Foley And Lardner LLP Suite 500

20090003034 - Multiple write configurations for a memory cell: One embodiment of the present invention relates to a method of programming an array of memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, each of which can write at least two data states to the memory cells of the... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20090003033 - Quasi-differential read operation: A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate,... Agent: Thomas G. Eschweilr. Esq. Eschweiler & Associates, LLC

20090003038 - Capacitor supported precharching of memory digit lines: Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the... Agent: Garry J. Tuma Fish & Neave

20090003039 - Electromechanical memory, electric circuit using the same, and method of driving electromechanical memory: A memory element which has high affinity with a conventional semiconductor process, which has a switching function of completely interrupting electric conduction paths by in a mechanical manner, and in which nonvolatile information recording is enabled is realized. An electromechanical memory which is formed on a substrate, which is formed... Agent: Pearne & Gordon LLP

20090003040 - Method and system for encoding to eliminate parasitics in crossbar array memories: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data... Agent: Novak Druce Deluca + Quigg LLP

20090003041 - Semiconductor memory device and read method thereof: A semiconductor memory device comprises a plurality of memory cells each capable of storing at least three different states; a first sense amplifier for amplifying a ternary potential read out in accordance with a state stored in a selected memory cell based on a comparison with a first reference potential;... Agent: Foley And Lardner LLP Suite 500

20090003042 - Magnetic memory device using domain structure and multi-state of ferromagnetic material: Disclosed is a memory device using a multi-domain state of a semiconductor material, and more particularly to a magnetic memory device, in which a ferromagnetic layer for recording magnetic data serves as a sensing layer so as to have a simple structure, shorten a manufacturing process, and reduce the unit... Agent: Morgan & Finnegan, L.L.P.

20090003043 - Method for switching magnetic moment in magnetoresistive random access memory with low current: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090003045 - Cmos-process-compatible programmable via device: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer... Agent: Michael J. Chang, LLC

20090003046 - Memory with dynamic redundancy configuration: One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes... Agent: Eschweiler & Associates LLC

20090003048 - Nonvolatile memory device using a variable resistive element and associated operating method: A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory... Agent: Volentine & Whitt PLLC

20090003049 - Phase change memory device and program method thereof: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval.... Agent: Volentine & Whitt PLLC

20090003044 - Program method with locally optimized write parameters: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a... Agent: Eschweiler & Associates LLC

20090003047 - Resistance change memory device: A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090003050 - Floating body memory array: Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.... Agent: Intel Corporation C/o Intellevate, LLC

20090003051 - Semiconductor memory device and semiconductor device: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20090003052 - System that compensates for coupling based on sensing a neighbor using coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20090003053 - System that compensates for coupling based on sensing a neighbor using coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20090003054 - Double programming methods of a multi-level-cell nonvolatile memory: A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090003058 - Flash memory device and method for adjusting read voltage of flash memory device: A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of... Agent: Volentine & Whitt PLLC

20090003055 - Method for programming multi-level cell flash memory device: A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory... Agent: Townsend And Townsend And Crew, LLP

20090003057 - Non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same: Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation... Agent: Myers Bigel Sibley & Sajovec

20090003056 - Nonvolatile semiconductor memory device and programming method thereof: Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation... Agent: Volentine & Whitt PLLC

20090003060 - High density nor flash array architecture: In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions.... Agent: Trop Pruner & Hu, PC

20090003062 - Non-volatile semiconductor device: A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The... Agent: Harness, Dickey & Pierce, P.L.C

20090003059 - Segmented bit line for flash memory: A memory device including segmented bit lines with memory cells coupled to a data cache is provided. A segmented bit line includes a bias transistor to selectively connect the bit line to a source line. Further, a physical implementation showing a segmentation pattern of the memory device is also provided.... Agent: Cool Patent, P.C. C/o Intellevate

20090003061 - Select gate transistors and methods of operating the same: Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate,... Agent: Fletcher Yoder (micron Technology, Inc.)

20090003063 - Method and device for demultiplexing a crossbar non-volatile memory: A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping... Agent: Seed Intellectual Property Law Group PLLC

20090003064 - Flash memory device and method of programming flash memory device: A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column... Agent: Volentine & Whitt PLLC

20090003065 - Flash cell with improved program disturb: Memory cells, memory arrays, memory devices and methods are disclosed, such as those involving a memory cell comprising a floating gate comprising lightly doped polysilicon, wherein the lightly doped polysilicon has a substantially uniform doping concentration. One such memory cell further comprises a control gate and dielectric disposed between the... Agent: Fletcher Yoder (micron Technology, Inc.)

20090003066 - Non-volatile memory system and programming method of the same: A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells... Agent: Lee & Morse, P.C.

20090003067 - Non-volatile memory device for reducing layout area of global wordline decoder and operation method thereof: A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n... Agent: Lee & Morse, P.C.

20090003068 - Method for source bias all bit line sensing in non-volatile storage: Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring... Agent: Vierra Magen/sandisk Corporation

20090003069 - Non-volatile storage with source bias all bit line sensing: A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to... Agent: Vierra Magen/sandisk Corporation

20090003070 - Semiconductor memory device: A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which... Agent: Amin, Turocy & Calvin, LLP

20090003072 - Non-volatile memory device: A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon... Agent: Townsend And Townsend And Crew, LLP

20090003073 - Rd algorithm improvement for nrom technology: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number,... Agent: Empk & Shiloh, LLP C/o Landon Ip, Inc.

20090003074 - Scalable electrically eraseable and programmable memory (eeprom) cell array: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20090003071 - Semiconductor storage device and read voltage correction method: A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090003075 - Flash memory devices and programming methods that vary programming conditions in response to a selected step increment: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage... Agent: Myers Bigel Sibley & Sajovec

20090003076 - Memory device and reading method: A memory device according to an embodiment of the present invention, comprises a common source line current detection unit for detecting current in a common source line of a memory cell array and outputting a control signal; and a control unit for controlling an evaluation time for reading data of... Agent: Townsend And Townsend And Crew, LLP

20090003077 - Non-volatile memory device: A non-volatile memory device for adjusting level of a verifying voltage supplied to a word line in accordance with occurrence of a source line bouncing phenomenon is disclosed. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line... Agent: Townsend And Townsend And Crew, LLP

20090003078 - Program-verify method: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or... Agent: Fletcher Yoder (micron Technology, Inc.)

20090003079 - Method and circuit for performing read operation in a nand flash memory: Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first set of bit lines of the array of bit lines for performing the read operation. The first... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090003080 - Method of depressing read disturbance in flash memory device: A method of reading a NAND flash memory device includes a cell string having a drain selection transistor, a plurality of memory cells and a source selection transistor which are in series connected to each other. The method comprises the steps of applying a first voltage to a gate of... Agent: Townsend And Townsend And Crew, LLP

20090003081 - Non-volatile memory and method of manufacturing same: The number of process steps for manufacturing a non-volatile memory is reduced while the performance of the non-volatile memory is improved. The non-volatile memory has a memory cell in which first, second and third P-type diffusion regions are formed in an N-type well, a select gate is formed via a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090003083 - Memory cell with voltage modulated sidewall poly resistor: A two terminal nonvolatile memory cell includes a first electrode, a second electrode, a charge storage medium, and a resistive element. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes. A presence or absence of charge being stored in the... Agent: Foley And Lardner LLP Suite 500

20090003082 - Method of making memory cell with voltage modulated sidewall poly resistor: A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a... Agent: Foley And Lardner LLP Suite 500

20090003084 - Driving method of flash memory device: In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit... Agent: Marshall, Gerstein & Borun LLP

20090003085 - Nonvolatile memory system, semiconductor memory, and writing method: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090003086 - Semiconductor memory device including output driver: A semiconductor memory device has a data output device. The data output device is provided with a slew rate control unit for detecting a transition number of a plurality of output data to output slew rate control information; and an output driving unit for driving the plurality of output data... Agent: Mcdermott Will & Emery LLP

20090003087 - Memory device bit line sensing system and method that compensates for bit line resistance variations: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090003088 - Semiconductor memory device: A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and... Agent: Rabin & Berdo, PC

20090003089 - Semiconductor memory device having input device: A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090003090 - Impedance adjusting circuit and semiconductor memory device having the same: An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section;... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090003091 - Semiconductor device: There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data... Agent: Buchanan, Ingersoll & Rooney PC

20090003092 - Device selection circuit and method: Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals).... Agent: Intel Corporation C/o Intellevate, LLC

20090003093 - Fuse reading circuit: Correction data is written in fuse circuits of q bits. A reading circuit sequentially reads information of the fuse circuits through a selector and writes the information in a storage circuit. Therefore, read data is output from the storage circuit in parallel.... Agent: Cantor Colburn, LLP

20090003094 - Semiconductor memory device having refresh mode and method for driving the same: A semiconductor memory device can control the toggling of signals corresponding to internal addresses during an auto-refresh mode. The semiconductor memory device includes an internal address generator configured to generate a plurality of first word line driving information signals and a plurality of first to seventh address information signals, which... Agent: Rabin & Berdo, PC

20090003095 - Column access control apparatus having fast column access speed at read operation: A column access control apparatus comprises a column signal control unit for controlling a write CAS pulse signal and an internal CAS pulse signal in response to a first signal, and a column decoder for outputting a column decoding signal using an output signal of the column signal control unit... Agent: Cooper & Dunham, LLP

20090003097 - Output control signal generating circuit: An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used... Agent: Mcdermott Will & Emery LLP

20090003096 - Semiconductor memory device: A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second... Agent: Mcdermott Will & Emery LLP

20090003098 - Method for hiding defective memory cells and semiconductor memories: A method for hiding defective memory cells in a semiconductor memory having a plurality of memory cells coupled with word lines for controlling is suggested. In the method, at least one word line is determined, where one control signal selects the at least one defective memory cell. For hiding the... Agent: Slater & Matsil, L.L.P.

20090003101 - Apparatus and method of setting test mode in semiconductor integrated circuit: An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in... Agent: Baker & Mckenzie LLP Patent Department

20090003099 - Memory test mode for charge retention testing: One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20090003102 - Method for testing semiconductor memory device: A method for testing a semiconductor memory device is provided. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each word line is controlled by a corresponding control line and a corresponding driving line. The method includes selecting... Agent: Ingrassia Fisher & Lorenz, P.C.

20090003103 - Semiconductor device and semiconductor memory tester: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090003100 - Semiconductor memory device and method of inputting addresses therein: A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses... Agent: Rabin & Berdo, PC

20090003104 - Test circuit and method for use in semiconductor memory device: A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test... Agent: Harness, Dickey & Pierce, P.L.C

20090003106 - Precharge control circuit: A precharge control circuit includes a precharge control unit and a precharge unit. The precharge control unit controls and outputs a precharge signal in response to a read command signal, a write command signal, and a first signal. The precharge unit precharges local input/output lines in response to a signal... Agent: Cooper & Dunham, LLP

20090003105 - Semiconductor device: A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of... Agent: Miles & Stockbridge PC

20090003107 - Semiconductor device: A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any... Agent: Young & Thompson

20090003108 - Sense amplifier method and arrangement: In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20090003109 - Methods and apparatus for extending the effective thermal operating range of a memory: Systems, methods, and apparatus are provided for thermal regulation of a non-volatile memory IC. The systems and apparatus may include a thermal sensor on a memory IC; and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the... Agent: Dugan & Dugan, PC

20090003110 - Methods and apparatus for extending the effective thermal operating range of a memory: Systems, methods, and apparatus are provided for thermal regulation of a non-volatile memory IC. The systems and apparatus may include a thermal sensor on a memory IC; and a heating element coupled to the thermal sensor and adapted to heat the memory IC in response to a signal from the... Agent: Dugan & Dugan, PC

20090003111 - Noise accommodating information storing apparatus: An apparatus including a plurality of semiconductor devices coupled via a plurality of circuit paths to store information. Selected circuit paths of the plurality of circuit paths present increased resistance, the increased resistance being sufficient to cooperate with capacitance present in the apparatus to establish a resistive-capacitive (RC) time constant... Agent: Law Office Of Donald D. Mondul C/o Intellevate

20090003113 - Block-by-block leakage control and interface: In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts... Agent: Macpherson Kwok Chen & Heid LLP

20090003112 - Reduced signal level support for memory devices: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to... Agent: Intel Corporation C/o Intellevate, LLC

20090003114 - Apparatus and method for reducing power consumption using selective power gating: A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit... Agent: Freescale Semiconductor, Inc. Law Department

20090003115 - Power-gating media decoders to reduce power consumption: Embodiments of a system that reduces power consumption by power-gating media decoders are described. During operation of the system, a decoder circuit receives encoded audio data and outputs corresponding decoded audio data to a memory, which is electrically coupled to the decoder circuit. Moreover, control logic, which is electrically coupled... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP

20090003116 - Control circuit for refreshing voltages in a non-volatile memory during a standby mode and a method thereof: Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Intellevate, LLC

20090003117 - Semiconductor memory device: A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality... Agent: Rabin & Berdo, PC

20090003118 - Word line block select circuit with repair address decision unit: A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control... Agent: Cooper & Dunham, LLP

20090003119 - Pseudo dual-port memory: A pseudo dual-port memory device is disclosed. One embodiment provides an internal data RAM for a microprocessor, and a method for operating a memory device. In one embodiment, a memory device for a microprocessor or microcontroller comprises: a first part with memory cells that are single-port memory cells; and a... Agent: Dicke, Billig & Czaja

20090003120 - Power-saving semiconductor memory: A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.... Agent: Fiala & Weaver, P.l.l.c. C/o Intellevate

20090003122 - Address synchronous circuit capable of reducing current consumption in dram: An address synchronous circuit comprises an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of an address which is buffered in accordance with a clock... Agent: Cooper & Dunham, LLP

20090003121 - Column address control circuit capable of selectively enabling sense amplifier in response to column addresses: A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The... Agent: Cooper & Dunham, LLP

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