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Static information storage and retrieval December patents and inventions 12/08

20080316787 - Method and apparatus for address allotting and verification in a semiconductor device: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of... Agent: Ingrassia Fisher & Lorenz, P.C.

20080316788 - Semiconductor memory device and method for operating semiconductor memory device: A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section. The memory array section and the interface section are sealed in a package. The interface section... Agent: Rader Fishman & Grauer PLLC

20080316789 - Random access electrically programmable e-fuse rom: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can... Agent: Whitham, Curtis & Christofferson, P.C.

20080316790 - Semiconductor device and method of manufacturing the same and semiconductor manufacturing device: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM... Agent: Ingrassia Fisher & Lorenz, P.C.

20080316791 - Operating method of one-time programmable read only memory: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric... Agent: J C Patents, Inc.

20080316792 - Circuit for programming a memory element: An integrated circuit includes a memory element and a circuit. The circuit is configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance. The one or more pulses... Agent: Dicke, Billig & Czaja

20080316794 - Integrated circuit having multilayer electrode: An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater... Agent: Dicke, Billig & Czaja

20080316793 - Integrated circuit including contact contacting bottom and sidewall of electrode: An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode.... Agent: Dicke, Billig & Czaja

20080316797 - Memory element array: Disclosed is a memory element array comprising a plurality of memory elements arranged in an array, wherein the memory elements are switching elements each including a gap of nanometer order in which a switching phenomenon of resistance is caused by applying a predetermined voltage between electrodes, and the memory element... Agent: Crowell & Moring LLP Intellectual Property Group

20080316796 - Method of making high forward current diodes for reverse write 3d cell: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the... Agent: Foley And Lardner LLP Suite 500

20080316795 - Method of making nonvolatile memory device containing carbon or nitrogen doped diode: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory... Agent: Foley And Lardner LLP Suite 500

20080316798 - Nonvolatile semiconductor memory device: A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array,... Agent: Mcdermott Will & Emery LLP

20080316799 - Read-preferred sram cell design: A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20080316800 - Semiconductor memory device: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080316801 - Magnetic memory system using mram-sensor: The invention relates to a Magnetic memory system (1, 20) which comprises an information layer (13) and a sensor (2, 22) for cooperating with the information layer (13). The information layer (13) comprises a pattern of magnetic bits (4a, 4b, 4c, 4d, 24a, 24c, 24d) which constitutes an array of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080316805 - Electronic circuit with a memory matrix: An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080316802 - Memory device having drift compensated read operation and associated method: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC

20080316804 - Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices: m

20080316806 - Phase change memory device: A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor... Agent: Mcginn Intellectual Property Law Group, PLLC

20080316807 - Semiconductor memory device having metal-insulator transition film resistor: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition... Agent: Harness, Dickey & Pierce, P.L.C

20080316803 - Sensing circuit of a phase change memory and sensing method thereof: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory... Agent: Quintero Law Office, PC

20080316809 - High forward current diodes for reverse write 3d cell: A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell... Agent: Foley And Lardner LLP Suite 500

20080316808 - Nonvolatile memory device containing carbon or nitrogen doped diode: A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.... Agent: Foley And Lardner LLP Suite 500

20080316810 - Memory unit: A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has... Agent: J C Patents, Inc.

20080316811 - Method for operating non-volatile storage with individually controllable shield plates between storage elements: A method for controlling non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between... Agent: Vierra Magen/sandisk Corporation

20080316819 - Flash memory device capable of storing multi-bit data and single-bit data: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory... Agent: Volentine & Whitt PLLC

20080316817 - Method and system for programming non-volatile memory cells based on programming of proximate memory cells: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080316820 - Method of programming memory device: Provided is a method of programming a memory device. The method includes performing a program voltage applying operation; and performing a verifying operation, wherein a plurality of verifying operations are consecutively performed after a program voltage applying operation.... Agent: Harness, Dickey & Pierce, P.L.C

20080316815 - Methods of programming multilevel cell nonvolatile memory: A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to... Agent: Weaver Austin Villeneuve Sampson LLP

20080316813 - Multi-level cell serial-parallel sense scheme for non-volatile flash memory: A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.... Agent: Cool Patent, P.C. C/o Intellevate

20080316818 - Non-volatile memory device and method of operating: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and... Agent: Marger Johnson & Mccollom, P.C.

20080316814 - Program-verify sensing for a multi-level cell (mlc) flash memory device: According to some embodiments, a method and apparatus for program verify sensing disclosed. During a program verify sensing operation, a tracking signal may be generated to match a sense amplifier signal. A data stream from a sequence generator may be held at a pass/hold logic until the tracking signal reaches... Agent: Trop, Pruner & Hu, P.C.

20080316812 - Programming a memory with varying bits per cell: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals... Agent: Leffert Jay & Polglaze, P.A.

20080316816 - Systems for programming multilevel cell nonvolatile memory: A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to... Agent: Weaver Austin Villeneuve Sampson LLP

20080316821 - Nonvolatile storage device and bias control method thereof: A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080316822 - Memory system that detects bit errors due to read disturbance and methods thereof: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main... Agent: Myers Bigel Sibley & Sajovec

20080316824 - Non-volatile memory device and method of operating the same: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing... Agent: Harness, Dickey & Pierce, P.L.C

20080316825 - Semiconductor memory device: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between... Agent: Marger Johnson & Mccollom, P.C.

20080316823 - Storage device and circuit element switching method thereof: The present invention discloses a storage device and a circuit element switching method thereof. The storage device includes: a plurality of memory modules, wherein each of the plurality of memory modules includes a plurality of chip enable terminals; a memory control unit that includes a plurality of bank selection terminals;... Agent: North America Intellectual Property Corporation

20080316826 - Semiconductor device having transistor and capacitor of soi structure and storing data in nonvolatile manner: In a semiconductor device, a first transistor of an SOI structure has a source region, a drain region, a body region positioned between the source region and the drain region, and a gate electrode positioned above the body region. A first capacitor of the SOI structure has a first terminal... Agent: Mcdermott Will & Emery LLP

20080316828 - Memory in logic cell: Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The... Agent: Brooks, Cameron & Huebsch , PLLC

20080316827 - Non-volatile storage with individually controllable shield plates between storage elements: A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of... Agent: Vierra Magen/sandisk Corporation

20080316829 - System for verifying non-volatile storage using different voltages: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for... Agent: Vierra Magen/sandisk Corporation

20080316830 - Compensation method to achieve uniform programming speed of flash memory devices: Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of... Agent: Amin, Turocy & Calvin, LLP

20080316831 - Nonvolatile semiconductor device, system including the same, and associated methods: A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate... Agent: Lee & Morse, P.C.

20080316833 - Intelligent control of program pulse duration: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of... Agent: Vierra Magen/sandisk Corporation

20080316832 - Non-volatile storage system with intelligent control of program pulse duration: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of... Agent: Vierra Magen/sandisk Corporation

20080316834 - Bias circuits and methods for enhanced reliability of flash memory device: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in... Agent: Mills & Onello LLP

20080316835 - Concurrent multiple-dimension word-addressable memory architecture: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of... Agent: Qualcomm Incorporated

20080316836 - Ground biased bitline register file: In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when... Agent: RyderIPLaw C/o Intellevate, LLC

20080316838 - Redundancy memory cell access circuit and semiconductor memory device including the same: A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy... Agent: Law Office Of Monica H Choi

20080316837 - Semiconductor memory device capable of controlling potential level of power supply line and/or ground line: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control... Agent: Mcdermott Will & Emery LLP

20080316839 - Memory cell array and method of controlling the same: To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate... Agent: Young & Thompson

20080316840 - Input/output line sense amplifier and semiconductor memory device using the same: An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O... Agent: Cooper & Dunham, LLP

20080316841 - Memory device having data paths with multiple speeds: A memory device has multiple bi-directional data paths. One of the multiple bidirectional data paths is configured to transfer data at one speed. Another one of the multiple bidirectional data paths is configured to transfer data at another speed.... Agent: Schwegman, Lundberg & Woessner/micron

20080316842 - System, method, and computer program product for broadcasting write operations: A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this... Agent: Zilka-kotab, PC

20080316843 - Semiconductor memory device capable of operating in a plurality of operating modes and method for controlling thereof: A semiconductor memory device capable of operating in a plurality operating modes and a method for controlling the device may be provided. The semiconductor memory device may include a selecting unit and a plurality of control circuits operating in a plurality of operating modes. The selecting unit may transmit a... Agent: Harness, Dickey & Pierce, P.L.C

20080316845 - Memory row architecture having memory row redundancy repair function: The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the... Agent: North America Intellectual Property Corporation

20080316844 - Selection method of bit line redundancy repair and apparatus performing the same: A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type... Agent: Connolly Bove Lodge & Hutz LLP

20080316846 - Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable... Agent: Marger Johnson & Mccollom, P.C.

20080316847 - Sensing circuit of a phase change memory and sensing method thereof: A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor... Agent: Quintero Law Office, PC

20080316849 - Memory driving method and semiconductor storage device: This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080316848 - Semiconductor memory device and driving method therefor: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data; bit lines and word lines connected to the memory cells; sense amplifiers connected to the bit lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080316850 - System for retaining state data of an integrated circuit: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains... Agent: Farjami & Farjami LLP

20080316851 - Semiconductor memory device: Disclosed is a semiconductor memory device including a plurality of memory cells, each of which is connected to word lines of first and second ports and to bit lines of the first and second ports, and first and second inter-port switches for electrically connecting first bit lines of the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080316852 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080310207 - 3-d sram array to improve stability and performance: A design structure for a three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a... Agent: Whitham, Curtis, & Christofferson, P.C.

20080310209 - Circuit, biasing scheme and fabrication method for diode accesed cross-point resistive memory array: Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The... Agent: Dickstein Shapiro LLP

20080310208 - Process for erasing chalcogenide variable resistance memory bits: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less... Agent: Thomas J. D'amico Dickstein Shapiro Morin & Oshinsky LLP

20080310211 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080310210 - Semiconductor memory device and method of operation: A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between... Agent: Slater & Matsil, L.L.P.

20080310212 - Sram with asymmetrical pass gates: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain... Agent: Schmeiser, Olsen & Watts

20080310214 - Device and method of programming a magnetic memory element: Thus, the present disclosure provides a method of programming a memory array. At least one memory cell including a magnetic element is provided. At least one current source coupled to the magnetic element is provided. A unipolar current is supplied from the at least one current source to the magnetic... Agent: Haynes And Boone, LLP

20080310215 - Magnetic random access memory and write method of the same: A magnetic random access memory includes a memory unit including a memory cell array having a first memory cell for writing first information and a second memory cell for writing second information, and a controller connected to the memory unit, and configured to start supplying a write current in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080310216 - Memory element utilizing magnetization switching caused by spin accumulation and spin ram device using the memory element: Provided is a spin memory that has excellent durability. The spin memory includes a ferromagnetic word line, a nonmagnetic bit line that crosses the ferromagnetic word line, a wiring disposed so as to be opposed to the ferromagnetic word line, and a magnetoresistive element formed between the wiring and the... Agent: Stanley P. Fisher Reed Smith LLP

20080310213 - Method and system for providing spin transfer tunneling magnetic memories utilizing non-planar transistors: A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality... Agent: Strategic Patent Group, P.C.

20080310217 - Writing circuit for a phase change memory: A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to the first memory cell. The first switch device... Agent: Birch Stewart Kolasch & Birch

20080310218 - Semiconductor memory device and its data reading method: Disclosed herein is a semiconductor memory device including a plurality of magnetic memory elements, a control line group and a read driving circuit.... Agent: Rader Fishman & Grauer PLLC

20080310219 - Method and system for providing a magnetic element and magnetic memory being unidirectional writing enabled: A method and system for providing a magnetic element and memory utilizing the magnetic element are described. The magnetic element includes a reference layer, a nonferromagnetic spacer layer, and a free layer. The reference layer has a resettable magnetization that is set in a selected direction by a magnetic field... Agent: Strategic Patent Group, P.C.

20080310220 - 3-d sram array to improve stability and performance: A three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier... Agent: Whitham, Curtis & Christofferson, P.C.

20080310224 - Coarse and fine programming in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080310223 - Method for programming a multilevel memory: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than... Agent: Birch Stewart Kolasch & Birch

20080310226 - Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A... Agent: Myers Bigel Sibley & Sajovec

20080310225 - Programming of a solid state memory utilizing analog communication of bit patterns: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes preprogramming erased memory cells that are to be programmed... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080310222 - Programming rate identification and control in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080310227 - Semiconductor memory device and related programming method: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein... Agent: Volentine & Whitt PLLC

20080310228 - Memory with correlated resistance: Methods, systems, and devices are disclosed, such as a method of operating a memory device. In certain embodiments, such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the... Agent: Fletcher Yoder (micron Technology, Inc.)

20080310230 - Flash memory devices having three dimensional stack structures and methods of driving same: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided... Agent: Myers Bigel Sibley & Sajovec

20080310229 - Semiconductor memory device in which word lines are driven from either side of memory cell array: A semiconductor memory device includes a memory cell array, a first row decoder which drives the memory cell array, and a second row decoder which drives the memory cell array. The first and second row decoders simultaneously drive the memory cell array.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080310231 - Optimization of critical dimensions and pitch of patterned features in and above a substrate: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the... Agent: Dugan & Dugan, PC

20080310232 - Erase verify for memory devices: Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells,... Agent: Schwegman, Lundberg & Woessner / Atmel

20080310233 - Multiple select gates with non-volatile memory cells: Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series... Agent: Brooks, Cameron & Huebsch , PLLC

20080310234 - Nonvolatile memory device and methods of programming and reading the same: A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and... Agent: Volentine & Whitt PLLC

20080310221 - Reference current sources: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second... Agent: Fletcher Yoder (micron Technology, Inc.)

20080310235 - Sensing circuit for memories: A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of... Agent: J C Patents, Inc.

20080310236 - Subtraction circuits and digital-to-analog converters for semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes an adder with first and second inputs... Agent: Fletcher Yoder (micron Technology, Inc.)

20080310237 - Cmos compatible single-poly non-volatile memory: The present invention teaches a single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. The single-poly non-volatile memory cell in accordance with the present invention comprises a program transistor with a program terminal;... Agent: Perkins Coie LLP

20080310238 - Methods of programming data in a non-volatile memory device and methods of operating a nand flash memory device using the same: Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed... Agent: Myers Bigel Sibley & Sajovec

20080310239 - Device for writing data into memory and method thereof: A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data is divided into a plurality of segments. The segments are written into first memory cells of the... Agent: Joe Mckinney Muncy

20080310240 - Semiconductor memory device having i/o unit: A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080310241 - Semiconductor memory device having memory cell and reference cell connected to same sense amplifier and method of reading data thereof: A semiconductor memory device includes a sense amplifier, first and second bit lines connected to the sense amplifier, a first reference cell connected to the first bit line, and a second reference cell connected to the second bit line. A reference potential is simultaneously written to the first and second... Agent: Mcginn Intellectual Property Law Group, PLLC

20080310242 - Systems for programmable chip enable and chip address in semiconductor memory: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled... Agent: Vierra Magen/sandisk Corporation

20080310243 - Semiconductor memory device for reducing precharge time: A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second... Agent: Harness, Dickey & Pierce, P.L.C

20080310245 - Digital filters for semiconductor devices: A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.... Agent: Fletcher Yoder (micron Technology, Inc.)

20080310244 - Digital filters with memory: A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The... Agent: Fletcher Yoder (micron Technology, Inc.)

20080310246 - Programmable pulsewidth and delay generating circuit for integrated circuits: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at... Agent: Keusey, Tutunjian & Bitetto, P.C. Suite 210

20080304308 - Unipolar resistance random access memory (rram) device and vertically stacked architecture: One embodiment of the present invention includes a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode.... Agent: Law Offices Of Imam

20080304307 - Use of a symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory: A symmetrically resistive memory material (such as a phase change material) is described for use as a rectifying element for driving symmetric or asymmetric resistive memory elements in a crosspoint memory architecture. The crosspoint architecture has a plurality of electrodes and a plurality of crossbar elements, with each crossbar element... Agent: Ip Authority, LLC Ramraj Soundararajan

20080304309 - Semiconductor memory device: The sense amp circuit includes a first node given a first, positive constant voltage larger than a fixed potential before reading, a second node given a second, negative constant voltage smaller than the fixed potential before reading, and a third node to be connected to the first and second nodes... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080304311 - Integrated circuit including logic portion and memory portion: An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.... Agent: Dicke, Billig & Czaja

20080304310 - Memory having shared storage material: An integrated circuit includes a bit line, a plurality of access devices coupled to the bit line, and a plate of phase change material. The integrated circuit includes a plurality of phase change elements contacting the plate of phase change material and a plurality of first contacts. Each first contact... Agent: Dicke, Billig & Czaja

20080304312 - Resistance memory with tungsten compound and manufacturing: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080304313 - Semiconductor memory device: A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bit line direction. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080304314 - Semiconductor device and method comprising a high voltage reset driver and an isolated memory array: A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set... Agent: Texas Instruments Incorporated

20080304315 - Semiconductor memory device, method of writing data therein, and method of reading data therefrom: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080304320 - Memory cell and method of programming the same: A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell includes applying a... Agent: J C Patents, Inc.

20080304318 - Multi-level-cell trapping dram: A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set... Agent: Akin Gump LLP - Silicon Valley

20080304319 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality... Agent: Hogan & Hartson L.L.P.

20080304317 - Solid state memory utilizing analog communication of data values: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080304322 - Nand flash memory cell programming: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source... Agent: Schwegman, Lundberg & Woessner/micron

20080304321 - Serial flash memory device and precharging method thereof: Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in... Agent: Cantor Colburn, LLP

20080304323 - Method and apparatus for programming data of memory cells considering floating poly coupling: A method and an apparatus for programming data of memory cells considering coupling are provided. The method includes: calculating a change of a threshold voltage based on source data of the memory cells; converting source data which will be programmed based on the calculated change of the threshold voltage; and... Agent: Harness, Dickey & Pierce, P.L.C

20080304324 - Nonvolatile semiconductor memory device which realizes \"1\" write operation by boosting channel potential: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of cell units each including a preset number of memory cells and select gate transistors on drain and source sides. The nonvolatile semiconductor memory device includes a voltage control circuit to prevent occurrence of an erroneous write... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080304316 - Sensing with bit-line lockout control in non-volatile memory: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080304325 - Non-volatile memory with improved sensing having bit-line lockout control: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080304326 - Method of erasing in non-volatile memory device: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are... Agent: Marger Johnson & Mccollom, P.C.

20080304327 - Methods and apparatuses for refreshing non-volatile memory: Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20080304328 - Nonvolatile memory devices and methods of operating the same: Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode... Agent: Harness, Dickey & Pierce, P.L.C

20080304329 - Method for erasing and changing data of floating gate flash memory: A method for erasing data stored in the memory cells of the floating gate flash memory is disclosed. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a control... Agent: North America Intellectual Property Corporation

20080304338 - Semiconductor memory device: To provide a semiconductor memory device capable of increasing its drive capability at operating time while reducing a leak current at standby time without the s need to make a significant change to the design of an existing semiconductor memory device a semiconductor memory device having a memory cell comprises:... Agent: Staas & Halsey LLP

20080304331 - Semiconductor integrated circuit with full-speed data transition scheme for ddr sdram at internally doubled clock testing application: The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal... Agent: Saile Ackerman LLC

20080304332 - Semiconductor integrated circuit with full-speed data transition scheme for ddr sdram at internally doubled clock testing application: The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal... Agent: Saile Ackerman LLC

20080304330 - Systems, methods, and apparatuses for transmitting data mask bits to a memory device: Embodiments of the invention are generally directed to systems, methods, and apparatuses for transferring data mask bits to a memory device. In some embodiments, an integrated circuit includes logic to issue a partial write command to a memory device. In addition, the integrated circuit may include logic to transfer a... Agent: Intel Corporation C/o Intellevate, LLC

20080304333 - Semiconductor integrated circuit and method of allocating codes: A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of... Agent: Arent Fox LLP

20080304334 - Synchronous semiconductor memory device having on-die termination circuit and on-die termination method: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having... Agent: Volentine & Whitt PLLC

20080304335 - Semiconductor memory device including apparatus for detecting threshold voltage: A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the... Agent: Mcdermott Will & Emery LLP

20080304337 - Method for accessing memory: A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080304336 - Semiconductor memory device with zq calibration: A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal... Agent: Rabin & Berdo, PC

20080304339 - Apparatus and method of operating an integrated circuit technical field: The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state... Agent: Slater & Matsil, L.L.P.

20080304340 - Data i/o line control circuit and semiconductor integrated circuit having the same: A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O... Agent: Baker & Mckenzie LLP Patent Department

20080304341 - Redundancy circuit: A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating... Agent: Baker & Mckenzie LLP Patent Department

20080304342 - Semiconductor memory device with redundancy ciruit: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address... Agent: Studebaker & Brackett PC

20080304343 - Method and apparatus for testing a circuit: A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080304345 - Semiconductor memory device with reduced number of channels for test operation: A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080304344 - Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device: A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word... Agent: Mcdermott Will & Emery LLP

20080304346 - Apparatus and method reducing aging in a data storage device: An apparatus for reducing aging of at least one transistor device employed in a read path for a data storage device may include: a signal unit coupled with the at least one transistor device and coupled with the data storage device. The signal unit may be coupled for receiving an... Agent: Law Office Of Donald D. Mondul C/o Intellevate

20080304348 - Current-mode memory cell: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the... Agent: Law Office Of Charles W. Bethards, LLP

20080304347 - One time programmable element system in an integrated circuit: A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance,... Agent: Freescale Semiconductor, Inc. Law Department

20080304349 - Voltage supply circuit and semiconductor memory: A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080304350 - Signal processing circuit: A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external memory based on the first address data and the second address data for performing a predetermined processing, and outputs processed data... Agent: Cantor Colburn, LLP

20080304352 - Memory controllers and pad sequence control methods thereof: Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080304351 - Pin multiplexing: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive... Agent: Slater & Matsil LLP

20080304353 - Memory storage device with heating element: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to... Agent: Dr. Daniel P. Morris, Esq. IBM Corporation

20080304354 - Semiconductor memory device and method for reading/writing data thereof: A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080298109 - Fast analog sampler for continuous recording and read-out and digital conversion system: P

20080298110 - Content addressable memory: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged... Agent: Hewlett Packard Company

20080298111 - Semiconductor memory device: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a... Agent: Mills & Onello LLP

20080298112 - Memory array including programmable poly fuses: According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly... Agent: Farjami & Farjami LLP

20080298115 - Memory cell array with low resistance common source and high current drivability: In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the... Agent: Paul J. Winters

20080298114 - Phase change memory structure with multiple resistance states and methods of programming an sensing same: A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative... Agent: Dickstein Shapiro LLP

20080298113 - Resistive memory architectures with multiple memory cells per access device: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive... Agent: Dickstein Shapiro LLP

20080298116 - Deglitching circuits for a radiation-hardened static random access memory based programmable architecture: A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a... Agent: Lewis And Roca LLP

20080298118 - Asymmetrical sram cell with 4 double-gate transistors: The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor... Agent: Oliff & Berridge, PLC

20080298117 - Semiconductor integrated circuit device: A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080298119 - Magnetic memory cell with multiple-bit in stacked strucrute and magnetic memory device: A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at... Agent: Jianq Chyun Intellectual Property Office

20080298122 - Biasing a phase change memory device: A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to... Agent: Trop Pruner & Hu, PC

20080298121 - Method of operating phase-change memory: A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction.... Agent: Infineon Technologies Ag Patent Department

20080298120 - Peripheral devices using phase-change memory: Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller... Agent: Stuart T Auvinen

20080298124 - Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type... Agent: Volentine & Whitt PLLC

20080298125 - Semiconductor device: A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is provided on the element region, and a source region and a drain region which are provided in the first element region, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080298126 - Non-volatile semiconductor memory and method for replacing defective blocks thereof: A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080298127 - Method of reading flash memory device for depressing read disturb: Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected... Agent: Marshall, Gerstein & Borun LLP

20080298130 - Memory device distributed controller system: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080298128 - Method of storing e-fuse data in flash memory device: Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string... Agent: Volentine & Whitt PLLC

20080298129 - Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080298131 - Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor: An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having... Agent: Freescale Semiconductor, Inc. Law Department

20080298132 - Sense transistor protection for memory programming: A method and apparatus for protecting a sense transistor in a sense amplifier during memory programming and erase operations, and for increasing the coupling efficiency of the memory device during the programming and erase operations.... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP

20080298133 - Program verifying method and programming method of flash memory device: A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage.... Agent: Townsend And Townsend And Crew, LLP

20080298134 - Method of reading configuration data in flash memory device: Provided is a method of reading configuration data in a flash memory device, including a memory cell array which stores configuration data about an operating environment of the flash memory device. The method includes setting a read time of the configuration data to differ from a read time of normal... Agent: Volentine & Whitt PLLC

20080298135 - Metal oxide semiconductor device and method for operating an array structure comprising the same devices: The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel;... Agent: Sinorica, LLC

20080298136 - Enhanced erasing operation for non-volatile memory: Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080298123 - Non-volatile memory cell healing: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage,... Agent: Edward J. Brooks Iii Brooks & Cameron, PLLC

20080298137 - Method and structure for domino read bit line and set reset latch: A domino read bit line structure (20) integral to an SRAM array (1, 2) with thirty-two word lines or less to access SRAM cells divided into two groups (3, 4, 90, 100) is described. The bit line structure (20) includes a dynamic bit decode multiplexer (11, 40) and two NAND... Agent: Ibm Microelectronics Intellectual Property Law

20080298138 - Semiconductor device: Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a... Agent: Foley And Lardner LLP Suite 500

20080298139 - Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and /or controlling same: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix... Agent: Neil Steinberg

20080298141 - Bit line control circuit for semiconductor memory device: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for... Agent: Mcdermott Will & Emery LLP

20080298140 - Memory structure with word line buffers: A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined... Agent: Harness, Dickey & Pierce P.L.C

20080298142 - Clock and control signal generation for high performance memory devices: Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit.... Agent: Qualcomm Incorporated

20080298143 - Memory device with delay tracking for improved timing margin: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory... Agent: Qualcomm Incorporated

20080298145 - Antifuse replacement determination circuit and method of semiconductor memory device: An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge... Agent: Sughrue Mion, PLLC

20080298146 - Memory redundance circuit techniques: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can... Agent: Mcandrews Held & Malloy, Ltd

20080298144 - Semiconductor memory device capable of confirming a failed address and a method therefor: A semiconductor memory device includes an address buffer, a row decoder, a column decoder, a fuse circuit, a memory cell array including regular and redundant memory cells, a regulator, a regular sense amplifier, a redundant sense amplifier, a selection circuit, an input/output buffer, and a test control circuit for a... Agent: Studebaker & Brackett PC

20080298147 - Semiconductor memory: To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output... Agent: Foley And Lardner LLP Suite 500

20080298148 - Semiconductor memory device and test method therefor: There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test signals are provided in association with the plurality of clock signals respectively controlling the activation timings of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080298149 - Current reduction with wordline bit line short-circuits in drams and dram derivatives: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the... Agent: Dicke, Billig & Czaja

20080298150 - Semiconductor device: A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages to the sense amplifier. A... Agent: Mcginn Intellectual Property Law Group, PLLC

20080298151 - Sense amplifier overdriving circuit and semiconductor device using the same: A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for selection of a cell block and a second... Agent: Marshall, Gerstein & Borun LLP

20080298152 - Power saving memory apparatus, systems, and methods: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage... Agent: Schwegman, Lundberg & Woessner, P.A.

20080298153 - Semiconductor memory device: The present invention provides a semiconductor memory device with an open bit line structure in which sense amplifiers are arranged in a zigzag pattern and a plurality of banks, each having a plurality of mats, are provided. The semiconductor memory device includes: a refresh counter that counts the number of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080298154 - Semiconductor memory device: A semiconductor memory device includes: a plurality of banks each of which includes a plurality of mats each having normal word lines and redundant word lines; a first refresh generating circuit that generates a first refresh start signal for performing a first refresh operation in response to input of a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080298156 - Semiconductor device undergoing defect detection test: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion... Agent: Mcdermott Will & Emery LLP

20080298155 - Semiconductor memory device compensating leakage current: A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage... Agent: Amin, Turocy & Calvin, LLP

20080298157 - Multi-die packaged device: A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory function circuit in accordance... Agent: Townsend And Townsend And Crew, LLP

20080298158 - Two transistor wordline decoder output driver: A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the... Agent: Cool Patent, P.C. C/o Intellevate

20080298159 - Semiconductor integrated circuit: An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant... Agent: Arent Fox LLP