Static information storage and retrieval inventions 11/08

20080291713 - Modular flash memory card expansion system: A memory card system is disclosed. The memory card system comprises at least one flash memory card and a module for holding the at least one memory card. The module comprises a plurality of supports. The supports include rails to guide the at least one memory card in place and... Agent: Sawyer Law Group LLP

20080291714 - Semiconductor memory device: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each... Agent: Dickinson Wright PLLC

20080291716 - Method of programming a non-volatile memory device: A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080291715 - Nonvolatile memory device using variable resistive materials: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and... Agent: Volentine & Whitt PLLC

20080291717 - Semiconductor storage device incorporated into a system lsi with finer design rules: In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can... Agent: Steptoe & Johnson LLP

20080291719 - Streaming mode programming in phase change memories: A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without... Agent: Trop Pruner & Hu, PC

20080291718 - Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and methods of forming the same: A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of... Agent: Dickstein Shapiro LLP

20080291721 - Method and system for providing a spin transfer device with improved switching characteristics: A method and system for providing a magnetic element is described. The magnetic element includes a first pinned layer, a first spacer layer, a free layer, a second spacer layer, and a second pinned layer. The first and second pinned layers have first and magnetizations oriented in first and second... Agent: Strategic Patent Group, P.C.

20080291720 - Spin torque transfer mram device: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area,... Agent: Haynes And Boone, LLP

20080291724 - Multi-bit-per-cell flash memory device with non-bijective mapping: To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to... Agent: Mark M. Friedman

20080291726 - Bandgap engineered split gate memory: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height;... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080291725 - Memory cell array and semiconductor memory: A memory cell array includes a plurality of memory cells disposed in matrix, a plurality of word lines extending to the column direction wherein the gates in the memory cells disposed in each column are commonly connected to one of the word lines, a plurality of sub bit lines extending... Agent: Junichi Mimura Oki America Inc.

20080291727 - Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory: Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory... Agent: Harness, Dickey & Pierce, P.L.C

20080291728 - Single-poly non-volatile memory cell: A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having... Agent: Macpherson Kwok Chen & Heid LLP

20080291729 - Non-volatile memory with high reliability: A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20080291730 - Reducing effects of program disturb in a memory device: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080291731 - Methods for optimizing page selection in flash-memory devices: The present invention discloses methods for storing data in a flash-memory storage device, the method including the steps of: receiving, by the device, primary data to be stored in the device and to be read from the device at a primary reading speed; storing at least part of the primary... Agent: Mark M. Friedman

20080291733 - Loading data with error detection in a power on sequence of flash memory device: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data... Agent: Jianq Chyun Intellectual Property Office

20080291734 - Nonvolatile memory devices and methods of controlling the wordline voltage of the same: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages... Agent: Myers Bigel Sibley & Sajovec

20080291732 - Three cycle sonos programming: A method to eliminate over-erase in a nonvolatile trapped-charge memory array during write operations includes a three-cycle process of bulk programming the memory array, bulk erasing the memory array and selectively inhibiting one or more memory cells in the memory array while applying a programming voltage to the memory array.... Agent: Cypress/blakely

20080291735 - Method for using transitional voltage during programming of non-volatile storage: To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements... Agent: Vierra Magen/sandisk Corporation

20080291738 - Methods and circuits for generating a high voltage and related semiconductor memory devices: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage... Agent: Myers Bigel Sibley & Sajovec

20080291736 - Non-volatile storage system with transitional voltage during programming: To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements... Agent: Vierra Magen/sandisk Corporation

20080291737 - Program and erase methods for nonvolatile memory: Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a... Agent: Harness, Dickey & Pierce, P.L.C

20080291722 - Charge trapping memory and accessing method thereof: An accessing method for a charge trapping memory including memory cells and tracking cells for storing expected data. The method includes the following steps. In a specific time first, the expected data is written into the tracking cells and the memory cells are not being programmed, read or erased. Next,... Agent: Bacon & Thomas, PLLC

20080291739 - Methods of programming non-volatile semiconductor memory devices using different program verification operations and related devices: A method of programming a non-volatile memory device includes receiving data to be programmed into memory cells of the memory device, programming the memory cells with the data, and selectively performing one of a plurality of program verify operations based on a current program loop number to determine whether the... Agent: Myers Bigel Sibley & Sajovec

20080291741 - Bit line decoder architecture for nor-type memory array: A bit line decoder for sensing states of memory cells of a memory array includes control devices and a control module. The control devices selectively communicate with bit lines. The control devices are arranged in a multi-level configuration having a plurality of levels, each level having a plurality of the... Agent: Harness, Dickey & Pierce P.L.C

20080291740 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080291742 - Semiconductor memory device: A semiconductor memory device is disclosed, which includes a plurality of NAND cells each comprising a plurality of series-connected memory cell transistors, and a drain-side select transistor and a source-side select transistor connected to a drain-side end and a source-side end of the series-connected memory cell transistors, respectively, a source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080291743 - Semiconductor storage device: This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080291723 - Source biasing of nor-type flash array with dynamically variable source resistance: A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value... Agent: Macpherson Kwok Chen & Heid LLP

20080291744 - Portable medical storage device and program: A medical self-portable device and program on portable drive containing medical information that would be useful and pertinent for doctors and pharmacists to access and have the ability to update. This medical information is necessary for medical personnel to accurately and efficiently treat life-threatening emergency, non-life-threatening emergency, critical care, and/or... Agent: Procopio, Cory, Hargreaves & Savitch LLP

20080291751 - Scr matrix storage device: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the... Agent: Goodwin Procter LLP Patent Administrator

20080291745 - Method and system for simultaneous reads of multiple arrays: A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set oft input selector signals. The method includes... Agent: Freescale Semiconductor, Inc. Law Department

20080291747 - Buffered memory device: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state... Agent: Fish & Richardson P.C.

20080291749 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system... Agent: Mcdermott Will & Emery LLP

20080291746 - Semiconductor storage device and burst operation method: The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL1 and CSL2 are driven in order during activation of sense amplifiers. This causes bit switches BSW1-BSW8 to be turned on... Agent: Ibm Microelectronics Intellectual Property Law

20080291748 - Wide window clock scheme for loading output fifo registers: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit... Agent: Hogan & Hartson LLP

20080291750 - Semiconductor device that uses a plurality of source voltages: A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line... Agent: Mcginn Intellectual Property Law Group, PLLC

20080291752 - Semiconductor device: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line. The semiconductor device may include a data transfer unit... Agent: Marshall, Gerstein & Borun LLP

20080291753 - Semiconductor memory device and latency signal generating method thereof: A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to... Agent: Harness, Dickey & Pierce, P.L.C

20080291754 - Semiconductor memory device with low standby current: In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for... Agent: Mcdermott Will & Emery LLP

20080291755 - Output circuit for a semiconductor memory device and data output method: An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to... Agent: Young & Thompson

20080291756 - Semiconductor memory device of controlling bit line sense amplifier: A semiconductor memory device includes a memory core and an input/output circuit. The memory core amplifies a signal of a memory cell to output the amplified signal through an input/output line pair in a read mode, receives a signal of the input/output line pair to store in the memory cell... Agent: Mills & Onello LLP

20080291757 - Signal masking method, signal masking circuit, and semiconductor integrated circuit: A signal masking circuit includes a detection circuit, a delayed read data strobe signal generation circuit, a gating circuit, a counting circuit, and a masking circuit. The detection circuit detects a period of a logic “L” of a read data strobe signal. The gating circuit gates a delayed read data... Agent: Arent Fox LLP

20080291759 - Apparatus and method of generating output enable signal for semiconductor memory apparatus: A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable... Agent: Venable LLP

20080291758 - Read-leveling implementations for ddr3 applications on an fpga: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and... Agent: Townsend And Townsend And Crew LLP

20080291760 - Sub-array architecture memory devices and related systems and methods: Memory devices, systems and methods implementing an architecture for partitioning a memory area of normally used memory cells and redundant memory cells are disclosed. A memory area is partitioned into a plurality of substantially equally sized sub-arrays of normally used memory cells and redundant memory cells. The groups of memory... Agent: Trask Britt, P.C./ Micron Technology

20080291761 - Burn-in test apparatus: A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit... Agent: Cooper & Dunham, LLP

20080291763 - Memory device: A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect... Agent: Arent Fox LLP

20080291762 - Semiconductor memory device for precharging bit lines except for specific reading and writing periods: A semiconductor memory device includes a memory cell having an FET of a floating body type, and a capacitor for storing a data charge; a bit line to which the source or the drain of the FET is connected; a precharging device for performing precharge control so that the bit... Agent: Sughrue Mion, PLLC

20080291764 - Semiconductor memory device: A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor... Agent: Young & Thompson

20080291765 - Methods, circuits, and systems to select memory regions: Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080291766 - Memory architecture having local column select lines: A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections of memory. Each section of memory having a plurality of memory cells arranged in rows and columns of memory and a plurality of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080291768 - Bitcell with variable-conductance transfer gate and method thereof: A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a... Agent: Larson Newman Abel Polansky & White, LLP

20080291767 - Multiple wafer level multiple port register file cell: A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are... Agent: Scully, Scott, Murphy & Presser, P.C.

20080291769 - Multiport semiconductor memory device: In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports... Agent: Mcdermott Will & Emery LLP

20080291770 - Pll circuit for increasing potential difference between ground voltage and reference voltage or power source voltage of oscillation circuit: A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance... Agent: Sughrue Mion, PLLC

20080285322 - Junction field effect dynamic random access memory cell and content addressable memory cell: A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors.... Agent: Darryl G. Walker

20080285323 - Method and arrangement for associative memory device based on ferrofluid: The present invention provides an associative memory device based on a ferromagnetic nano-colloid, or ferrofluid. The design comprises inductive input and output units for training the ferrofluid as well as sensors incorporated into the output units for performing recall.... Agent: Foley And Lardner LLP Suite 500

20080285324 - Semiconductor memory device: Shunt regions are formed at certain intervals in a memory cell array region as extending in a second direction. The shunt regions each include a contact formed to connect a word line or a signal line wired in the same direction to another metal wire. Extension regions are each formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080285325 - Semiconductor memory device: In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and... Agent: Miles & Stockbridge PC

20080285326 - High density non-volatile memory array: A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains... Agent: Schwegman, Lundberg & Woessner / Atmel

20080285327 - Ferroelectric memory and semiconductor memory: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080285330 - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080285328 - Phase change memory: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One... Agent: Slater & Matsil, L.L.P.

20080285329 - Recordable electrical memory: A memory device includes a plurality of memory cells each including a recordable layer between two metal layers, the recordable layer including a first sub-cell and a second sub-cell. Each memory cell is constructed and designed to change from an as-deposited state to an initialized state upon application of an... Agent: Fish & Richardson PC

20080285331 - Scalable nonvolatile memory: Various magnetoresistive memory cells and architectures are described which enable nonvolatile memories having high information density.... Agent: Beyer Weaver LLP

20080285332 - Bit-alterable, non-volatile memory management: Methods and apparatuses for storage of data in bit-alterable, non-volatile memories. In some embodiments, an array of memory locations implemented as bit-alterable, non-volatile memory configured as a plurality of blocks of memory locations; and control circuitry coupled with the array of memory locations to cause a block of data to... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080285333 - Electric device comprising phase change material: The electric device (100) according to the invention has a resistor comprising a layer (7, 107) of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080285334 - Local bank write buffers for accelerating a phase-change memory: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may... Agent: Stuart T Auvinen

20080285335 - Programmable fuse/non-volatile memory structures using externally heated phase change material: A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed... Agent: Cantor Colburn LLP-ibm Yorktown

20080285336 - Semiconductor device: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output... Agent: Miles & Stockbridge PC

20080285337 - Recordable electrical memory: A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second state to a third state upon application... Agent: Fish & Richardson PC

20080285338 - Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage... Agent: Hoffman Warnick LLC

20080285341 - Reading non-volatile multilevel memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in... Agent: Brooks, Cameron & Huebsch , PLLC

20080285343 - Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups: Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality... Agent: Harness, Dickey & Pierce, P.L.C

20080285342 - Method of programming a nonvolatile memory cell and related memory array: A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant... Agent: North America Intellectual Property Corporation

20080285346 - Decoder, memory system, and physical position converting method thereof: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address... Agent: Lee & Morse, P.C.

20080285344 - Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.... Agent: Slater & Matsil, L.L.P.

20080285345 - Semiconductor memory device capable of increasing writing speed: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080285347 - Non-volatile memory devices and systems including bad blocks address re-mapped and methods of operating the same: A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT... Agent: Myers Bigel Sibley & Sajovec

20080285348 - Nonvolatile semiconductor memory device having assist gate: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line... Agent: Mcdermott Will & Emery LLP

20080285350 - Circuit and method for a three dimensional non-volatile memory: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on... Agent: Slater & Matsil, L.L.P.

20080285349 - Nonvolatile memory with backplate: The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common.... Agent: Macpherson Kwok Chen & Heid LLP

20080285353 - Flash memory device, method of manufacturing the same, and method of operating the same: Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected... Agent: Harness, Dickey & Pierce, P.L.C

20080285351 - Measuring threshold voltage distribution in memory using an aggregate characteristic: A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as... Agent: Vierra Magen/sandisk Corporation

20080285352 - Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations: Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading... Agent: Harness, Dickey & Pierce, P.L.C

20080285340 - Apparatus for reading data and method using the same: Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of... Agent: Harness, Dickey & Pierce, P.L.C

20080285339 - Voltage reference generator using big flash cell: A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference... Agent: Lemoine Patent Services, PLLC

20080285354 - Self reference sensing system and method: A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input... Agent: Spansion LLC

20080285355 - Flash memory device and method of erasing flash memory device: A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during... Agent: Volentine & Whitt PLLC

20080285356 - Semiconductor memory device employing clamp for preventing latch up: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing... Agent: Lowe Hauptman Ham & Berner, LLP

20080285357 - 1-transistor type dram cell, dram device and dram comprising thereof and driving method thereof and manufacturing method thereof: The present invention relates to a semiconductor device, and more precisely to an 1-transistor type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data... Agent: Ladas & Parry LLP

20080285358 - Method and circuit for stressing upper level interconnects in semiconductor devices: A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein.... Agent: Posz Law Group, PLC

20080285359 - Level-shifter circuit and memory device comprising said circuit: A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second... Agent: Seed Intellectual Property Law Group PLLC

20080285361 - Input/output line sense amplifier and semiconductor device having the same: An input/output (I/O) line sense amplifier includes a first sense amplifier configured to amplify a signal of an I/O line in response to a strobe signal, and a second sense amplifier configured to latch and amplify an output signal of the first sense amplifier in response to the strobe signal.... Agent: Cooper & Dunham, LLP

20080285360 - Semiconductor memory device and method of reading data therefrom: A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value.... Agent: Dickstein Shapiro LLP

20080285362 - Semiconductor memory device: A semiconductor memory device has a memory cell having a hierarchical bit line structure for large capacity even in a small cell size. The semiconductor memory device comprises a unit cell configured to read/write data, a cell data sensing unit configured to adjust a current amount of a main bit... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080285363 - Self-feedback control pipeline architecture for memory read path applications: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock... Agent: Saile Ackerman LLC

20080285364 - Data input circuit of semiconductor memory apparatus and data input method using the same: A data input circuit of a semiconductor memory apparatus includes a plurality of data input sense amplifiers, each of which amplifies input data in response to a data input strobe signal and generates amplified data, and a data selecting block that selectively outputs a plurality of amplified data in response... Agent: Baker & Mckenzie LLP Patent Department

20080285365 - Memory device for repairing a neighborhood of rows in a memory array using a patch table: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in... Agent: Brinks Hofer Gilson & Lione/sandisk

20080285366 - Test apparatus, program, and test method: There is provided a test apparatus that tests a device under test. The test apparatus includes an address generating circuit that generates a physical address to be supplied to a memory block inside the device under test, a plurality of mask registers being provided in correspondence with a plurality of... Agent: Jianq Chyun Intellectual Property Office

20080285367 - Method and apparatus for reducing leakage current in memory arrays: Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to... Agent: Qualcomm Incorporated

20080285369 - Block erase for volatile memory: A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are... Agent: Trask Britt, P.C./ Micron Technology

20080285368 - Method for nrom array word line retry erasing and threshold voltage recovering: A method for erasing and recovering a memory array is disclosed. The memory array includes a plurality of sectors of memory cells. After erasing a sector of the memory array, all of the memory cells of the memory array are checked to find programmed memory cells in the other un-erased... Agent: Stout, Uxa, Buyan & Mullins LLP

20080285370 - Semiconductor memory and system: An access control unit performs an access operation and a refresh operation of a memory block in response to an access request and a refresh request. The access control unit operates respective memory blocks in a single-cell mode or a twin-cell mode according to cell mode information in a mode... Agent: Arent Fox LLP

20080285371 - Wide window clock scheme for loading output fifo registers: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit... Agent: Hogan & Hartson LLP

20080285372 - Multi- port memory device for buffering between hosts and non-volatile memory devices: A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured... Agent: Myers Bigel Sibley & Sajovec

20080285373 - Address receiving circuit for a semiconductor apparatus: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according... Agent: Baker & Mckenzie LLP Patent Department

20080285374 - Semiconductor memory device: A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080285375 - Semiconductor device, module including the semiconductor device, and system including the module: A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment... Agent: Arent Fox LLP

20080278986 - High-speed and low-power differential non-volatile content addressable memory cell and array: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal,... Agent: Dla Piper US LLP

20080278987 - Layout structure of sub-word line driver and forming method thereof: A layout structure of a Sub-Word Line Driver (SWD) and a forming method thereof. A layout structure of an SWD may include first through fourth metal-oxide-semiconductor (MOS) transistors. The layout structure may include a first area including an active area of the first MOS transistor, wherein a gate-poly (GP) of... Agent: Marger Johnson & Mccollom, P.C.

20080278989 - Resistive memory device and method of manufacturing the same: Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in... Agent: Harness, Dickey & Pierce, P.L.C

20080278988 - Resistive switching element: According to one aspect, an integrated circuit may comprise a first electrode, a second electrode, and a resistive switching rod extending from the first electrode to the second electrode and being at least partly embedded in a thermal barrier matrix.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080278990 - Resistive-switching nonvolatile memory elements: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes... Agent: G. Victor Treyz

20080278991 - Semiconductor memory device: A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory... Agent: Young & Thompson

20080278992 - Independent-gate controlled asymmetrical memory cell and memory using the cell: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number... Agent: Ryan, Mason & Lewis, LLP

20080278993 - Static random acess memory device: Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080278995 - Magnetic memory and memory cell thereof and method of manufacturing the memory cell: A magnetic memory, a memory cell thereof, and a method of manufacturing the memory cell are provided. The memory cell of the magnetic memory includes a bottom contact layer, a bit line, a magnetic stack structure and a dielectric material. The bit line is disposed over the bottom contact layer.... Agent: Birch Stewart Kolasch & Birch

20080278994 - Mram cell with multiple storage elements: An improved MRAM cell may include a first, second, and third contact, a first MTJ between the first and second contact, and a MTJ between the second and third contact. The MRAM cell is nonconductive between the first and second MTJ. The first MTJ may include a first free layer... Agent: Honeywell International Inc.

20080278996 - Programmable magnetic read only memory (mrom): In one embodiment, there is provided a method for programming a memory device having magnetoresistive memory elements as storage elements. The method is performed during fabrication of the memory device and may be used to realize a Magnetic Read Only Memory (MROM) device. In accordance with the method, during fabrication... Agent: Hahn And Moodley, LLP

20080278997 - Semiconductor memory device and write control method thereof: A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying... Agent: Sughrue Mion, PLLC

20080278998 - Data storage device and method: A serial magnetic mass storage device and associated data storage method is provided based on magnetic nanowires that support single magnetic domains separated by domain walls. Each data-storing nanowire has a plurality of crossing nanowires along its length, forming cross junctions that constitute domain wall pinning sites. Data is fed... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080278999 - Source and drain side early boosting using local self boosting for non-volatile storage: Program disturb is reduced during programming of non-volatile storage by providing a boosting scheme in which isolation voltage are applied to two word lines to create a source side channel region on a source side of one isolation word line, an intermediate channel region between the isolation word lines and... Agent: Vierra Magen/sandisk Corporation

20080279002 - Methods of reading data including comparing current and previous section addresses and related devices: A memory device may include a memory cell array arranged in a plurality of sections of memory cells, with each section of memory cells including a plurality of sub-sections of memory cells. Operation of the memory device may include providing a current memory address for a current read operation from... Agent: Myers Bigel Sibley & Sajovec

20080279003 - Multiple independent serial link memory: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080279001 - Operating method of non-volatile memory: A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed... Agent: Jianq Chyun Intellectual Property Office

20080279004 - Charge-trapping memory device and methods for its manufacturing and operation: A method for leveling bit errors in a charge-trapping memory device is disclosed. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused... Agent: Slater & Matsil, L.L.P.

20080279005 - Managing flash memory program and erase cycles in the time domain: A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject... Agent: Amin, Turocy & Calvin, LLP

20080279006 - Semiconductor memory device and electric power supply method: A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080279007 - Boosting for non-volatile storage using channel isolation switching: Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is... Agent: Vierra Magen/sandisk Corporation

20080279008 - Non-volatile storage with boosting using channel isolation switching: Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel... Agent: Vierra Magen/sandisk Corporation

20080279011 - Data processing apparatus: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After... Agent: Miles & Stockbridge PC

20080279010 - Flash memory device and program method thereof: A method for programming a flash memory device comprising programming memory cells via repetition of program loops, a first of the program loops including a program execution interval and a verify read interval, a second of the program loops including the program execution interval, the verify read interval, and a... Agent: Marger Johnson & Mccollom, P.C.

20080279009 - Nonvolatile semiconductor memory device and writing method of the same: A nonvolatile semiconductor memory device and a writing method thereof are provided. The nonvolatile semiconductor memory device includes a cell array, a controller configured to receive input data from an outside source, an address latch unit configured to store a Y-address of the input data and X-addresses respectively corresponding to... Agent: F. Chau & Associates, LLC

20080279012 - Methods of operating memory devices including negative incremental step pulse programming and related devices: A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the... Agent: Myers Bigel Sibley & Sajovec

20080279000 - Nonvolatile semiconductor memory: There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of... Agent: Miles & Stockbridge PC

20080279013 - Multi-level non-volatile memory cell with high-vt enhanced btbt device: The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080279014 - Multi-phase wordline erasing for flash memory: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines... Agent: Amin, Turocy & Calvin, LLP

20080279015 - Register file: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20080279016 - Simplified-down mode control circuit utilizing active mode operation control signals: A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in... Agent: Ladas & Parry LLP

20080279017 - Semiconductor memory device: During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line... Agent: Mcdermott Will & Emery LLP

20080279018 - Redundancy circuit capable of reducing time for redundancy discrimination: A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row address signals to a plurality of fuse address signals; and... Agent: Baker & Mckenzie LLP Patent Department

20080279019 - Semiconductor device: A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data... Agent: Quintero Law Office, PC

20080279020 - Semiconductor memory device: The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block... Agent: Sughrue Mion, PLLC

20080279021 - Multi-wordline test control circuit and controlling method thereof: A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a... Agent: Baker & Mckenzie LLP Patent Department

20080279022 - Semiconductor device with self refresh test mode: A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through... Agent: Trask Britt, P.C./ Micron Technology

20080279023 - Semiconductor integrated circuit with full-speed data transition scheme for ddr sdrsm at internally doubled clock testing application: The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal... Agent: Saile Ackerman LLC

20080279024 - Programmable boosting and charge neutralization: A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node... Agent: Brinks Hofer Gilson & Lione/marvell

20080279025 - Electronic circuit with memory for which a threshold level is selected: A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form... Agent: Philips Intellectual Property & Standards

20080279026 - Signal sensing circuit and semiconductor memory device using the same: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation... Agent: Rosenberg, Klein & Lee

20080279027 - Thermally stable reference voltage generator for mram: A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080279028 - Flash/dynamic random access memory field programmable gate array: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory... Agent: Lewis And Roca LLP

20080279029 - Low voltage data path in memory array: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel... Agent: Freescale Semiconductor, Inc. Law Department

20080279030 - Voltage stabilization circuit and semiconductor memory apparatus using the same: A voltage stabilization circuit includes a control signal generating unit not generating a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control... Agent: Baker & Mckenzie LLP Patent Department

20080279031 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for... Agent: Baker & Mckenzie LLP Patent Department

20080279032 - Integrated circuit memory device, system and method having interleaved row and column control: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to... Agent: Deniro/rambus

20080279033 - Semiconductor integrated circuit device: A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with... Agent: Stanley P. Fisher Reed Smith LLP

20080279034 - Data output circuit of synchronous memory device: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data... Agent: Ladas & Parry LLP

20080273361 - Memory cell for content-addressable memory: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word.... Agent: Ryan, Mason & Lewis, LLP

20080273362 - Low power content addressable memory: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare... Agent: Shemwell Gregory & Courtney LLP

20080273364 - Memory structure with embeded multi-type memory: A memory includes a first-type memory; and a second-type memory, formed on the first-type memory, wherein the first-type memory is a nonvolatile memory with a stack of conductor/storage/conductor, and the second-type memory is a nonvolatile memory, a flash memory or another memory with a stack of conductor/storage/conductor. In addition, the... Agent: J C Patents, Inc.

20080273365 - Nonvolatile memory device having twin memory cells: A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction.... Agent: Volentine & Whitt PLLC

20080273363 - Semiconductor constructions, electronic systems, and methods of forming cross-point memory arrays: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched... Agent: Wells St. John P.s.

20080273366 - Design structure for improved sram device performance through double gate topology: A design structure embodied in a machine readable medium used in a design process includes a static random access memory (SRAM) device having a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured... Agent: Cantor Colburn LLP-ibm Burlington

20080273368 - Method and apparatus for reading data from a ferromagnetic memory cell: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor... Agent: Morgan Lewis & Bockius LLP

20080273367 - Multi-stack ferroelectric polymer memory device and method for manufacturing same: A memory device and method for manufacturing the memory device are provided. The memory device including a first electrode, a first ferroelectric polymer layer over the first electrode, a second electrode over the first ferroelectric polymer layer, a second ferroelectric polymer layer over the second electrode, a third electrode over... Agent: Bell, Boyd & Lloyd, LLP

20080273369 - Integrated circuit, memory module, method of operating an integrated circuit, and computing system: According to one embodiment of the present invention, a memory device includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different... Agent: Slater & Matsil, L.L.P.

20080273370 - Integrated circuit, method of operating an integrated circuit, memory cell array, and memory module: According to one embodiment of the present invention, an integrated circuit includes a memory cell that includes at least two resistivity changing layers being stacked above each other, each resistivity changing layer serving as a separate data storage layer and having individual data storing properties.... Agent: Slater & Matsil, L.L.P.

20080273371 - Memory including write circuit for providing multiple reset pulses: An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first... Agent: Dicke, Billig & Czaja

20080273372 - Method of programming multi-layer chalcogenide devices: A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. The method includes providing an electrical signal between the two terminals, where the electrical signal alters an electrical characteristic of... Agent: Kevin L. Bray Energy Conversion Devices, Inc.

20080273373 - Apparatus for improved sram device performance through double gate topology: A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during... Agent: Cantor Colburn LLP-ibm Burlington

20080273374 - Methods of operating and designing memory circuits having single-ended memory cells with improved read stability: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a... Agent: Ryan, Mason & Lewis, LLP

20080273375 - Integrated circuit having a magnetic device: An integrated circuit having a magnetic device is disclosed. In one embodiment, the integrated circuit includes a reference structure having a first blocking temperature. A storage structure is provided made of a ferromagnetic material. An antiferromagnetic structure is provided having a second blocking temperature lower than the first blocking temperature.... Agent: Dicke, Billig & Czaja

20080273376 - Intrusion resistant apparatus and method: An intrusion-resistant apparatus may include a magnetic memory array disposed with an enclosure. The magnetic memory may include a plurality of magnetic memory elements, each adapted to store a binary value only in the presence of a predetermined bias magnetic field having a magnetic field strength and direction within predetermined... Agent: SocalIPLaw Group LLP

20080273377 - Methods of writing data to magnetic random access memory devices with bit line and/or digit line magnetic layers: A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel... Agent: Myers Bigel Sibley & Sajovec

20080273378 - Multi-level resistive memory cell using different crystallization speeds: An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second... Agent: Dicke, Billig & Czaja

20080273379 - Programming a normally single phase chalcogenide material for use as a memory of fpla: A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the... Agent: Trop Pruner & Hu, PC

20080273380 - Method and system for providing field biased magnetic memory devices: A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic storage cells in an array, a plurality of bit lines, and at least one bias structure. Each of the plurality of magnetic storage cells includes at least one magnetic... Agent: Strategic Patent Group, P.C.

20080273381 - Method for switching random access memory elements and magnetic element structures: A method for storing data in a magnetic memory element of an array of elements which avoids inadvertent switching of other elements. First and second magnetic fields are applied to a selected magnetic element for a first time interval to switch the element into an intermediate state where minor domains... Agent: Ratnerprestia

20080273382 - Pseudo 6t sram cell: A pseudo 6T SRAM cell design comprising eight transistors is provided. An embodiment comprises a pair of cross-coupled inverters and a pair of pass-gate transistors electrically coupled to each inverter through the substrate. Each pass-gate transistor has a different beta ratio from the other transistor in its pair, and the... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20080273386 - Multi-level cell access buffer with dual function: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory... Agent: Smart & Biggar P.o. Box 2999, Station D

20080273385 - Nand step up voltage switching method: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20080273384 - Non-volatile multilevel memory cells with data read of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold... Agent: Brooks, Cameron & Huebsch , PLLC

20080273387 - Nonvolatile semiconductor storage device and method for writing therein: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is... Agent: Hansen Huang Technology Law Group, LLP

20080273388 - Adjusting resistance of non-volatile memory using dummy memory cells: In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data... Agent: Vierra Magen/sandisk Corporation

20080273389 - Flash memory cells, nand cell units, methods of forming nand cell units, and methods of programming nand cell unit strings: Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell... Agent: Wells St. John P.s.

20080273390 - Nand flash memory cell array and method of fabricating the same: A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the... Agent: Birch Stewart Kolasch & Birch

20080273391 - Regulator bypass start-up in an integrated circuit device: An internal voltage regulator in an integrated circuit device is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator protects the low voltage core logic circuits of the integrated circuit device from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory... Agent: Attention Of : Paul N. Katz Baker Botts L.L.P.

20080273392 - Method of programming a selected memory cell: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate,... Agent: Fountain Law Group, PLC C/o Maxim

20080273383 - High voltage generator circuit and flash memory device including the same: A high voltage generator circuit includes a high voltage generator configured to generate a high voltage; and a control circuit configured to control the high voltage generator so as to vary the high voltage in response to variations of a peripheral temperature.... Agent: F. Chau & Associates, LLC

20080273393 - Programmable heavy-ion sensing device for accelerated dram soft error detection: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply... Agent: Ryan, Mason & Lewis, LLP

20080273394 - Symmetric differential current sense amplifier: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080273395 - Expanded programming window for non-volatile multilevel memory cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include... Agent: Brooks, Cameron & Huebsch , PLLC

20080273396 - Nonvolatile semiconductor memory device: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one... Agent: Mcdermott Will & Emery LLP

20080273397 - Switched bitline vth sensing for non-volatile memories: A transistor provides a voltage source commonly switched by SE and SO switches to pre-charge both the even bitline and the odd bitline. The SE and SO switches are open during a sensing stage to determine whether the cell side or the reference side has a higher current and determine... Agent: Intel Corporation C/o Intellevate, LLC

20080273398 - Semiconductor device storage cell structure, method of operation, and method of manufacture: The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least... Agent: Haverstock & Owens, LLP

20080273399 - Single-poly non-volatile memory: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate.... Agent: Connolly Bove Lodge & Hutz LLP

20080273400 - Fast erasable non-volatile memory: A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting... Agent: Seed Intellectual Property Law Group PLLC

20080273401 - Method of erasing a block of memory cells: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate,... Agent: Fountain Law Group, PLC C/o Maxim

20080273402 - Apparatus for implementing domino sram leakage current reduction: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080273404 - Semiconductor integrated circuit device: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit... Agent: Miles & Stockbridge PC

20080273403 - Storage cell design evaluation circuit including a wordline timing and cell access detection circuit: A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080273406 - Enhanced sram redundancy circuit for reducing wiring and required number of redundant elements: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time,... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080273405 - Multi-bit programming device and method of multi-bit programming: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to... Agent: Harness, Dickey & Pierce, P.L.C

20080273407 - Circuit and method to find wordline-bitline shorts in a dram: Method and apparatus for testing for a short between a wordline being tested and a bitline in a memory device. The method includes applying a first voltage to the bitline using a first voltage source and applying a second voltage to the wordline being tested using a second voltage source.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080273408 - System for bitcell and column testing in sram: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.... Agent: Texas Instruments Incorporated

20080273409 - Junction field effect dynamic random access memory cell and applications therefor: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data... Agent: Darryl G. Walker

20080273410 - Tungsten digitlines: Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a tungsten (W) monolayer on a tungsten nitride (WNx) substrate, a boron (B) monolayer on the W monolayer, and a bulk W... Agent: Brooks, Cameron & Huebsch , PLLC

20080273411 - Fuse of a semiconductor memory device and repair process for the same: Disclosed herein is a fuse of a semiconductor memory device and a repair process for the same. The fuse includes a lower conductive film of a multilayer interconnection formed on a lower structure of a semiconductor substrate, an upper conductive film of the multilayer interconnection spaced apart upward from the... Agent: Marshall, Gerstein & Borun LLP

20080273412 - Memory device with split power switch: A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side... Agent: Brooks Kushman P.C. / Sun / Stk

20080273413 - Semiconductor device: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080273414 - Semiconductor device and memory circuit layout method: A memory comprising a memory array, a sensor amplifier, and a column driver/decoder. The memory comprises a plurality of memory cells. The sensor amplifier is disposed on one side of the memory array for accessing the memory cells of the memory array. The column driver/decoder is disposed on the opposite... Agent: Quintero Law Office, PC