Static information storage and retrieval inventions 10/08

20080259667 - Content addressable memory: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an... Agent: Hewlett Packard Company

20080259671 - 3-dimensional integrated circuit architecture, structure and method for fabrication thereof: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device... Agent: Scully, Scott, Murphy & Presser, P.C.

20080259668 - Layout structure of bit line sense amplifiers for a semiconductor memory device: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of... Agent: Lee & Morse, P.C.

20080259670 - Memory module: A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of... Agent: Slater & Matsil, L.L.P.

20080259669 - Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof: A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first... Agent: Marger Johnson & Mccollom, P.C.

20080259672 - 4f2 self align side wall active phase change memory: Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080259675 - Data writing to scalable magnetic memory devices: A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of... Agent: Michael J. Chang, LLC

20080259674 - Scalable magnetic memory devices: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer, and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent... Agent: Michael J. Chang, LLC

20080259673 - Space and process efficient mram and method: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52′) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52′) formed substantially directly on a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080259676 - Integrated circuit, memory module, method of operating an integrated circuit, method of manufacturing an integrated circuit, and computer program product: According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable... Agent: Slater & Matsil, L.L.P.

20080259677 - Memory including bipolar junction transistor select devices: An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions... Agent: Trop Pruner & Hu, PC

20080259678 - Method for initializing resistance-variable material, memory device containing a resistance-variable material, and method for initializing nonvolatile memory circuit including variable resistor: An initialization method of the present invention is a method for initializing a material (variable-resistance material) (2) whose resistance value increases/decreases according to the polarity of an applied electric pulse. An electric pulse having a first polarity is applied at least once between first and second electrodes (1, 3) connected... Agent: Mcdermott Will & Emery LLP

20080259679 - Programming method of magnetic random access memory: A programming method of a magnetic random access memory (MRAM) is provided. The magnetic random access memory includes a first magnetic pinned layer, a second magnetic pinned layer and a magnetic free layer. The first magnetic pinned layer is pinned at a first magnetic direction. The second magnetic pinned layer... Agent: Bacon & Thomas, PLLC

20080259680 - Memory element and method for manufacturing same: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between... Agent: Darby & Darby P.C.

20080259681 - Systems and devices for implementing sub-threshold memory devices: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor... Agent: Texas Instruments Incorporated

20080259682 - Semiconductor device: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080259686 - Non-volatile memory device, memory system, and lsb read method: A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and... Agent: Volentine & Whitt PLLC

20080259685 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080259684 - Programming a nand flash memory with reduced program disturb: When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the... Agent: Mark M. Friedman

20080259687 - Integrated circuits and methods of manufacturing thereof: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating... Agent: Slater & Matsil, L.L.P.

20080259689 - Mimicking program verify drain resistance in a memory device: A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified Vpass voltage that is determined in response to a predetermined drain resistance. In one embodiment, the... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080259688 - Non-volatile memory devices and methods of operating the same: A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected... Agent: Harness, Dickey & Pierce, P.L.C

20080259690 - Flash memory device: A NAND flash memory device includes a high voltage switch and a bulk voltage supplying circuit. The high voltage switch is configured to transfer a word line voltage to selected word lines of selected memory cells. The bulk voltage supplying circuit is configured to provide a negative voltage to a... Agent: Volentine & Whitt PLLC

20080259683 - Method and circuit for programming a memory cell, in particular of the nor flash type: A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to... Agent: Seed Intellectual Property Law Group PLLC

20080259691 - Two-bits per cell not-and-gate (nand) nitride trap memory: A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region... Agent: Jianq Chyun Intellectual Property Office

20080259692 - Semiconductor memory device for simultaneously performing read access and write access: Disclosed herein is a semiconductor memory device which can simultaneously perform a read access and a write access independently. The semiconductor memory device according to the present invention can access a plurality of data through the global sense amplifying unit and the global bit line, and enables the read controller... Agent: Occhiuti Rohlicek & Tsao, LLP

20080259696 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line... Agent: Schwegman, Lundberg & Woessner/micron

20080259693 - Semiconductor device: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080259694 - Semiconductor device: A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided... Agent: Miles & Stockbridge PC

20080259695 - Semiconductor memory devices having a demultiplexer and related methods of testing such semiconductor memory devices: A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input port that is configured to receive a control signal that identifies a type of signal... Agent: Myers Bigel Sibley & Sajovec

20080259697 - Semiconductor memory device having output impedance adjustment circuit and test method of output impedance: A semiconductor device has an output impedance adjustment circuit for automatically adjusting an output impedance of an output circuit including transistors connected in parallel. The output impedance adjustment circuit comprises: a replica circuit including a circuit portion of the substantially same configuration as the output circuit; a comparator for comparing... Agent: Young & Thompson

20080259698 - High speed dual port memory without sense amplifier: A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell... Agent: Stolowitz Ford Cowger, LLP/cypress

20080259699 - Memory control with selective retention: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080259700 - Bus control apparatus and bus control method: A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence with each of the blocks. The bus connection control unit monitors signals between the bus and the block,... Agent: Amin, Turocy & Calvin, LLP

20080259701 - Redundancy architecture for an integrated circuit memory: An integrated circuit memory 2 is described having multiple memory banks 4, 6, 8, 10, 12, 14, 16, 18 which are grouped into repair groups Group0, Group1. One of the memory banks 4, 18 is provided with redundant rows 20, 22 which can be used to substitute for a defective... Agent: Nixon & Vanderhye, PC

20080259705 - Hardware and software programmable fuses for memory repair: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is... Agent: Mcandrews Held & Malloy, Ltd

20080259703 - Self-timed synchronous memory: A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test... Agent: Stolowitz Ford Cowger, LLP/cypress

20080259704 - Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof: According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus,... Agent: Steptoe & Johnson LLP

20080259702 - State-monitoring memory element: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator... Agent: Stolowitz Ford Cowger LLP

20080259706 - Semiconductor memory: A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of... Agent: Mcdermott Will & Emery LLP

20080259707 - Semiconductor storage device: A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side... Agent: Mcdermott Will & Emery LLP

20080259709 - Column redundancy circuit: A column redundancy circuit is disclosed. The column redundancy circuit includes a first control signal generator configured to receive a refresh flag signal having an enable width larger than that of a refresh signal and a control signal and generate a pull-up control signal, a second control signal generator configured... Agent: Cooper & Dunham, LLP

20080259708 - Memory controller: A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080259711 - Print engine having authentication device for preventing multi-word memory writing upon power drop: A print engine comprising at least one print controller and at least one associated authentication device is provided. Each authentication device has a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit. Each authentication device is configured to enable multi-word writes to... Agent: Silverbrook Research Pty Ltd

20080259710 - System and method for power management of storage resources: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response... Agent: Baker Botts, LLP

20080259712 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations.... Agent: Schwegman, Lundberg & Woessner / Atmel

20080259667 - Content addressable memory: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an... Agent: Hewlett Packard Company

20080259671 - 3-dimensional integrated circuit architecture, structure and method for fabrication thereof: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device... Agent: Scully, Scott, Murphy & Presser, P.C.

20080259668 - Layout structure of bit line sense amplifiers for a semiconductor memory device: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of... Agent: Lee & Morse, P.C.

20080259670 - Memory module: A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of... Agent: Slater & Matsil, L.L.P.

20080259669 - Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof: A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first... Agent: Marger Johnson & Mccollom, P.C.

20080259672 - 4f2 self align side wall active phase change memory: Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include self-aligned side wall memory members comprising an active programmable resistive material. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080259675 - Data writing to scalable magnetic memory devices: A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of... Agent: Michael J. Chang, LLC

20080259674 - Scalable magnetic memory devices: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer, and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent... Agent: Michael J. Chang, LLC

20080259673 - Space and process efficient mram and method: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52′) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52′) formed substantially directly on a... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080259676 - Integrated circuit, memory module, method of operating an integrated circuit, method of manufacturing an integrated circuit, and computer program product: According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable... Agent: Slater & Matsil, L.L.P.

20080259677 - Memory including bipolar junction transistor select devices: An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions... Agent: Trop Pruner & Hu, PC

20080259678 - Method for initializing resistance-variable material, memory device containing a resistance-variable material, and method for initializing nonvolatile memory circuit including variable resistor: An initialization method of the present invention is a method for initializing a material (variable-resistance material) (2) whose resistance value increases/decreases according to the polarity of an applied electric pulse. An electric pulse having a first polarity is applied at least once between first and second electrodes (1, 3) connected... Agent: Mcdermott Will & Emery LLP

20080259679 - Programming method of magnetic random access memory: A programming method of a magnetic random access memory (MRAM) is provided. The magnetic random access memory includes a first magnetic pinned layer, a second magnetic pinned layer and a magnetic free layer. The first magnetic pinned layer is pinned at a first magnetic direction. The second magnetic pinned layer... Agent: Bacon & Thomas, PLLC

20080259680 - Memory element and method for manufacturing same: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between... Agent: Darby & Darby P.C.

20080259681 - Systems and devices for implementing sub-threshold memory devices: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor... Agent: Texas Instruments Incorporated

20080259682 - Semiconductor device: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080259686 - Non-volatile memory device, memory system, and lsb read method: A non-volatile memory device and system as well as a LSB read method are disclosed. The LSB read method includes reading LSB data from a memory cell during a main LSB read operation making reference to a flag cell threshold voltage, determining whether the LSB data contains an error, and... Agent: Volentine & Whitt PLLC

20080259685 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data program control section which programs a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080259684 - Programming a nand flash memory with reduced program disturb: When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the... Agent: Mark M. Friedman

20080259687 - Integrated circuits and methods of manufacturing thereof: Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating... Agent: Slater & Matsil, L.L.P.

20080259689 - Mimicking program verify drain resistance in a memory device: A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified Vpass voltage that is determined in response to a predetermined drain resistance. In one embodiment, the... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080259688 - Non-volatile memory devices and methods of operating the same: A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected... Agent: Harness, Dickey & Pierce, P.L.C

20080259690 - Flash memory device: A NAND flash memory device includes a high voltage switch and a bulk voltage supplying circuit. The high voltage switch is configured to transfer a word line voltage to selected word lines of selected memory cells. The bulk voltage supplying circuit is configured to provide a negative voltage to a... Agent: Volentine & Whitt PLLC

20080259683 - Method and circuit for programming a memory cell, in particular of the nor flash type: A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to... Agent: Seed Intellectual Property Law Group PLLC

20080259691 - Two-bits per cell not-and-gate (nand) nitride trap memory: A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region... Agent: Jianq Chyun Intellectual Property Office

20080259692 - Semiconductor memory device for simultaneously performing read access and write access: Disclosed herein is a semiconductor memory device which can simultaneously perform a read access and a write access independently. The semiconductor memory device according to the present invention can access a plurality of data through the global sense amplifying unit and the global bit line, and enables the read controller... Agent: Occhiuti Rohlicek & Tsao, LLP

20080259696 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line... Agent: Schwegman, Lundberg & Woessner/micron

20080259693 - Semiconductor device: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080259694 - Semiconductor device: A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided... Agent: Miles & Stockbridge PC

20080259695 - Semiconductor memory devices having a demultiplexer and related methods of testing such semiconductor memory devices: A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input port that is configured to receive a control signal that identifies a type of signal... Agent: Myers Bigel Sibley & Sajovec

20080259697 - Semiconductor memory device having output impedance adjustment circuit and test method of output impedance: A semiconductor device has an output impedance adjustment circuit for automatically adjusting an output impedance of an output circuit including transistors connected in parallel. The output impedance adjustment circuit comprises: a replica circuit including a circuit portion of the substantially same configuration as the output circuit; a comparator for comparing... Agent: Young & Thompson

20080259698 - High speed dual port memory without sense amplifier: A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell... Agent: Stolowitz Ford Cowger, LLP/cypress

20080259699 - Memory control with selective retention: The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080259700 - Bus control apparatus and bus control method: A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence with each of the blocks. The bus connection control unit monitors signals between the bus and the block,... Agent: Amin, Turocy & Calvin, LLP

20080259701 - Redundancy architecture for an integrated circuit memory: An integrated circuit memory 2 is described having multiple memory banks 4, 6, 8, 10, 12, 14, 16, 18 which are grouped into repair groups Group0, Group1. One of the memory banks 4, 18 is provided with redundant rows 20, 22 which can be used to substitute for a defective... Agent: Nixon & Vanderhye, PC

20080259705 - Hardware and software programmable fuses for memory repair: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is... Agent: Mcandrews Held & Malloy, Ltd

20080259703 - Self-timed synchronous memory: A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test... Agent: Stolowitz Ford Cowger, LLP/cypress

20080259704 - Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof: According to the present invention, an intra-macro match determining circuit 111 internally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus,... Agent: Steptoe & Johnson LLP

20080259702 - State-monitoring memory element: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator... Agent: Stolowitz Ford Cowger LLP

20080259706 - Semiconductor memory: A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of... Agent: Mcdermott Will & Emery LLP

20080259707 - Semiconductor storage device: A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side... Agent: Mcdermott Will & Emery LLP

20080259709 - Column redundancy circuit: A column redundancy circuit is disclosed. The column redundancy circuit includes a first control signal generator configured to receive a refresh flag signal having an enable width larger than that of a refresh signal and a control signal and generate a pull-up control signal, a second control signal generator configured... Agent: Cooper & Dunham, LLP

20080259708 - Memory controller: A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080259711 - Print engine having authentication device for preventing multi-word memory writing upon power drop: A print engine comprising at least one print controller and at least one associated authentication device is provided. Each authentication device has a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit. Each authentication device is configured to enable multi-word writes to... Agent: Silverbrook Research Pty Ltd

20080259710 - System and method for power management of storage resources: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response... Agent: Baker Botts, LLP

20080259712 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations.... Agent: Schwegman, Lundberg & Woessner / Atmel

20080253159 - Semiconductor memory device: A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of... Agent: Young & Thompson

20080253160 - Integrated circuit having a memory cell array and method of forming an integrated circuit: An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in... Agent: Dicke, Billig & Czaja

20080253161 - Sequence of current pulses for depinning magnetic domain walls: A method and structure for depinning a domain wall that is in spatial confinement by a pinning potential to within a local region of a magnetic device. At least one current pulse applied to the domain has a pulse length sufficiently close to a precession period of the domain wall... Agent: Schmeiser, Olsen & Watts

20080253162 - Multibit rom memory: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being... Agent: HowardIPLaw Group

20080253163 - Ferroelectric random access memory circuits for guarding against operation with out-of-range voltages and methods of operating same: A semiconductor device can include a first ferroelectric random access memory to which a first voltage is applied and a second ferroelectric random access memory to which a second voltage is applied, where the second voltage is lower than the first voltage. A data protection circuit can determine whether test... Agent: Myers Bigel Sibley & Sajovec

20080253166 - Integrated circuit, method for manufacturing an integrated circuit, memory cell array, memory module, and device: According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.... Agent: Slater & Matsil, L.L.P.

20080253167 - Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, active element, memory module, and computing system: According to one embodiment of the present invention, an active element includes a reactive electrode, an inert electrode and a solid electrolyte disposed between the reactive electrode and the inert electrode. The solid electrolyte has a negative differential resistance.... Agent: Slater & Matsil, L.L.P.

20080253164 - Integrated circuit, resistivity changing memory device, memory module and method of fabricating an integrated circuit: According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, and a plurality of conductive elements being electrically connected to the resistivity changing memory cells, at least some of the conductive elements comprising copper.... Agent: Slater & Matsil, L.L.P.

20080253168 - Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit: According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite... Agent: Slater & Matsil, L.L.P.

20080253165 - Method of manufacturing a memory device, memory device, cell, integrated circuit, memory module, and computing system: In one embodiment of the present invention, a method of fabricating a memory device includes: providing a composite structure including a resistivity changing layer and a first conductive layer disposed on or above the resistivity changing layer, forming a second conductive layer on or above the first conductive layer, and... Agent: Slater & Matsil, L.L.P.

20080253169 - Semiconductor memory device and writing method thereof: A semiconductor memory device includes a phase-change memory and has high compatibility with DRAM interface. The memory cell array comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily... Agent: Foley And Lardner LLP Suite 500

20080253170 - Semiconductor device: In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253171 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one... Agent: Mcdermott Will & Emery LLP

20080253172 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected... Agent: Mcdermott Will & Emery LLP

20080253173 - Magnetic random access memory: A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253174 - Magnetoresistance effect element and magnetoresistive random access memory using the same: A magnetoresistive effect element includes a first magnetic layer, a second magnetic layer, and a first spacer layer. The first magnetic layer has an invariable magnetization direction. The second magnetic layer has a variable magnetization direction, and contains at least one element selected from Fe, Co, and Ni, at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253175 - Nonvolatile magnetic memory device and photomask: A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two... Agent: Sonnenschein Nath & Rosenthal LLP

20080253176 - Nonvolatile magnetic memory device and photomask: A nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two... Agent: Sonnenschein Nath & Rosenthal LLP

20080253177 - Write operations for phase-change-material memory: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated... Agent: Ryan, Mason & Lewis, LLP

20080253178 - Mram with enhanced programming margin: An MRAM that is not subject to accidental writing of half-selected memory elements is described, together with a method for its manufacture. The key features of this MRAM are a C-shaped memory element used in conjunction with a segmented bit line architecture.... Agent: Stephen B. Ackerman

20080253179 - Semiconductor device, an electronic device and a method for operating the same: A semiconductor memory device includes circuitry coupled to a plurality of memory cells with transistors. The circuitry is configured to change a potential of a body of the transistor to a degree depending on a charging state of the body. A gate electrode of the transistor is maintained in a... Agent: Edell, Shapiro & Finnan, LLC

20080253180 - Hardened memory cell: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is... Agent: Oliff & Berridge, PLC

20080253181 - Method for programming a semiconductor memory device: A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253182 - Nand flash memory device and programming method: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating... Agent: Volentine & Whitt PLLC

20080253183 - Semiconductor memory device: A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253184 - Non volatile memory: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the... Agent: Miles & Stockbridge PC

20080253185 - Non-volatile memory and method with control gate compensation for source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080253186 - Bit line structure for a multilevel, dual-sided nonvolatile memory cell array: A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping dual-sided charge-trapping nonvolatile... Agent: Saile Ackerman LLC

20080253187 - Multiple select gate architecture: Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage.... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080253188 - Programming method to reduce gate coupling interference for non-volatile memory: A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20080253191 - Flash memory device and set-up data initialization method: A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a... Agent: Volentine & Whitt PLLC

20080253189 - Memory unit: A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The... Agent: J C Patents, Inc.

20080253190 - Non-volatile memory device and method of operating the same: The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between... Agent: Mills & Onello LLP

20080253192 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253194 - Flash memory device and program method thereof: A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality... Agent: F. Chau & Associates, LLC

20080253193 - Non-volatile memory with predictive programming: In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080253195 - Semiconductor memory device which includes mos transistor having charge accumulation layer and control gate and data readout method thereof: A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253196 - Method and apparatus for charging large capacitances: A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating... Agent: Dickstein Shapiro LLP

20080253197 - Predictive programming in non-volatile memory: In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080253199 - Parallel data storage system: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A... Agent: Mcdermott Will & Emery LLP

20080253198 - Semiconductor memory device with a noise filter and method of controlling the same: A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080253201 - Apparatus and method for calibrating on-die termination in semiconductor memory device: An on-die termination circuit in a semiconductor memory apparatus can comprise a comparing block for comparing a reference voltage with a code voltage corresponding to a code and outputting a comparison signal, a counting block for changing the code based on the comparison signal, and controlling block for controlling the... Agent: Baker & Mckenzie LLP Patent Department

20080253200 - Reading of the state of a non-volatile storage element: A method for reading of the state of a non-volatile memory element, comprising adjusting including conditioning the frequency of a first oscillatory to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080253202 - Communicating information using an existing light source of an electronic device: An electronic device 100 includes a data processor 106 for generating a data stream for communication with an external device. The electronic device also includes an illumination light source (145) for illuminating components (140) within the electronic device 100 and which provides modulated optical signals indicative of the data stream... Agent: Dillon & Yudell, LLP

20080253203 - Data output circuit for semiconductor memory apparatus: A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response... Agent: Baker & Mckenzie LLP Patent Department

20080253204 - Semiconductor memory apparatus including synchronous delay circuit unit: A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver.... Agent: Venable LLP

20080253205 - Write control signal generation circuit, semiconductor ic having the same and method of driving semicounductor ic: A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block... Agent: Baker & Mckenzie LLP Patent Department

20080253206 - Metal programmable self-timed memories: A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to... Agent: Lsi Corporation

20080253207 - Method and apparatus for testing the functionality of a page decoder: A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M... Agent: Schwegman, Lundberg & Woessner / Atmel

20080253208 - Semiconductor integrated circuit and memory checking method: The semiconductor integrated circuit includes a memory for storing secret data, a memory BIST circuit for executing a memory. BIST, a first selector for switching between a path for a memory isolation test via an external terminal and a path from the memory BIST circuit, a second selector for switching... Agent: Mcdermott Will & Emery LLP

20080253209 - Semiconductor memory device and method of testing same: Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080253210 - Semiconductor memory apparatus: Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of... Agent: Baker & Mckenzie LLP Patent Department

20080253211 - Semiconductor memory device: A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed during manufacture are eliminated. The semiconductor memory device is provided with word line selection circuits connected with a row address signal line to... Agent: Dickinson Wright PLLC

20080253212 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed... Agent: Mcdermott Will & Emery LLP

20080253213 - Semiconductor memory device and refresh method for the same: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even... Agent: Arent Fox LLP

20080253214 - Method and apparatus for incorporating ddr sdram into portable devices: A portable electronic device is provided which comprises (a) a memory device (42) equipped with an interface clock which is controlled by a Delay Locked Loop (DLL) such that the memory device is configured to operate in a first mode characterized by a minimum clock rate CRmin; and (b) a... Agent: Fortkort & Houston P.C.

20080253215 - Semiconductor memory circuit: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of... Agent: Stanley P. Fisher Reed Smith LLP

20080253216 - Semiconductor package for forming a double die package (ddp): A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080253219 - Active driver control circuit for semiconductor memory apparatus: An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled,... Agent: Baker & Mckenzie LLP Patent Department

20080253218 - Column decoder and semiconductor memory apparatus using the same: A column decoder according includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding... Agent: Venable LLP

20080253217 - Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage fo: Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage... Agent: Slater & Matsil, L.L.P.

20080253220 - Flexible ram clock enable: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a... Agent: Martine Penilla & Gencarella, LLP

20080247212 - Memory system having point-to-point (ptp) and point-to-two-point (pttp) links between devices: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary... Agent: Mills & Onello LLP

20080247213 - Memory device for protecting memory cells during programming: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080247218 - Design structure for implementing improved write performance for pcram devices: A design structure embodied in a machine readable medium used in a design process includes a circuit for implementing a write operation for a programmable resistive random access memory array, the circuit including a current source coupled to a bit line associated with a programmable resistive memory element; a dummy... Agent: Cantor Colburn LLP-ibm Burlington

20080247217 - Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system: An integrated circuit includes a plurality of resistivity changing memory cells and a plurality of resistivity changing reference cells. The integrated circuit is arranged such that each memory cell is switchable between N resistance levels, N being an integer greater than or equal to 2. To each of at least... Agent: Slater & Matsil LLP

20080247214 - Integrated memory: In one aspect, a resistive memory device may be implemented in an embedded system. A resistive memory may comprise a resistive switchable medium that may be electrically connected to a first and a second electrode. In one aspect the first and the second electrode may comprise a via conductor and... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080247216 - Method and apparatus for implementing improved write performance for pcram devices: A method of implementing a write operation for a programmable resistive random access memory array includes coupling a current source to a bit line associated with a programmable resistive memory element; prior to activating a word line associated with the memory element, precharging the bit line by passing current the... Agent: Cantor Colburn LLP-ibm Burlington

20080247219 - Resistive random access memory devices including sidewall resistive layers and related methods: A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions... Agent: Myers Bigel Sibley & Sajovec

20080247215 - Resistive switching element: According to one aspect, a switching element may comprise a first electrode, a second electrode, and a resistive switching region extending from the first electrode to the second electrode and comprising transition metal oxinitride.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080247221 - 8t sram cell with higher voltage on the read wl: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry... Agent: Texas Instruments Incorporated

20080247220 - Semiconductor memory device with memory cells operated by boosted voltage: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than... Agent: Miles & Stockbridge PC

20080247222 - Spin transfer torque magnetoresistive random access memory and design methods: Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word... Agent: Qualcomm Incorporated

20080247223 - Spin-injection magnetic random access memory: A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which applies, to the magnetoresistive element, a magnetic field of a direction of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080247226 - Memory devices having electrodes comprising nanowires, systems including same and methods of forming same: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory... Agent: Trask Britt, P.C./ Micron Technology

20080247224 - Phase change memory bridge cell with diode isolation device: Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080247227 - Semiconductor memory device and control method thereof: A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during... Agent: Sughrue Mion, PLLC

20080247225 - Variable resistance memory with lattice array using enclosing transistors: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are... Agent: Dickstein Shapiro LLP

20080247231 - Nand flash memory device: A NAND flash memory device includes: a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells; a plurality of word lines that are connected to the plurality of memory cells; a plurality of bit lines... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080247230 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,... Agent: Saile Ackerman LLC

20080247232 - Semiconductor storage device and electronic equipment therefor: A semiconductor storage device includes a first memory cell for storing two kinds of states, a second memory cell for storing two kinds of states, and a sense amplifier for detecting a potential difference between voltages equivalent to readout currents of the first and second memory cells, respectively. Either one... Agent: Birch Stewart Kolasch & Birch

20080247233 - Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device: A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device 1 comprises a booster controller circuit 10, a booster circuit 20, a level-shifting circuit 30, a Y-decoder 40, and a main circuit 50. A NAND gate... Agent: Ingrassia Fisher & Lorenz, P.C.

20080247234 - Flash memory device and method of operating the same: A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the... Agent: Townsend And Townsend And Crew, LLP

20080247235 - Flash memory device and method for driving the same: Provided are a flash memory device and a method of driving the same for reading set information and stably storing the read set information in a latch. The method of driving the flash memory device includes applying power to the flash memory device, which includes a memory cell array for... Agent: Volentine & Whitt PLLC

20080247236 - Program method of flash memory device: A method for operating a flash memory device includes applying a first program voltage Vp1 to a plurality of word lines of memory cells. Threshold voltages of the memory cells are measured to obtain a first threshold voltage distribution for the memory cells. A second program voltage Vp2 is applied... Agent: Townsend And Townsend And Crew, LLP

20080247229 - Non-volatile storage using current sensing with biasing of source and p-well: A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element.... Agent: Vierra Magen/sandisk Corporation

20080247228 - Non-volatile storage with current sensing of negative threshold voltages: A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well,... Agent: Vierra Magen/sandisk Corporation

20080247239 - Method for current sensing with biasing of source and p-well in non-volatile storage: Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The... Agent: Vierra Magen/sandisk Corporation

20080247238 - Method for sensing negative threshold voltages in non-volatile storage using current sensing: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well,... Agent: Vierra Magen/sandisk Corporation

20080247237 - Semiconductor memory device in which sense timing of sense amplifier can be controlled by constant current charge: A semiconductor memory device includes a plurality of sense amplifiers which read data from a plurality of memory cells of a memory cell array, and a sense time generation circuit which controls the sense time of the plurality of sense amplifiers, the sense time generation circuit including a dummy capacitor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080247240 - Erase verifying method of nand flash memory device: In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory... Agent: Townsend And Townsend And Crew, LLP

20080247241 - Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise: A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common... Agent: Vierra Magen/sandisk Corporation

20080247242 - Method using a one-time programmable memory cell: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080247243 - Semiconductor memory device including post package repair control circuit and post package repair method: Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing... Agent: Mills & Onello LLP

20080247244 - Reading circuitry in memory: A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a... Agent: Rabin & Berdo, PC

20080247245 - Write control method for a memory array configured with multiple memory subarrays: Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080247246 - Methods and apparatus for read/write control and bit selection with false read suppression in an sram: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate... Agent: Ryan, Mason & Lewis, LLP

20080247247 - Flash memory device and method for driving the same: Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding... Agent: Volentine & Whitt PLLC

20080247248 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a driving voltage supplying unit configured to detect a simultaneous activation of banks and selectively supply one of a high voltage and an external voltage lower than the high voltage as a driving voltage; a flag detecting unit configured to detect inputs of flag signals... Agent: Rabin & Berdo, PC

20080247249 - Circuit and method for a sense amplifier: A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch... Agent: Slater & Matsil, L.L.P.

20080247250 - Semiconductor memory device with two-stage input buffer: A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the... Agent: Mcdermott Will & Emery LLP

20080247251 - Memory device that takes leakage currents into account in activating the read amplifiers: A memory device is proved that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy... Agent: Fleit Gibbons Gutman Bongini & Bianco P.l.

20080247253 - Non-volatile storage with temperature compensation for bit line during sense operations: A non-volatile storage system in which temperature compensation of a bit line voltage is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it... Agent: Vierra Magen/sandisk Corporation

20080247252 - Semiconductor memory device with temperature control: A memory device in a semiconductor substrate includes at least one temperature sensor to provide a temperature dependent signal and at least one circuit to dissipate heat in response to a control signal. A control circuit is coupled to the at least one circuit and is operable to generate the... Agent: Edell, Shapiro & Finnan, LLC

20080247254 - Method for temperature compensating bit line during sense operations in non-volatile storage: Temperature-compensation is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature... Agent: Vierra Magen/sandisk Corporation

20080247255 - Electronic device including a nonvolatile memory array and methods of using the same: An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a... Agent: Larson Newman Abel Polansky & White, LLP

20080247256 - Refresh signal generator of semiconductor memory device: A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to... Agent: Rabin & Berdo, PC

20080247257 - Memory data inversion architecture for minimizing power consumption: A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state,... Agent: Christopher P Maiorana, PC Lsi Corporation

20080247258 - Semiconductor memory device and semiconductor integrated circuit device: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections... Agent: Miles & Stockbridge PC

20080247259 - Configurable memory data path: A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data... Agent: Coats & Bennett/qimonda

20080247260 - Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof: A semiconductor memory device in which a mode of a memory bank may be independently selected and a method of controlling the semiconductor memory device may be provided. The semiconductor memory device with a plurality of banks may include a plurality of bank groups that each may have at least... Agent: Harness, Dickey & Pierce, P.L.C

20080247261 - Semiconductor memory device and control method thereof: A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal... Agent: Young & Thompson

20080239778 - Hybrid dual match line architecture for content addressable memories and other data structures: A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an... Agent: Mhkkg/sun

20080239779 - System and method for detecting multiple matches: A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating... Agent: Baker Botts L.L.P.

20080239780 - Semiconductor device: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this... Agent: Miles & Stockbridge PC

20080239781 - Semiconductor memory device and method of forming a layout of the same: A semiconductor memory device having a double-patterned memory cell array that includes a plurality of first bit lines spaced apart from each other and having a first pattern, a plurality of second bit lines spaced apart from each other and having a second pattern, the second bit lines being between... Agent: Lee & Morse, P.C.

20080239782 - Semiconductor memory device: A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239783 - Semiconductor memory devices having strapping contacts: Semiconductor memory devices having strapping contacts with an increased pitch are provided. The semiconductor memory devices include cell regions and strapping regions between adjacent cell regions in a first direction on a semiconductor substrate. Active patterns extend in the first direction throughout the cell regions and strapping regions and are... Agent: Harness, Dickey & Pierce, P.L.C

20080239784 - High density planar magnetic domain wall memory apparatus: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location;... Agent: Cantor Colburn LLP-ibm Yorktown

20080239785 - High density planar magnetic domain wall memory apparatus: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location;... Agent: Cantor Colburn LLP-ibm Yorktown

20080239786 - Logic coding in an integrated circuit: The programming of a read-only memory formed of MOS transistors, the programming being set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. An interconnection structure and a read-only memory.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080239788 - Integrated circuit having a resistively switching memory and method: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold... Agent: Dicke, Billig & Czaja

20080239787 - Large array of upward pointing p-i-n diodes having large and uniform current: An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material... Agent: Dugan & Dugan, PC

20080239789 - Semiconductor memory device: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239790 - Method to form a memory cell comprising a carbon nanotube fabric element and a steering element: A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical... Agent: Dugan & Dugan, PC

20080239791 - Nano-electronic memory array: A memory device includes an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode; a... Agent: Bao Q. Tran

20080239793 - Generalized interlocked register cell (gice): A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches... Agent: Intel Corporation C/o Intellevate, LLC

20080239792 - Metal silicide alloy local interconnect: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms... Agent: Scully, Scott, Murphy & Presser, P.C.

20080239796 - Magnetic memory device and method of writing into the same: A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ1, MTJ2 and a select transistor connected to the connection node of the magnetoresistance effect elements MTJ1, MTJ2, a first signal line extended in a first direction and connected to the magnetoresistance effect element MTJ1, a second signal... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080239794 - Magnetoresistive random access memory device with small-angle toggle write lines: Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080239795 - Nonvolatile memory device with write error suppressed in reading data: A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current... Agent: Mcdermott Will & Emery LLP

20080239798 - Compensation circuit and memory with the same: One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to... Agent: Birch Stewart Kolasch & Birch

20080239797 - Information recording/reproducing device: There is proposed a nonvolatile information recording/reproducing device with low power consumption and high thermal stability. The information recording/reproducing device according to an aspect of the present invention includes a recording layer, and mechanism for recording information by generating a phase change in the recording layer while applying a voltage... Agent: Charles N.j. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080239799 - Nonvolatile semiconductor memory device and data erase/write method thereof: A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a switching element having a current path with one end and the other end, between which the variable resistor element is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239800 - Magnetic memory arrays: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and... Agent: Birch Stewart Kolasch & Birch

20080239802 - Device with load-based voltage generation: Method and device for providing voltage generation with load-based control are disclosed. The voltage generation can be provided within an electronic device, such as a memory system that provides data storage. In one embodiment, an electrical load imposed on a generated voltage can be monitored and used to dynamically control... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080239801 - Load management for memory device: Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080239803 - Memory cells, memory devices and integrated circuits incorporating the same: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080239804 - Method for reading multiple-value memory cells: A read method for multiple-value information in a semiconductor memory such as a nonvolatile semiconductor memory is introduced. The method includes obtaining a first data from a selected multiple-value memory cell by applying a first voltage to a control gate of the selected multiple-value memory cell. A second data from... Agent: North America Intellectual Property Corporation

20080239806 - Non-volatile multilevel memory cell programming: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number... Agent: Brooks, Cameron & Huebsch , PLLC

20080239805 - Nonvolatile semiconductor memory and data reading method: A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239807 - Transition areas for dense memory arrays: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory... Agent: Empk & Shiloh, LLP

20080239809 - Flash memory device and method for providing initialization data: A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the... Agent: Volentine & Whitt PLLC

20080239808 - Flash memory refresh techniques triggered by controlled scrub data reads: The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080239810 - Cell array of semiconductor memory device and method of driving the same: A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply... Agent: Townsend And Townsend And Crew, LLP

20080239811 - Method for controlling a non-volatile semiconductor memory, and semiconductor storage system: A semiconductor storage system includes a first memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing n bits data, the block is a minimum unit which is capable of being independently erased, a second memory region including at... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239812 - Nonvolatile semiconductor memory system: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239813 - Method of compensating variations along a word line in a non-volatile memory: Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080239814 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device includes a plurality of memory cells coupled in series, a plurality of word lines coupled to the respective memory cells, and a plurality of spacers interposed between the word lines and having different dielectric constants according to line widths of the word lines.... Agent: Lowe Hauptman Ham & Berner, LLP

20080239815 - Semiconductor device and manufacturing method thereof: In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating... Agent: Sughrue Mion, PLLC

20080239816 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device comprises a memory cell unit including at least one memory cell having a structure with a floating gate and a control gate stacked via an insulator on a semiconductor substrate. A common source line is connected to one end of the memory cell unit. A bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239817 - Nonvolatile semiconductor memory device and method of erasing and programming the same: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and... Agent: Posz Law Group, PLC

20080239819 - Nand flash memory with fixed charge: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may... Agent: Vierra Magen/sandisk Corporation

20080239821 - Nand memory with side-tunneling: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from... Agent: Weaver Austin Villeneuve Sampson LLP

20080239820 - Self-adaptive and self-calibrated multiple-level non-volatile memories: Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates... Agent: Macpherson Kwok Chen & Heid LLP

20080239822 - Semiconductor memory device and method for controlling the same: A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239818 - Three dimensional nand memory: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of... Agent: Foley And Lardner LLP Suite 500

20080239823 - Nonvolatile semiconductor memory and method for controlling the same: A nonvolatile semiconductor memory includes a memory cell array, a flag information storage that stores a write flag indicating success/failure of writing in association with each address of a plurality of data segments contained in the data block, an internal address storage that selects the address where the writing has... Agent: Sughrue Mion, PLLC

20080239824 - Non-volatile memory with compensation for variations along a word line: Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080239825 - Floating gate memory device with improved reference current generation: A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain... Agent: Young & Thompson

20080239826 - Semiconductor memory device capable of achieving narrower distribution width of threshold voltages of memory cells and method of data write in the same: When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat,... Agent: Mcdermott Will & Emery LLP

20080239827 - Methods of forming and operating nand memory with side-tunneling: A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from... Agent: Weaver Austin Villeneuve Sampson LLP

20080239828 - Flash memory device and erase method thereof: An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected... Agent: Townsend And Townsend And Crew, LLP

20080239829 - Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can... Agent: Miles & Stockbridge PC

20080239830 - Methods of operating memory devices including discharge of source/drain regions and related electronic devices: A memory device may include a memory cell array having a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. The string selection transistor may be coupled between the string and a bit line, and the ground selection transistor... Agent: Myers Bigel Sibley & Sajovec

20080239831 - Clock synchronizer: Disclosed herein are synchronization latch solutions.... Agent: Intel Corporation C/o Intellevate, LLC

20080239832 - Flash memory device and method for driving the same: A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region.... Agent: Rabin & Berdo, PC

20080239833 - Readout of multi-level storage cells: A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing... Agent: Slater & Matsil LLP

20080239835 - Semiconductor memory device with high voltage generator: A semiconductor memory device which prevents a drop of the level of an external voltage due to generation of high voltage, thereby ensuring an effective data window. The semiconductor memory device includes a level detecting unit and a voltage generating unit. The level detecting unit is configured to detect a... Agent: Mcdermott Will & Emery LLP

20080239834 - Sense amplifier for low voltage high speed sensing: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to... Agent: Dla Piper US LLP

20080239836 - Method for managing electrical load of an electronic device: Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080239837 - Semiconductor device: A semiconductor memory device includes a boosting circuit which boosts in a second voltage higher than an external power supply by using a first voltage as a reference voltage, and a bandgap reference circuit which operates by using the second voltage generated by the boosting circuit as a power supply... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080239838 - Semiconductor memory device for reducing power consumption: A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal;... Agent: Mcdermott Will & Emery LLP

20080239839 - Method for using a spatially distributed amplifier circuit: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages,... Agent: Zagorin O'brien Graham LLP (023)

20080239840 - Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits: A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as... Agent: Ladas & Parry LLP

20080239841 - implementing calibration of dqs sampling during synchronous dram reads: A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080239844 - Implementing calibration of dqs sampling during synchronous dram reads: A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080239843 - Interface circuit, memory interface system, and data reception method: An interface circuit is disclosed that can include a delay circuit that generates a delay signal obtained by delaying a data strobe signal; a first logical circuit that performs a logical operation of on the data strobe signal and the delay signal, and outputs an operation result as a first... Agent: Arent Fox LLP

20080239842 - Semiconductor memory device: A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response... Agent: Mcdermott Will & Emery LLP

20080239846 - Delay locked loop and semiconductor memory device with the same: A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking... Agent: Mcdermott Will & Emery LLP

20080239845 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a... Agent: Mcdermott Will & Emery LLP

20080239847 - Semi-shared sense amplifier and global read line architecture: A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital... Agent: Qualcomm Incorporated

20080239848 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes a write driver, a first precharging unit, and a second precharging unit. The write driver loads data applied to a first data line onto a second data line. The first precharging unit precharges the second data line to a precharging voltage in response to a... Agent: Rabin & Berdo, PC

20080239849 - Semiconductor memory device with reduced sense amplification time and operation method thereof: A semiconductor memory device is capable of swiftly sensing data loaded on local I/O lines and transferring the sensed data to a global I/O line, thereby reducing an operating time of a sense amplifier by increasing the sensing and amplifying speed. The semiconductor memory device includes a sense amplifying unit,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080239850 - Apparatus of processing a signal in a memory device and a circuit of removing noise in the same: A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configured to sense the falling edge... Agent: Townsend And Townsend And Crew, LLP

20080239851 - Flash memory with data refresh triggered by controlled scrub data reads: The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080239853 - Semiconductor memory device: A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery... Agent: Mcdermott Will & Emery LLP

20080239855 - Semiconductor memory device performing self refresh operation: The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080239854 - Semiconductor memory, system, and operating method of semiconductor memory: Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so... Agent: Arent Fox LLP

20080239852 - Test feature to improve dram charge retention yield: In some embodiments, a design for test feature to improve DRAM charge retention yield is presented. In this regard, an apparatus is introduced comprising a first integrated circuit die, and a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random... Agent: Intel Corporation C/o Intellevate, LLC

20080239856 - Method for load-based voltage generation: Method and device for providing voltage generation with load-based control are disclosed. The voltage generation can be provided within an electronic device, such as a memory system that provides data storage. In one embodiment, an electrical load imposed on a generated voltage can be monitored and used to dynamically control... Agent: Technology & Innovation Law Group, PC Attn: 1901

20080239858 - Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with... Agent: Zilka-kotab, PC- Mrm1

20080239857 - Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits... Agent: Zilka-kotab, PC- Mrm1

20080239859 - Access device: P-type multi gate field effect transistor access devices are adapted to be coupled to a memory cell to provide access to the memory cell. A method is described that uses a power switch to switch off address decoding circuitry allowing word lines to float toward a high supply voltage, turning... Agent: Schwegman, Lundberg & Woessner / Infineon

20080239860 - Apparatus and method for providing multiple reads/writes using a 2read/2write register file array: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080239861 - Memory and operation method thereof: A memory and an operation method thereof are provided. The present invention divides memory banks of the memory into a plurality of memory groups, wherein each memory group has an independent driving power for providing an operating voltage to the corresponding memory bank in the memory group. The present invention... Agent: Jianq Chyun Intellectual Property Office

20080239862 - Semiconductor memory device: The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a... Agent: Mcdermott Will & Emery LLP

20080239863 - Memory circuit arrangement and method for the production thereof: In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate.... Agent: Brinks Hofer Gilson & Lione

20080239864 - Memory access circuit: A memory access circuit is provided. The memory access circuit includes a latch circuit, a feedback reset circuit, and a gate latch circuit. The latch circuit receives a high level input signal and outputs a first signal. The feedback reset circuit generates a second signal and a reset signal according... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080239865 - Semiconductor memory device: The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which... Agent: Miles & Stockbridge PC