Static information storage and retrieval inventions 09/08

20080232148 - Semiconductor memory device and redundancy method thereof: A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080232149 - Integrated circuit chip with improved array stability: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g.,... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080232150 - Method and structure for implementing a reprogrammable rom: A method and structure implementing a reprogrammable read only memory (ROM) include a pair of fuse elements having different lengths and selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080232152 - Method and structure for implementing a reprogrammable rom: A method and structure for implementing a reprogrammable read only memory (ROM), and a design structure on which the subject circuit resides are provided. A pair of fuse elements having different lengths are selectively arranged to define an initial bit state. A group of a plurality of the pairs of... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080232151 - System and method to control one time programmable memory: Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may... Agent: Toler Law Group

20080232153 - Non-volatile memory device: A non-volatile memory device 100 contains: an insulating substrate 10; a first electrode 20 provided on the insulating substrate 10; a second electrode 30 provided on the insulating substrate 10; and a gap 40 set between the first electrode 20 and the second electrode 30, in which a distance G... Agent: Birch Stewart Kolasch & Birch

20080232154 - Resistance memory element and method of manufacturing the same, and semiconductor memory device: A resistance memory element memorizing a high resistance state or a low resistance state in a memory region and switched between the high resistance state and the low resistance state by an application of a voltage includes a resistance memory layer 42 of a resistance memory material, an electrode 38... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080232156 - Method using a synthetic molecular spring device in a system for dynamically controlling a system property and a corresponding system thereof: Using a synthetic molecular spring device in a system for dynamically controlling a system property, such as momentum, topography, and electronic behavior. System features (a) the synthetic molecular spring device having (i) at least one synthetic molecular assembly each featuring at least one chemical unit including at least one: (1)... Agent: Martin D. Moynihan Prtsi, Inc.

20080232155 - Molecular battery memory device and data processing system using the same: Each memory cell of a molecular battery memory device includes a combination of a molecular battery and a selection transistor, and a parasitic capacitance is present in the molecular battery. A PN junction is present in the selection transistor, and is inversely biased. Therefore, a junction leak current flows. Accordingly,... Agent: Young & Thompson

20080232157 - Random access memories with an increased stability of the mos memory cell: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number... Agent: Glenn Patent Group

20080232158 - Optimized phase change write method: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM.... Agent: Scully Scott Murphy & Presser, PC

20080232159 - Phase-change tan resistor based triple-state/multi-state read only memory: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN... Agent: Scully, Scott, Murphy & Presser, P.C.

20080232160 - Rectifying element for a crosspoint based memory array architecture: An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance... Agent: Ip Authority, LLC Ramraj Soundararajan

20080232161 - Resistance variable memory device and read method thereof: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage,... Agent: Volentine & Whitt PLLC

20080232163 - Memory storage technique for a bi-directionally programmable memory device: According to some embodiments, a memory device is disclosed. The memory device includes a memory array with a programming region to store data. The programming region includes a plurality of memory cells and has an associated flag bit. Logic is coupled to the memory array. The logic is to compare... Agent: Trop, Pruner & Hu, P.C.

20080232165 - Method for modifying data more than once in a multi-level cell memory location within a memory array: A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in... Agent: Dickstein Shapiro LLP

20080232164 - Method for programming a multilevel memory: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the... Agent: Birch Stewart Kolasch & Birch

20080232166 - Content data storage device and its control method: A content data storage device which stores content data in nonvolatile memories from which data is erasable in units of blocks includes a bus width conversion unit converting a transmission bus to buses of a plurality of systems, a storage unit including a plurality of sets of memories, a plurality... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080232167 - Current controlled recall schema: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.... Agent: Fsp LLC

20080232162 - One time programming cell structure and method of fabricating the same: A One Time Programming (OTP) cell structure, a method of fabricating an OTP structure, and a method of programming a OTP cell structure. The OTP structure comprises a semiconductor substrate; an n Metal-Oxide-Semiconductor (nMOS) programming structure formed on the substrate; wherein respective electrical contacts to a source of the nMOS... Agent: Christie, Parker & Hale, LLP

20080232168 - Level shift circuit which improved the blake down voltage: A gate and the other end of the current path of first and second transistors are cross-connected. A third transistor is inserted to the other end of the current path of the first transistor, and a gate is supplied with a constant voltage, and further, one end of the current... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080232170 - Memory device, a non-volatile semiconductor memory device and a method of forming a memory device: A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.... Agent: Dicke, Billig & Czaja

20080232169 - Nand-like memory array employing high-density nor-like memory devices: A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality... Agent: Schwegman, Lundberg & Woessner / Atmel

20080232172 - Flash memory device and method of controlling program voltage: A memory cell array of a NAND flash memory device includes memory cells connected to bit lines and word lines. A page buffer unit includes cell program test circuits configured to program data into a selected memory cell or read data from the memory cell. An IO controller includes a... Agent: Townsend And Townsend And Crew, LLP

20080232171 - Phase change memory with program/verify function: A phase change memory includes a plurality of cells for storing data in the form of respective resistance levels, addressing circuits for addressing cells to be programmed, and the resistance levels are determined from comparison of cell currents of addressed cells with a reference current. A reference generator provides the... Agent: Trop Pruner & Hu, PC

20080232173 - Non-volatile memory having a row driving circuit with shared level shift circuits: Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits.... Agent: North America Intellectual Property Corporation

20080232174 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Fish & Richardson P.C.

20080232175 - Content data storage device and its control method: A content data storage device which stores content data which includes a wide-band content and a narrow-band content includes a buffer memory temporarily storing the content data to be externally input, a storage unit including a plurality of nonvolatile memories configured to be written for each page and storing in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080232176 - Portable information terminal: The present invention provides a portable information terminal having installed therein an IC chip. The portable information terminal includes an internal memory disposed within the IC chip driven by using power supplied via a reader/writer, which is impossible to be accessed from outside the IC chip, an external memory driven... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080232177 - Nonvolatile memory device using variable resistive element: Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove noise from one or more corresponding control signals.... Agent: Volentine & Whitt PLLC

20080232178 - Apparatus and method for controlling delay of signal: An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080232179 - Circuit, system and method for controlling read latency: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080232180 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay... Agent: Mcdermott Will & Emery LLP

20080232181 - Semiconductor memory device: This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080232182 - Precharge voltage supplying circuit: A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal... Agent: Cooper & Dunham, LLP

20080232183 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080232184 - Semiconductor memory device: This disclosure concerns a memory comprising memory cells including floating bodies, logic data being stored in the memory cells; word lines connected to gates of the memory cells; bit lines connected to the memory cells; and sense amplifiers connected to the bit lines, and applying a first voltage to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080232185 - Structure and method of implementing power savings during addressing of dram architectures: A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of... Agent: Cantor Colburn LLP - IBM Rochester Division

20080232186 - Memory interface and adaptive data access method: A data access method for an application circuit to access a memory. The method includes steps of: receiving a first data from the application circuit; duplicating the first data to obtain a duplicated first data; and writing the first data and the duplicated first data into the memory at continuously... Agent: Kirton And Mcconkie

20080225566 - Using efuses to store pll configuration data: A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080225567 - Method and structure for increasing effective transistor width in memory arrays with dual bitlines: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to... Agent: Cantor Colburn, LLP - IBM Arc Division

20080225568 - Dense read-only memory: In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting,... Agent: Macpherson Kwok Chen & Heid LLP

20080225569 - Ferroelectric capacitor and its manufacturing method: A ferroelectric capacitor includes: a ferroelectric film, and a lower electrode and an upper electrode interposing the ferroelectric film, wherein the ferroelectric film includes a first ferroelectric layer of ferroelectric material having a perovskite type crystal structure expressed by a general formula ABO3 formed by a metal organic chemical vapor... Agent: Harness, Dickey & Pierce, P.L.C

20080225570 - Over-driven access method and device for ferroelectric memory: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line /bit-line voltage... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080225571 - Complementary bit pcram sense amplifier and method of operation: A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low... Agent: Dickstein Shapiro LLP

20080225572 - Circuit arrays having cells with combinations of transistors and nanotube switching elements: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and... Agent: Wilmerhale/boston

20080225573 - Static random access memory cell with improved stability: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and... Agent: Ryan, Mason & Lewis, LLP

20080225574 - Memory cell with independent-gate controlled access devices and memory using the cell: A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the... Agent: Ryan, Mason & Lewis, LLP

20080225575 - Multi-state memory and multi-functional devices comprising magnetoplastic or magnetoelastic materials: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is... Agent: Pedersen & Company, PLLC

20080225577 - Magnetic random access memory, and write method and manufacturing method of the same: A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080225576 - Method of magnetic tunneling junction pattern layout for magnetic random access memory: An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer... Agent: Stephen B. Ackerman

20080225579 - Memory architecture and method of manufacture and operation thereof: An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a... Agent: Dickstein Shapiro LLP

20080225580 - Resistance variable memory with temperature tolerant materials: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.... Agent: Dickstein Shapiro LLP

20080225578 - Structure for increasing effective transistor witdth in memory arrays with dual bitlines: A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to... Agent: Cantor Colburn, LLP - IBM Arc Division

20080225581 - Memory device and memory: A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information... Agent: Bell, Boyd & Lloyd, LLP

20080225582 - Thin film magnetic memory device capable of conducting stable data read and write operations: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic... Agent: Mcdermott Will & Emery LLP

20080225585 - Low cost multi-state magnetic memory: An embodiment of the present invention includes a multi-state current-switching magnetic memory element having a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when... Agent: Law Offices Of Imam

20080225586 - Low magnetization materials for high performance magnetic memory devices: Techniques for attaining high performance magnetic memory devices are provided. In one aspect, a magnetic memory device comprising one or more free magnetic layers is provided. The one or more free magnetic layers comprise a low magnetization material adapted to have a saturation magnetization of less than or equal to... Agent: Ryan, Mason & Lewis, LLP

20080225584 - Magnetic storage element responsive to spin polarized current: The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the... Agent: Kinney & Lange, P.A.

20080225583 - Spin transfer mram device with novel magnetic free layer: We describe a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel free... Agent: Stephen B. Ackerman

20080225588 - Capacitorless dram and method of manufacturing and operating the same: Provided are a capacitorless dynamic random access memory (DRAM) and a method of manufacturing and operating the capacitorless DRAM. The capacitorless DRAM includes a substrate having a first dopant region formed on the upper part thereof, a first protrusion unit formed on the substrate, a first gate and a second... Agent: Harness, Dickey & Pierce, P.L.C

20080225587 - Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays: The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.... Agent: Slater & Matsil, L.L.P.

20080225589 - Memory page boosting method, device and system: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When... Agent: Trask Britt, P.C./ Micron Technology

20080225590 - Apparatus and method for integrating nonvolatile memory capability within sram devices: A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices... Agent: Cantor Colburn LLP-ibm Burlington

20080225591 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080225592 - Nonvolatile semiconductor memory device: With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be erased, a voltage of the P-type well is applied to all word lines... Agent: Mcdermott Will & Emery LLP

20080225593 - Single poly eeprom without separate control gate nor erase regions: A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein the source-to-floating gate capacitance is substantially greater than the drain-to-floating gate capacitance.... Agent: Texas Instruments Incorporated

20080225594 - Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell nand flash array: A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the... Agent: Saile Ackerman LLC

20080225595 - Charge trap type non-volatile memory device and program method thereof: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory... Agent: Townsend And Townsend And Crew, LLP

20080225598 - Flash memory and method for checking status register by block unit: Provided is a test method of a NAND flash memory. The method includes programming a page of a selected memory block in the flash memory; accumulating a program result of the page; and repeating the programming of other pages and the accumulating of the program result of the other pages... Agent: Mills & Onello LLP

20080225596 - High accuracy adaptive programming: Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change... Agent: Amin, Turocy & Calvin, LLP

20080225597 - Method of detecting an under program cell in a non-volatile memory device and method of programming the under program cell using the same: A method of detecting an under program cell includes detecting second memory cells of programmed first memory cells. A threshold voltage of the second memory cell is higher than a first verifying voltage. A third memory cell is detected in the second memory cells. A threshold voltage of the third... Agent: Townsend And Townsend And Crew, LLP

20080225599 - Flash memory device with reduced coupling effect among cells and method of driving the same: Embodiments of the invention provide a flash memory device that can improve the reliability of a reading operation by minimizing a variation in the threshold voltage distribution that occurs due to coupling between cells, and a method of driving the flash memory device. In an embodiment of the invention, the... Agent: Volentine & Whitt PLLC

20080225600 - Method of reading data in a non-volatile memory device: A method of reading data in a non-volatile memory device includes providing a plurality of blocks and a plurality of bit lines, each block having a plurality of memory cells, each block coupled to at least one bit line. Frst and second bit lines are discharged to be at a... Agent: Townsend And Townsend And Crew, LLP

20080225602 - Data processing system and nonvolatile memory: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells... Agent: Miles & Stockbridge PC

20080225601 - Eeprom memory device with cell having nmos in a p pocket as a control gate, pmos program/erase transistor, and pmos access transistor in a common well: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate,... Agent: Orion Law Group, PLC

20080225603 - Circuit: An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to... Agent: Slater & Matsil, L.L.P.

20080225606 - Data output circuit and method in ddr synchronous semiconductor device: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output.... Agent: Marger Johnson & Mccollom, P.C.

20080225605 - Latch structure and bit line sense amplifier structure including the same: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter.... Agent: Baker & Mckenzie LLP Patent Department

20080225604 - Semiconductor memory device: A semiconductor memory having a plurality of memory cells coupled to bit lines includes a bit line selecting circuit, a latch circuit, and a switching circuit. The bit line selecting circuit is disposed in a cell area where the memory cells are formed. The bit line selecting circuit is configured... Agent: Townsend And Townsend And Crew, LLP

20080225607 - Division-based sensing and partitioning of electronic memory: Providing distinction between overlapping threshold levels of one or more multi-cell memory devices is described herein. By way of example, a system can include a sensing component that can measure a level associated with a first memory cell. The system can also include a comparison component that can compare the... Agent: Amin, Turocy & Calvin, LLP

20080225608 - Semiconductor memory device and control signal generating method thereof: A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate... Agent: Marger Johnson & Mccollom, P.C.

20080225609 - Voltage generating circuit and reference voltage generating circuit for semiconductor memory apparatus, and semiconductor system using the same: A voltage generating circuit for a semiconductor memory apparatus according includes a data logic voltage generating unit that, when a data output unit outside a semiconductor memory apparatus outputs low-level data, generates an internal data logic voltage at the same potential level as the low-level data in response to an... Agent: Baker & Mckenzie LLP Patent Department

20080225611 - Method and apparatus for improving sram cell stabilty by using boosted word lines: The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′)... Agent: Scully, Scott, Murphy & Presser, P.C.

20080225610 - Write driver of semiconductor memory device and driving method thereof: A write driver of a semiconductor memory device over drives a local input/output line at a write operation in order to transmit data provided in a global input/output line to a core area at a stable voltage level. Therefore the write driver charges a stable voltage level corresponding to data... Agent: Mcdermott Will & Emery LLP

20080225612 - Semiconductor memory device: According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to... Agent: Arent Fox LLP

20080225613 - Memory row and column redundancy: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row... Agent: Macpherson Kwok Chen & Heid LLP

20080225614 - Method and system for reducing volatile memory dram power budget: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080225615 - Pulsed ring oscillator circuit for storage cell read timing evaluation: A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080225617 - Method for high speed sensing for extra low voltage dram: A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and... Agent: Duane Morris LLPIPDepartment (tsmc)

20080225616 - Method for increasing retention time in dram: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit... Agent: Duane Morris LLPIPDepartment (tsmc)

20080225618 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080225619 - Semiconductor memory, memory controller, system, and operating method of semiconductor memory: When a main block address held in a memory refresh address counter coincides with an access block address corresponding to an access request, its counter value is transferred to a sub refresh address counter. Thereafter, a sub refresh address counter operates with priority over a main refresh address counter until... Agent: Arent Fox LLP

20080225620 - Semiconductor memory device: In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080225621 - Static random access memory system and control method for static random access memory system: A static random access memory system used within a microprocessor includes a static random access memory array including a plurality of static random access memories, a storage unit configured to store a context ID used in the execution of a program or a process in association with an access pattern... Agent: Greer, Burns & Crain

20080225622 - Semiconductor memory device, operational processing device and storage system: A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.... Agent: Buchanan, Ingersoll & Rooney PC

20080225623 - Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to... Agent: Myers Bigel Sibley & Sajovec

20080225627 - Apparatus for memory device wordline: A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower... Agent: Trask Britt, P.C./ Micron Technology

20080225626 - Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the... Agent: Marger Johnson & Mccollom, P.C.

20080225624 - High speed array pipeline architecture: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being... Agent: Jones Day

20080225625 - Page mode access for non-volatile memory arrays: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry... Agent: Ovonyx, Inc

20080225628 - Semiconductor memory device for driving a word line: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of... Agent: Mcdermott Will & Emery LLP

20080225629 - Memory control device: A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output... Agent: Dickstein Shapiro LLP

20080225630 - Method and apparatus for initialization of read latency tracking circuit in high-speed dram: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of... Agent: Jones Day

20080219037 - Integrated circuit, memory device, method of operating an integrated circuit, and method of designing an integrated circuit: An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of logical elements and a bus carrying signals for said plurality of logical elements. The integrated circuit also comprises a routing... Agent: Lee & Hayes, Pllc

20080219038 - Ferroelectric memory device: Disclosed is a ferroelectric memory device. Multiple memory cells are connected between bit lines and a plate line, and constitute a memory cell array. Each of the memory cells is composed of a first ferroelectric capacitor and a memory cell transistor. The gates of the memory cell transistors are connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080219040 - Method to prevent overreset: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a... Agent: Eschweiler & Associates, Llc National City Bank Building

20080219039 - Nonvolatile memory elements with metal-deficient resistive-switching metal oxides: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in... Agent: G. Victor Treyz

20080219041 - Processing systems and methods for molecular memory: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be... Agent: Morgan, Lewis & Bockius, LLP.

20080219042 - Magnetic memory cell: By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the... Agent: Stephen B. Ackerman

20080219044 - Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory: Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from... Agent: Qualcomm Incorporated

20080219045 - Semiconductor memory device and magneto-logic circuit: Provided are a semiconductor memory device and a magneto-logic circuit which change the direction of a magnetically induced current according to a logical combination of logic states of a plurality of input values. The semiconductor memory device comprises a current driving circuit, a magnetic induction layer, and a resistance-variable element.... Agent: Harness, Dickey & Pierce, P.L.C

20080219043 - Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory: Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can... Agent: Qualcomm Incorporated

20080219047 - Apparatus and method for writing data to phase-change memory by using power calculation and data inversion: Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or... Agent: Cantor Colburn, LLP

20080219046 - Writing method and system for a phase change memory: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the... Agent: Birch Stewart Kolasch & Birch

20080219048 - Multibit electro-mechanical memory device and method of manufacturing the same: A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad... Agent: Mills & Onello LLP

20080219049 - Electrically alterable non-volatile memory with n-bits per cell: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of... Agent: Miles & Stockbridge Pc

20080219050 - Reduction of back pattern dependency effects in memory devices: A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least... Agent: Darby & Darby P.c.

20080219051 - System that compensates for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20080219052 - Always-evaluated zero standby-current programmable non-volatile memory: In an integrated circuit device, a continuous-output, zero-standby-current non-volatile storage cell is formed by P-MOS and N-MOS transistor elements coupled in series between first and second power supply nodes (e.g., VDD and ground) and having a shared floating gate. When a positive charge is stored on the shared floating gate,... Agent: Shemwell Mahamedi LLP

20080219053 - Partial block erase architecture for flash memory: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore,... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080219054 - Semiconductor memory device and method of manufacturing of the same: A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080219055 - Multiple level programming in a non-volatile memory device: The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20080219056 - System that compensates for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20080219057 - Non-volatile memory with cache page copy: A non-volatile memory and methods includes cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080219058 - Semiconductor memory device which stores plural data in a cell: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080219059 - Method for cache page copy in a non-volatile memory: A non-volatile memory and methods include cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080219063 - System and method of selective row energization based on write data: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform... Agent: Ibm Corporation (jvm)

20080219060 - Device and method for internal voltage monitoring: A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the... Agent: Dicke, Billig & Czaja

20080219061 - Apparatus and method for detecting leakage current of semiconductor memory device, and internal voltage generating circuit using the same: A semiconductor memory device is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory devices, thereby minimizing the amount of the leakage current. The semiconductor memory device includes a leakage current detector and a back bias voltage... Agent: Rabin & Berdo, Pc

20080219062 - Semiconductor memory device: In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of the pairs including a first bit line, a second bit line, a memory cell coupled to the first bit line, a sense amplifier determining the logical value stored in the memory cell according... Agent: Young & Thompson

20080219064 - Semiconductor memory apparatus with write training function: A semiconductor memory apparatus having a write training function includes a storage unit that stores write data or read data output from a memory cell block and outputs data according to an output control signal, and a control unit that controls the output control signal to be generated at different... Agent: Venable LLP

20080219065 - Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a... Agent: F. Chau & Associates, Llc

20080219066 - Memory system and method ensuring read data stability: A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a... Agent: Volentine & Whitt Pllc

20080219067 - Individual i/o modulation in memory devices: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner... Agent: Dickstein Shapiro LLP

20080219068 - Zq calibration controller and method for zq calibration: A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an... Agent: Rabin & Berdo, Pc

20080219069 - Device threshold calibration through state dependent burnin: Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080219070 - Semiconductor memory device: A semiconductor memory device includes: memory cells respectively arranged on intersecting points of a plurality of word lines and a plurality of data lines, and respectively having a capacitor for storing data; a sense amplifier provided in between the data lines forming a data line pair so as to amplify... Agent: Sughrue Mion, Pllc

20080219071 - Data flow scheme for low power dram: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required... Agent: Saile Ackerman Llc

20080219072 - Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit: A high-density dynamic memory device with compact sense amplifier circuit is described. The memory device achieves high density through the use of a compact sense amplifier circuit that employs a single transistor to sense stored dynamic data. Functionality of the device is enabled by an architecture and method of operation... Agent: Duncan Elliott

20080219073 - Semiconductor memory device and method for driving the same: A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory... Agent: Mcdermott Will & Emery LLP

20080219074 - Abbreviated burst data transfers for semiconductor memory: An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank, prefetching less than the nominal data prefetch size, and providing the data in an abbreviated burst data transfer less... Agent: Coats & Bennett/qimonda

20080219075 - Control of inputs to a memory device: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy... Agent: Knobbe Martens Olson & Bear LLP

20080219077 - Internal voltage generation circuit and method for semiconductor device: An internal voltage generation circuit for a semiconductor device and method therefor includes a voltage generator configured to generate voltages with different levels by using an external voltage. A code storing unit is configured to store a selection code to select an internal voltage out of the plurality of voltages.... Agent: Rabin & Berdo, Pc

20080219078 - Memory system and method of controlling the same: One aspect in accordance with the present invention provides a memory system receiving a power supply from a host device. The memory system includes a non-volatile semiconductor memory and a controller for controlling writing and reading data to and from the semiconductor memory. The controller operates in such a manner... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080219076 - Semiconductor circuits: Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a... Agent: Quintero Law Office, Pc

20080219079 - Semiconductor memory device and output drive circuit thereof: An apparatus for supplying current to a semiconductor memory device. A current supply circuit supplies current to an input/output (I/O) drive circuit responsive to a pattern of data input to the I/O drive circuit. The current supply circuit configured to supply current generated by an external voltage to the I/O... Agent: Marger Johnson & Mccollom, P.c.

20080219080 - Memory device with reduced standby power consumption and method for operating same: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080219081 - Semiconductor memory apparatus: A semiconductor memory apparatus includes first and second data storing/processing sections that have memory areas in a bank and the first and second data storing/processing sections share a circuit block that inputs and outputs the data, and a signal line that transmits the data.... Agent: Baker & Mckenzie LLP Patent Department

20080219082 - Nonvolatile semiconductor memory: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080219083 - Semiconductor memory device and power control method thereof: A semiconductor memory device for saving power consumption and control method thereof are disclosed. The clock frequency on memory chips is dynamically adjusted to match the data transferring rate between the other units in computer system and the memory chips. A fill state of buffer and transferring rate on an... Agent: Troxell Law Office Pllc

20080212350 - Cam asynchronous search-line switching: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A... Agent: Robert A. Walsh

20080212352 - Multi-layer semiconductor memory device comprising error checking and correction (ecc) engine and related ecc method: Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes... Agent: Volentine & Whitt PLLC

20080212351 - Pin configuration changing circuit, base chip and system in package including the same: A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the... Agent: Mills & Onello LLP

20080212353 - Sram design with separated vss: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of... Agent: Slater & Matsil, L.L.P.

20080212354 - Biased sensing module: A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080212355 - Compact virtual ground diffusion programmable rom array architecture, system and method: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared... Agent: Shreen K. Danamraj Danamraj & Emanuelson, P.C.

20080212356 - Random access memory featuring reduced leakage current, and method for writing the same: The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal.... Agent: Maginot, Moor & Beck

20080212357 - Simultaneous read circuit for multiple memory cells: A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state.... Agent: Dickstein Shapiro LLP

20080212358 - Method for manufacturing ferroelectric memory device and ferroelectric memory device: A method for manufacturing a ferroelectric memory device includes: forming a conductive base layer above a substrate; and laminating above the base layer a first electrode, a ferroelectric layer and a second electrode, wherein, prior to the step of forming the base layer, the method includes forming an active element... Agent: Harness, Dickey & Pierce, P.L.C

20080212359 - Memory device and semiconductor integrated circuit: First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the... Agent: Mcdermott Will & Emery LLP

20080212360 - Persistent volatile memory cell: A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point... Agent: Seed Intellectual Property Law Group PLLC

20080212361 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode... Agent: Wilmerhale/boston

20080212362 - Control of set/reset pulse in response to peripheral temperature in pram device: A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For... Agent: Law Office Of Monica H Choi

20080212363 - Method for programming phase-change memory and method for reading date from the same: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold... Agent: Sughrue Mion, PLLC

20080212364 - Magnetic memory cell and method of fabricating same: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array... Agent: Hahn And Moodley, LLP

20080212365 - Scalable magnetic random access memory device: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent... Agent: Michael J. Chang, LLC

20080212366 - Semiconductor memory device: This disclosure concerns a semiconductor memory device comprising Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080212368 - Data verification method and semiconductor memory: A semiconductor memory device storing multi-bit write data and a related method of verifying data programmed to a memory cell are disclosed. The method compares a write data reference bit selected from the write data with a corresponding external data bit indicative of an intended write data bit value, and... Agent: Volentine & Whitt PLLC

20080212369 - Method of managing a memory device employing three-level cells: A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080212367 - Method of operating a flash memory device: In a method of operating a flash memory device including a memory cell array having a Multi-Level Cell (MLC) for storing plural bit data, a first memory block included in the MLC is selected. First to Mth word lines are selected while increasing from a first column line to an... Agent: Townsend And Townsend And Crew, LLP

20080212371 - Non-volatile memory copy back: Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory controller for data repair... Agent: Schwegman, Lundberg & Woessner/micron

20080212370 - Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080212372 - Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same: A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of... Agent: Myers Bigel Sibley & Sajovec

20080212373 - Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080212374 - Novel multi-state memory: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080212375 - Method of programming and erasing a p-channel be-sonos nand flash memory: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.... Agent: Jianq Chyun Intellectual Property Office

20080212376 - Methods of operating and manufacturing logic device and semiconductor device including complementary nonvolatile memory device, and reading circuit for the same: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and... Agent: Lee & Morse, P.C.

20080212378 - Data latch controller of synchronous memory device: Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the... Agent: Ladas & Parry LLP

20080212377 - Semiconductor memory device: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a pair of bit lines connected to the memory cells, and transmitting data of the memory cells; a pair of sense nodes connected to the bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080212380 - Self-refresh control circuit for detecting current flowing from current generator and semiconductor device including same: A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating... Agent: Mcginn Intellectual Property Law Group, PLLC

20080212379 - Semiconductor memory device: When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not... Agent: Stroock & Stroock & Lavan LLP

20080212381 - Voltage generating circuits for semiconductor memory devices and methods for the same: In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have different voltage levels. An output voltage generator generates a... Agent: Harness, Dickey & Pierce, P.L.C

20080212382 - Crossbar waveform driver circuit: A driving waveform circuit includes a crossbar array having input columns and output rows wherein the crossbar array is configured to store data in the form of high or low resistance states, delay timing circuitry electrically connecting an input signal to the input columns of the crossbar array and configured... Agent: Blaise Mouttet

20080212383 - Circuit and method for parallel test of memory device: A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line... Agent: Mcdermott Will & Emery LLP

20080212384 - Sense amp circuit, and semiconductor memory device using the same: A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at least one of the pair of first differential output signals reaching a certain voltage and provides an activation signal. A latch-type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080212385 - Output driver: According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of... Agent: Infineon Technologies North America Corp.

20080212386 - Semiconductor memory device, semiconductor device, memory system and refresh control method: A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held... Agent: Sughrue Mion, PLLC

20080212387 - Integrated circuit fuse array: The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly... Agent: Freescale Semiconductor, Inc. Law Department

20080212388 - Integrated circuit fuse array: The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly... Agent: Freescale Semiconductor, Inc. Law Department

20080212390 - Bulk bias voltage level detector in semiconductor memory device: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080212389 - Sdram with reset function: A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes a low voltage MOS input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is... Agent: Townsend And Townsend And Crew, LLP

20080212391 - Low power multi-chip semiconductor memory device and chip enable method thereof: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.... Agent: Volentine & Whitt PLLC

20080212392 - Multiple port mugfet sram: A circuit includes a multi gate field effect transistor based static random access memory device having a cross coupled inverter cell. A first set of multi gate field effect transistor access devices are coupled to the memory device to provide a first port. A second set of multi gate field... Agent: Schwegman, Lundberg & Woessner / Infineon

20080212396 - Delay mechanism for unbalanced read/write paths in domino sram arrays: A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080212395 - Driver, and a semiconductor, memory device having the same: A driver may include a driving unit and/or a boosting unit. The driving unit may be configured to provide a driving signal to at least one load. The boosting unit may be configured to boost the driving signal based on transition time points of the driving signal to reduce a... Agent: Harness, Dickey & Pierce, P.L.C

20080212393 - Semiconductor memory device: A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address... Agent: Mcdermott Will & Emery LLP

20080212394 - Write driving circuit and semiconductor memory apparatus using the same: A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units.... Agent: Baker & Mckenzie LLP Patent Department