Static information storage and retrieval inventions 08/08

20080205110 - Digital magnetic current sensor and logic: A sensor for sensing magnetic field strength has a sensor element, and detection circuitry for detecting a level of resistance of the sensor element, the level of resistance varying with magnetic field under test and having hysteresis, so that upon electromagnetic excitation the resistance can switch between two or more... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080205111 - Semiconductor memory device and defect remedying method thereof: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080205112 - Apparatus for hardening a static random access memory cell from single event upsets: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a... Agent: Dillon & Yudell LLP

20080205113 - Inter-transmission multi memory chip, system including the same and associated method: A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.... Agent: Lee & Morse, P.c.

20080205114 - Semiconductor memory device and method of operating same: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the... Agent: Neil Steinberg

20080205115 - Apparatus and method for trimming integrated circuit: A trimming apparatus including a switch transistor and a one-time programming (OTP) memory component is provided. The switch transistor has a first source/drain terminal connected to a first bias voltage, a gate terminal used for receiving a switch signal, and a second source/drain terminal connected to a first source/drain terminal... Agent: J C Patents, Inc.

20080205116 - Three-dimensional magnetic memory: Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. Bits may be written to a data storage layer in the form of magnetic domains. The bits can then be transferred between the stacked... Agent: Duft Bornsen & Fishman, LLP

20080205117 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205118 - Integrated circuit having a resistive switching device: An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume... Agent: Dicke, Billig & Czaja

20080205119 - Non-volatile semiconductor memory device: In order to determine data stored in a memory cell of a resistive cross-point cell array, two reference cells having two different known resistance values (e.g., data “0” and data “1”) are provided, and a difference in current between a selected cell and the reference cell having data “0” and... Agent: Mcdermott Will & Emery LLP

20080205120 - Multiple layer random accessing memory: The present invention provides a new semiconductor Random Access Memory, RAM which stores multiple bits per cell. When writing data, at least three levels of voltage sources are generated to charge the bit line and the RAM capacitive device through the selective devices. During reading data, at least three referencing... Agent: Chih-ta Star Sung

20080205121 - Current driven memory cells having enhanced current and enhanced current symmetry: A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents... Agent: Strategic Patent Group, P.c.

20080205126 - Magnetic random access memory: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205123 - Magnetic random access memory and method of reducing critical current of the same: A magnetic random access memory includes a substrate, a free layer and a spacer layer. The substrate and the free layer are made of a vertical anisotropy ferrimagentic thin film. The spacer layer is sandwiched between the substrate and the free layer and is made of an insulating layer. The... Agent: Pai Patent & Trademark Law Firm

20080205125 - Magnetic random access memory and write method thereof: A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205122 - Mram memory conditioning: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080205124 - Semiconductor memory device and data write and read methods of the same: A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205128 - Phase change memory device: A phase change memory device has a memory cell that uses a phase change film as a storage element, and includes: a first phase change region formed on a side of one face of the phase change film; and a second phase change region formed on a side of another... Agent: Young & Thompson

20080205127 - Phase change storage cells for memory devices: Storage cells for a semiconductor device can include a first layer of phase change material on a substrate and a second layer of phase change material being in contact with the first layer, the second layer of phase change material having a higher resistance than the first layer.... Agent: Timothy J. O'sullivan Myers Bigel Sibley & Sajovec

20080205129 - Non-volatile magnetic memory device: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second... Agent: Morgan Lewis & Bockius LLP

20080205131 - Magnetic random access memory with selective toggle memory cells: A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni˜0.8Fe˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher... Agent: Saile Ackerman Llc

20080205130 - Mram free layer synthetic antiferromagnet structure and methods: A magnetic tunnel junction (MTJ) structure for use with toggle MRAM devices and the like includes a tunnel barrier layer and a synthetic antiferromagnet (SAF) structure formed on the tunnel barrier layer, wherein the SAF includes a plurality (e.g., three or more) ferromagnetic layers antiferromagnetically or ferromagnetically coupled by a... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080205132 - Memory element and semiconductor device, and method for manufacturing the same: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080205133 - Capacitor-less volatile memory cell, device, system and method of making same: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line.... Agent: Trask Britt, P.c./ Micron Technology

20080205140 - Bit line structure for a multilevel, dual-sided nonvolatile memory cell array: A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string... Agent: Saile Ackerman Llc

20080205141 - Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell: A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate... Agent: Saile Ackerman Llc

20080205138 - Memory device and method of operating the same: A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification.... Agent: Townsend And Townsend And Crew, LLP

20080205139 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each having a plurality of threshold levels corresponding to a plurality of programming data respectively; a voltage generator circuit which generates a plurality of programming voltage pulses and a plurality of verify voltage pulses... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205136 - Read method of memory device: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read... Agent: Townsend And Townsend And Crew, LLP

20080205137 - Semiconductor memory device and control method of the same: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205143 - Nonvolatile semiconductor memory device having protection function for each memory block: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205145 - Memory controller controlling semiconductor storage device and semiconductor device: A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.l.p.

20080205144 - Nonvolatile semiconductor memory device: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device,... Agent: Mcdermott Will & Emery LLP

20080205146 - Nonvolatile ram: A nonvolatile RAM for reading and writing data in a random manner includes a memory area configured by a plurality of memory cells suited to a nonvolatile-mode write operation, in which the stored content thereof is not lost irrespective of a power-off event, and a volatile-mode write operation, in which... Agent: Mcginn Intellectual Property Law Group, Pllc

20080205147 - Local self-boost inhibit scheme with shielded word line: A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of... Agent: Leffert Jay & Polglaze, P.a. Attn: Andrew C. Walseth

20080205148 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205152 - Flash memory device for over-sampling read and interfacing method thereof: A memory system having a flash memory device that performs an over-sampling read operation to read data from a memory cell in the flash device by using an over-sampling read voltage that falls within a threshold voltage distribution range. A memory controller supplies a read mode signal to the flash... Agent: Volentine & Whitt Pllc

20080205150 - Hybrid non-volatile memory: A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that... Agent: Merchant & Gould Impinj

20080205153 - Method and apparatus for controlling two or more non-volatile memory devices: A method and apparatus for controlling two or more non-volatile memory devices includes activating a read enable signal or a write enable signal, which is input to the first and second non-volatile memory devices, using a controller. A first chip enable signal is alternately activated for selecting the first non-volatile... Agent: Volentine & Whitt Pllc

20080205149 - Method of programming non-volatile memory device: A method of programming a non-volatile memory device enables a pump in response to a first program confirm command. The pump generates a voltage. An initial page of a memory block is programmed. Subsequent intermediate pages of the memory block are programmed in response to a second program confirm command... Agent: Townsend And Townsend And Crew, LLP

20080205151 - Non-volatile memory device and method of driving the same: A non-volatile memory device capable of stably setting its operating environment and a method of driving the non-volatile memory device are provided. The method includes providing power to the non-volatile memory device having a memory cell array that stores initial setting data for setting the operating environment of the non-volatile... Agent: F. Chau & Associates, Llc

20080205154 - Semiconductor memory device: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080205156 - Method of operating nonvolatile memory device: Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.... Agent: Harness, Dickey & Pierce, P.L.C

20080205157 - Method of operating nonvolatile memory device: Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase... Agent: Harness, Dickey & Pierce, P.L.C

20080205155 - Systems and methods to reduce interference between memory cells: Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page... Agent: Schwegman, Lundberg & Woessner, P.a.

20080205134 - Charge pump to supply voltage bands: This voltage generating circuit comprises a first charge pump unit to which a first clock signal is inputted, wherein the first charge pump unit generates a voltage by pumping a voltage of a first external power supply in stages by a first voltage, a voltage selector that selects the voltage... Agent: Spansion Llc C/o Murabito , Hao & Barnes LLP

20080205135 - Method of reading the bits of nitride read-only memory cell: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according... Agent: Birch Stewart Kolasch & Birch

20080205158 - Reading method and circuit for a non-volatile memory device based on the adaptive generation of a reference electrical quantity: A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a determination stage, which compares an array electrical quantity, correlated to a current flowing in the array... Agent: Graybeal, Jackson, Haley LLP

20080205160 - Non-volatile memory devices and operating methods thereof: Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage... Agent: Harness, Dickey & Pierce, P.L.C

20080205159 - Verification process of a flash memory: A verification process is disclosed for verifying correctness of a data status of a flash memory after data of the flash memory is altered. The flash memory has a plurality of memory cells array and a volatile memory. The verification process includes reading memory-cell verification data stored in the volatile... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080205161 - Flash memory device utilizing multi-page program method: A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and... Agent: Volentine & Whitt Pllc

20080205162 - Non-volatile memory device and driving method thereof: This patent relates to a non-volatile memory device and a driving method thereof The non-volatile memory device includes a source select line in which a floating gate and a control gate are electrically connected to each other, a drain select line in which a floating gate and a control gate... Agent: Marshall, Gerstein & Borun LLP

20080205163 - Nonvolatile memory device and driving method thereof: Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution... Agent: Volentine & Whitt Pllc

20080205164 - Decoding control with address transition detection in page erase function: Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event... Agent: Smart & Biggar P.o. Box 2999, Station D

20080205165 - Semiconductor memory device: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data... Agent: Arent Fox LLP

20080205166 - Trapping storage flash memory cell structure with inversion source and drain regions: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080205142 - Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same: An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage... Agent: F. Chau & Associates, Llc

20080205167 - Voltage generator for nonvolatile memory and writing and erasing method of nonvolatile memory: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with... Agent: Mcginn Intellectual Property Law Group, Pllc

20080205168 - Apparatus and method for using a page buffer of a memory device as a temporary cache: An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows... Agent: Mosaid Technologies Incorporated

20080205169 - Device for storing a binary state: Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the... Agent: Dickstein Shapiro LLP

20080205170 - Ddr-sdram interface circuitry, and method and system for testing the interface circuitry: According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data strobe signal, the memory interface circuit comprising: a first delay-locked loop circuit that adjusts a delay of... Agent: Arent Fox LLP

20080205171 - Redundant cross point switching system and method: A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the... Agent: Iandiorio & Teska

20080205172 - Design-for-test micro probe: Systems and techniques for testing a device having first and second interconnected chips that are internal to the device include selecting a site on a communication pathway along which an internal signal travels inside the device between the first and second chips, and connecting a test probe to the site.... Agent: Fish & Richardson P.c.

20080205173 - Method and system for testing an integrated circuit: s

20080205174 - Semiconductor memory device and test method thereof: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data... Agent: Harness, Dickey & Pierce, P.L.C

20080205175 - Auto-precharge control circuit in semiconductor memory and method thereof: An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may... Agent: Harness, Dickey & Pierce, P.L.C

20080205178 - Dram writing ahead of sensing scheme: This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080205177 - Layout structure of semiconductor memory device having iosa: Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output... Agent: Volentine & Whitt Pllc

20080205176 - Memory having a dummy bitline for timing control: A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least... Agent: Freescale Semiconductor, Inc. Law Department

20080205179 - Integrated circuit having a memory array: One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line... Agent: Dicke, Billig & Czaja

20080205180 - Semiconductor memory device having bit-line sense amplifier: A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes: a unit memory cell for storing a data; a sense amplification unit including a bit-line sense amplifier (BLSA) for sensing and amplifying... Agent: Mcdermott Will & Emery LLP

20080205181 - Semiconductor storage device: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080205182 - Method of operating a memory cell, memory cell and memory unit: A method of operating a memory cell, a memory cell and a memory unit are described. For example, a memory cell comprises a capacitance and an access circuit in association with said capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust... Agent: Slater & Matsil LLP

20080205183 - Self-refresh control circuit and semiconductor memory device including the same: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator... Agent: Volentine & Whitt Pllc

20080205184 - Semiconductor memory device: This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a... Agent: Miles & Stockbridge Pc

20080205185 - Semiconductor memory device and its driving method: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower unit memory cell arrays and a switching controller. The bit line sense amplifier block array senses and amplifies data of a unit memory cell array. The upper and the lower unit memory cell arrays are... Agent: Mcdermott Will & Emery LLP

20080205186 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked... Agent: Mcdermott Will & Emery LLP

20080205187 - Data flow control in multiple independent port: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that... Agent: Mosaid Technologies Incorporated

20080198640 - Data storage device: In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across... Agent: Birch Stewart Kolasch & Birch

20080198641 - Semiconductor integrated circuit device and layout method thereof: A semiconductor integrated circuit device includes a memory macro and M (N is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which are arranged in a matrix, digit line pairs connected with the memory cells and extending in a column... Agent: Young & Thompson

20080198643 - One-time programmable cell and memory device having the same: One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured to form a current path between a third... Agent: Morgan Lewis & Bockius LLP

20080198642 - Semiconductor memory device: A memory cell includes an antifuse device that is capable of having data written thereto by breakdown of a gate dielectric film by application of a high voltage. A data inversion portion generates, according to a relationship between the sense amplifier's determination and write data to be written to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198644 - Data storage device: In a non-volatile electric memory system a memory unit (4) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the... Agent: Birch Stewart Kolasch & Birch

20080198645 - Nonvolatile memory device having memory and reference cells: A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and... Agent: Volentine & Whitt PLLC

20080198646 - Nonvolatile memory device using resistance material: The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least... Agent: Volentine & Whitt PLLC

20080198647 - Method and apparatus for bitline and contact via integration in magnetic random access memory arrays: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction... Agent: Patterson & Sheridan, LLP

20080198648 - Writing method for magnetic memory cell and magnetic memory array structure: A writing method for a magnetic memory cell which has a magnetic free stack layer with a bi-directional easy axis. A magnetic X axis and a magnetic Y axis are taken as reference directions, and the bi-directional easy axis is substantially on the magnetic X axis. The method includes applying... Agent: Jianq Chyun Intellectual Property Office

20080198649 - Memory device and method of manufacturing a memory device: A memory device includes a bit line, a reading word line, a bit line contact, an electrode, a writing word line and a contact tip. The bit line is formed on a substrate. The reading word line is formed over the bit line. The bit line contact is disposed between... Agent: Mills & Onello LLP

20080198650 - Distortion estimation and cancellation in memory devices: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference... Agent: Darby & Darby P.C.

20080198653 - Circuit arrangement and method for operating a circuit arrangement: A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a... Agent: Dickstein Shapiro LLP

20080198652 - Memory device programming using combined shaping and linear spreading: A method for data storage includes accepting data for storage in a memory (28) that includes multiple analog memory cells (32). The data is converted to input values. The input values are filtered using a non-linear filtering operation to produce respective shaped values, and the shaped values are converted to... Agent: Darby & Darby P.C.

20080198651 - Non-volatile memory with dynamic multi-mode operation: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080198654 - Semiconductor memory device: A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198655 - Integrated circuit, method of reading data stored within a memory device of an integrated circuit, method of writing data into a memory device of an integrated circuit, memory module, and computer program: A memory device comprises a plurality of memory cells, each of which comprising a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, wherein the memory cells are grouped into memory cell groups, each memory cell group defining a memory cell... Agent: Slater & Matsil LLP

20080198656 - Time-dependent compensation currents in non-volatile memory read operations: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and... Agent: Vierra Magen/sandisk Corporation

20080198658 - Memory card, semiconductor device, and method of controlling memory card: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198657 - Non-volatile semiconductor memory having multiple external power supplies: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20080198659 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from the memory cell array and externally supplied expectance... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198660 - Multiple pass write sequence for non-volatile storage: A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting... Agent: Vierra Magen/sandisk Corporation

20080198661 - Non-volatile storage apparatus with variable initial program voltage magnitude: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional... Agent: Vierra Magen/sandisk Corporation

20080198662 - Dynamic verify based on threshold voltage distribution: After erasing a plurality of non-volatile storage elements, a soft programming process is performed to tighten the erase threshold distribution for the non-volatile storage elements. During the soft programming process, the system identifies the number of programming pulses needed for a first set of the non-volatile storage elements to complete... Agent: Vierra Magen/sandisk Corporation

20080198663 - Flash memory device and program method thereof: A flash memory device which comprises a memory cell array having memory cells arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage at a program operation; and a row selector circuit that receives... Agent: Mills & Onello LLP

20080198664 - Non-volatile storage apparatus with multiple pass write sequence: A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting... Agent: Vierra Magen/sandisk Corporation

20080198666 - Semiconductor device including adjustable driver output impedances: A semiconductor device is disclosed. In one embodiment, the device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to drive output signals and includes an adjustable output impedance. The second circuit is configured to adjust the adjustable output impedance. The third circuit... Agent: Dicke, Billig & Czaja

20080198665 - Variable initial program voltage magnitude for non-volatile storage: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional... Agent: Vierra Magen/sandisk Corporation

20080198668 - Nonvolatile semiconductor memory and driving method thereof: A nonvolatile semiconductor memory according to an aspect of the invention comprises a plurality of serially connected memory cells arranged on a P-well area within a semiconductor substrate, select gate transistors connected to one end and the other of the serially connected memory cells, a P-well control circuit which controls... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198667 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198669 - Method of operating non-volatile memory: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of... Agent: Jianq Chyun Intellectual Property Office

20080198670 - Reduced power programming of non-volatile cells: Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without... Agent: Empk & Shiloh, LLP

20080198671 - Enqueue event first-in, first-out buffer (fifo): In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, wherein each data item has... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20080198672 - Power supply control circuit and controlling method thereof: The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080198673 - Semiconductor memory device and driving method for the device: This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080198674 - Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit: A method for testing an integrated circuit having an array of resistivity changing cells, wherein the method includes selecting a plurality of cells, setting the state of each selected cell to a defined state, measuring a resistance value being dependent on the resistances of the selected cells, comparing the resistance... Agent: Slater & Matsil LLP

20080198675 - Semiconductor device including a plurality of memory units and method of testing the same: In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively,... Agent: Mills & Onello LLP

20080198676 - Semiconductor memory device and method with a changeable substrate potential: A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier.... Agent: Dicke, Billig & Czaja

20080198677 - Internal voltage detection circuit and internal voltage generation device using the same: An internal voltage detection circuit and an internal voltage generation device using the same are disclosed. The internal voltage detection circuit includes a first detect signal generator for generating a first detect signal to detect a level of an internal voltage corresponding to an operating temperature of a memory cell,... Agent: Cooper & Dunham, LLP

20080198678 - Programmable sram source bias scheme for use with switchable sram power supply sets of voltages: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is... Agent: Stmicroelectronics, Inc.

20080198679 - Sram with switchable power supply sets of voltages: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell... Agent: Stmicroelectronics, Inc.

20080198680 - Semiconductor memory device having input/output sense amplification circuit with reduced junction loading and circuit layout area: A semiconductor memory device includes an input/output sense amplifier that amplifies a read data and provides it to the external, when making a read operation. The semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each bank and output them as amplified signals; a controller... Agent: Ladas & Parry LLP

20080198681 - Multiple port memory with prioritized word line driver and method thereof: A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a... Agent: Freescale Semiconductor, Inc. Law Department

20080198682 - Semiconductor device and method for selection and de-selection of memory devices interconnected in series: A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared... Agent: Mosaid Technologies Incorporated

20080198683 - Semiconductor memory apparatus: A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address... Agent: Young & Thompson

20080198684 - Semiconductor memory integrated circuit: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch... Agent: Mcginn Intellectual Property Law Group, PLLC

20080192523 - Apparatus and method to detect patterns in data: In a method for detecting patterns, a plurality of data patterns is stored in a memory, and a data block from a stream of data is received. A first subset of the data block is compared in parallel to the plurality of data patterns. A second subset of the data... Agent: Marshall, Gerstein & Borun, LLP (marvell)

20080192524 - Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers: An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks... Agent: Zagorin O'brien Graham LLP (023)

20080192526 - Manufacturing method for an integrated semiconductor memory device and corresponding semiconductor memory device: The present invention provides an integrated semiconductor memory device comprising: a semiconductor substrate; a plurality of active area lines formed in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; a plurality... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080192527 - Semiconductor memory device and control method thereof: A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080192525 - Single-ended memory cell with improved read stability, memory using the cell, and methods of operating and designing same: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a... Agent: Ryan, Mason & Lewis, LLP

20080192528 - Piezoelectric reading of ferroelectric data storage media: An apparatus comprises mechanically scanned ferroelectric data storage media. A scanning electrode contacts the scannable surface with a contact force. The ferroelectric data storage media generates a piezoelectric potential that is picked up by the electrode. The piezoelectric potential has a polarity that varies as a function of data polarity... Agent: Seagate Technology Llc C/o Westman Champlin & Kelly, P.a.

20080192529 - Integrated circuit having a resistive memory: An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a... Agent: Dicke, Billig & Czaja

20080192531 - Method of writing into semiconductor memory device: An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080192530 - Resistive memory element sensing using averaging: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element... Agent: Dickstein Shapiro LLP

20080192532 - Hybrid circuit having nanotube memory cells: A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to... Agent: Wilmerhale/boston

20080192533 - Method of addressing digital data: A magnetic memory storage device with at least one magnetic storage element comprising electrical addressing leads to inject electrical current directly through a single magnetic memory storage element. The number of electrical addressing leads is at least one more than the number of magnetic memory storage elements.... Agent: Naval Research Laboratory Associate Counsel (patents)

20080192534 - Memory element with reduced-current phase change element: A memory device having a reduced-thickness phase change film is described along with methods for manufacture. The device includes an electrode element, in electrical contact with a phase change layer. The latter element is formed from a memory material having at least two solid phases. A top electrode element makes... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080192535 - Sense amplifiers and semiconductor devices including the same: A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the... Agent: Harness, Dickey & Pierce, P.L.C

20080192538 - Architecture and method for nand flash memory: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even... Agent: Leffert Jay & Polglaze, P.a. Attn: Daniel J. Polglaze

20080192539 - Memory system including mlc flash memory: A memory system includes a flash memory storing multi-bit data in one memory cell. A memory controller controls the flash memory to program the multi-bit data in the memory cell. The flash memory programs the multi-bit data in the memory cell in a single program operation.... Agent: F. Chau & Associates, Llc

20080192541 - Non-volatile memory device having monitoring memory cell and related method of driving using variable read voltage: A non-volatile memory device and related method of driving data are disclosed. The non-volatile memory device includes an array of multi level cells and a monitoring memory cell. The method of driving including performing a preliminary read operation with respect to a monitoring memory cell using a first read voltage,... Agent: Volentine & Whitt Pllc

20080192540 - Nonvolatile memory devices capable of reducing data programming time and methods of driving the same: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device... Agent: Harness, Dickey & Pierce, P.L.C

20080192542 - Memory system and data reading method thereof: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the... Agent: F. Chau & Associates, Llc

20080192544 - Error correction coding techniques for non-volatile memory: During programming of memory cells, calculating sigma bits for cells programmed at each program level based on attributes of the cells, such an index representing a cell's bit location in the memory array. For example, summing the indexes with an increasing weight factor, such as factor-of-2. During read, new sigma... Agent: Empk & Shiloh, LLP

20080192543 - Method and apparatus for selecting redundant memory cells: In a semiconductor memory which comprises a main memory array, redundant memory cells, and a plurality of repair fuse boxes, a method of selecting redundant memory cells in relation to repair fuse boxes, comprising testing redundant memory cells to determine whether they are valid or defective, and making a selection... Agent: Edell, Shapiro & Finnan, Llc

20080192546 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080192545 - Flash memory with sequential programming: A method of programming a group of memory cells in a semiconductor memory device selecting a group of memory cells for programming, and enabling a first subgroup of memory cells from the group of memory cells for programming. After enabling the first subgroup, the programming method waits a first predetermined... Agent: Duane Morris, LLP Ip Department

20080192547 - User configurable commands for flash memory: A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the boot data includes a reconfigured command, that command is loaded into the register. A signal... Agent: Leffert Jay & Polglaze, P.a.

20080192548 - Semiconductor memory system including a plurality of semiconductor memory devices: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080192549 - Nonvolatile semiconductor storage device and operation method thereof: To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080192536 - Bit line select voltage generator and nonvolatile memory device using the same: A bit line select voltage generator includes a first voltage generator, a second voltage generator, and a voltage transmission unit. The first voltage generator is configured to divide a reference voltage of a reference voltage generator, generate a control voltage, and generate a first voltage in response to the control... Agent: Townsend And Townsend And Crew, LLP

20080192537 - Semiconductor device and method for controlling the same: A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.... Agent: Ingrassia Fisher & Lorenz, P.c.

20080192550 - Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory: An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080192551 - Complementary output flip flop: A flip-flop has a master stage and two slave stages coupled to receive complementary outputs from the master stage. Each stage includes transfer gates and a bistable element in the form of cross-coupled inverters. The master stage bistable element switches states on a first edge of a clock signal in... Agent: Texas Instruments Incorporated

20080192552 - Internal address generator: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate... Agent: Mcdermott Will & Emery LLP

20080192553 - Non-imprinting memory with high speed erase: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same... Agent: North Weber & Baugh LLP

20080192554 - Semiconductor device and method of testing semiconductor device: A semiconductor device includes: a first memory; and a second memory. The first memory includes: a first memory cell array configured to be divided into a plurality of sectors, an erasure time setting register configured to hold a sector erasure assurance time to assure an erasure time for erasing data... Agent: Sughrue Mion, Pllc

20080192556 - Input-output line sense amplifier having adjustable output drive capability: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080192555 - Single ended sense amplifier for very low voltage applications: A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedance amplifier output voltage. The transconductance device is capable of utilizing the... Agent: Schwegman, Lundberg & Woessner / Atmel

20080192557 - System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080192558 - Semiconductor memory device and operating method thereof: A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.... Agent: Foley And Lardner LLP Suite 500

20080192559 - Bank interleaving compound commands: Embodiments of the invention are generally directed to systems, methods, and apparatuses for bank interleaving compound commands. In some embodiments, a memory device receives a command having interleaving hooks. The memory device may access at least two pages of memory in at least two different bank groups responsive, at least... Agent: Caven & Aghevli C/o Intellevate, Llc

20080192560 - Integrated circuit memory system with high speed non-volatile memory data transfer capability: An integrated circuit memory system includes an integrated circuit device having a random access memory array, a non-volatile memory array (e.g., flash memory array) and a data transfer circuit therein. The memory arrays and data transfer circuit may be included in a common integrated circuit chip. The random access memory... Agent: Myers Bigel Sibley & Sajovec

20080192561 - Dual-port sram device: A dual-port SRAM cell structure includes a first inverter area where a first inverter is constructed on a semiconductor substrate; a second inverter area where a second inverter is constructed on the semiconductor substrate, the first and second inverters being cross-coupled to form one or more data stage nodes for... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080192562 - Circuit and method for decoding column addresses in semiconductor memory apparatus: A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.... Agent: Baker & Mckenzie LLP Patent Department

20080192563 - Method and apparatus for controlling read latency of high-speed dram: Provided are a method and apparatus for controlling a read latency of a high-speed DRAM. A memory device may include a delay measurement unit, a delay locked loop, a latency counter and a data output buffer. The delay measurement unit measures a delay time between when an external clock signal... Agent: Harness, Dickey & Pierce, P.L.C

20080186752 - Memory cell with independent-gate controlled access devices and memory using the cell: A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the... Agent: Ryan, Mason & Lewis, LLP

20080186753 - High density one time programmable memory: A one time programmable memory cell for use in high-density memory devices is provided. The one time programmable memory cell includes a fuse device connected to a bit line and a select device and a select device connected to a row select line and to ground. The fuse device may... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080186754 - Ferroelectric semiconductor storage device: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080186755 - Memory cell device and programming methods: A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080186756 - Nanotube-based switching elements with multiple controls: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform... Agent: Wilmerhale/boston

20080186757 - Advanced mram design: Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080186758 - Magnetic memory device: A magnetic memory device includes a substrate, a magnetic tunneling junction (MTJ) structure disposed on the substrate, and a capping layer disposed on the MTJ structure. By adding a capping layer on the MTJ structure, the property of the magnetic memory device is improved, the magnetoresistance (MR) ratio is raised,... Agent: Apex Juris, PLLC

20080186759 - Magnetic random access memory and write method of the same: A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080186761 - Memory cell with separate read and program paths: A memory cell comprises a bit line, a read word line and a program word line, and a read device having a second read terminal connected to the read word line and a first read terminal. A program device has a second program terminal connected to the program word line... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080186762 - Phase-change memory element: A phase-change memory is provided. The phase-change memory comprises first and second electrodes, wherein the first and second electrodes comprise phase-change material. A conductive path is formed between the first and second electrodes and electrically connects the first and second electrodes, wherein the conductive path comprises an embedded metal layer... Agent: Birch Stewart Kolasch & Birch

20080186760 - Programmable fuse/non-volatile memory structures using externally heated phase change material: A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed... Agent: Cantor Colburn LLP-ibm Yorktown

20080186763 - Twin monos array for high speed application: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row... Agent: Saile Ackerman LLC

20080186766 - Non-volatile semiconductor memory device: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit... Agent: Hansen Huang Technology Law Group, LLP

20080186764 - Nor architecture memory and operation method thereof: An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080186765 - Semiconductor memory device: A semiconductor memory device according to one example includes a first cell transistor series including memory cell transistor connected in series, a first selecting transistor whose one terminal is connected to one terminal of the first cell transistor series, a second selecting transistor connected between the other terminal of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080186767 - Nonvolatile memory utilizing hot-carrier effect with data reversal function: A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the... Agent: Richard P. Berg C/o Ladas & Parry

20080186768 - Semiconductor memory device: A semiconductor memory device is capable of reading data at a high speed, without using a reference cell transistor. The semiconductor memory device includes a sensing unit including first cross-coupled MOS transistors to sense and amplify a voltage difference between a first node and a second node, and a unit... Agent: Morgan Lewis & Bockius LLP

20080186769 - Method for metal bit line arrangement: A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is... Agent: Rabin & Berdo, PC

20080186770 - Non-volatile memory device and method of compensating leakage reading current of a non-volatile memory array: A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080186771 - Nonvolatile semiconductor memory: In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080186772 - Non-volatile memory devices having floating-gates fets with different source-gate and drain-gate border lengths: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080186773 - One or multiple-times programmable device: Methods and apparatus, including computer program products, for a one or multiple-times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c Attn: Patent Intake Customer No. 64046

20080186774 - High-endurance memory device: A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080186776 - Source side asymmetrical precharge programming scheme: A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080186775 - Wordline voltage transfer apparatus, systems, and methods: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that... Agent: Schwegman, Lundberg & Woessner, P.A.

20080186777 - Relaxed metal pitch memory architectures: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied... Agent: Schwegman, Lundberg & Woessner, P.A.

20080186778 - Non-volatile memory embedded in a conventional logic process and methods for operating same: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20080186780 - Non-volatile memory with improved erasing operation: A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a... Agent: Akin Gump LLP - Silicon Valley

20080186779 - Semiconductor device and memory and method of operating thereof: A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the... Agent: J C Patents, Inc.

20080186781 - Semiconductor memory device: A semiconductor memory device includes: a phase comparison unit for comparing a phase of a clock signal with a phase of a reference clock signal; a delay line for delaying the clock signal in response to the comparison result of the phase comparison unit to output the delayed clock signal... Agent: Mcdermott Will & Emery LLP

20080186782 - Semiconductor memory devices having memory cell arrays with shortened bitlines: A semiconductor memory device includes a first memory cell array that comprises first memory cells arranged in a matrix of first rows and first columns; a second memory cell array that comprises second memory cells arranged in a matrix of second rows and second columns; a row decoder that is... Agent: Myers Bigel Sibley & Sajovec

20080186783 - Redundancy circuit semiconductor memory device: A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output... Agent: Townsend And Townsend And Crew, LLP

20080186785 - Semiconductor memory device for preventing supply of excess specific stress item and test method thereof: A semiconductor memory device includes a memory core which receives a specific stress item and a pattern item from an external source, a switch part which provides the power supplied from an external source and a switch control part which controls the switch part. The memory core responds to the... Agent: Mills & Onello LLP

20080186784 - Testing for sram memory data retention: A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced... Agent: Marger Johnson & Mccollom, P.C.

20080186786 - Fast and accurate sensing amplifier for low voltage semiconductor memory: A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080186787 - Storage device: A storage device includes: a ferroelectric memory that temporarily stores data, wherein the ferroelectric memory stores an error correction code that is used for verifying the data by correcting errors possibly occurring on the data stored; a storage medium that has a plurality of storage regions and continually stores the... Agent: Harness, Dickey & Pierce, P.L.C

20080186789 - Electric fuse circuit available as one time programable memory: A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.... Agent: Steptoe & Johnson LLP

20080186788 - Electrical fuse and associated methods: A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and the fuse link. According to other embodiments, a fuse link is connected between first and second contact regions.... Agent: Schwegman, Lundberg & Woessner / Infineon

20080186791 - Elastic power for read and write margins: An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of... Agent: Brooks Kushman P.C. / Sun / Stk

20080186792 - Semiconductor memory device having a short reset time: A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit... Agent: Mills & Onello LLP

20080186790 - Voltage down converter for high speed memory: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080186794 - Memory with tunable sleep diodes: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.... Agent: Texas Instruments Incorporated

20080186793 - Method and circuit for saving power: Portable devices are usually synchronized with servers like personal computers. Furthermore, most portable devices provide a user with the possibility to generate data objects or to obtain data objects from other sources than the personal computer. This means that of certain data objects a backup exists, as they are stored... Agent: Philips Intellectual Property & Standards

20080186795 - Elastic power for read margins: An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header... Agent: Brooks Kushman P.C. / Sun / Stk

20080186796 - Semiconductor memory device: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second... Agent: Sughrue Mion, PLLC

20080186797 - Circuit for use in a multiple block memory: A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal.... Agent: Freescale Semiconductor, Inc. Law Department

20080186798 - Semiconductor package: A semiconductor package facilitates package connection due to different locations of input/output pads in each interlayer die depending on coding information in a multi-chip package. The semiconductor package includes many chips. Each of the chips includes: input/output pads configured to input and output data having a given bandwidth; a decoding... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP