Static information storage and retrieval inventions 07/08

20080180980 - Memory device with an asymmetric layout structure: An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080180981 - Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof: A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly,... Agent: F. Chau & Associates, LLC

20080180982 - Stacked 1t-nmemory cell structure: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics... Agent: Dickstein Shapiro LLP

20080180983 - Semiconductor device with a plurality of different one time programmable elements: A semiconductor device and method with a plurality of different one time programmable elements. One embodiment provides a semiconductor device having a plurality of different one time programmable elements that form a group of one time programmable elements, wherein at least one bit of information is jointly stored by the... Agent: Dicke, Billig & Czaja

20080180985 - Ferroelectric media structure for ferroelectric hard disc drive and method of fabricating the same: A recording medium structure for a ferroelectric hard disc drive (HDD) and a method of fabricating the same are provided. A ferroelectric medium is deposited on a glass substrate so as to form a film with a uniform roughness, thereby improving data recording density and reducing the manufacturing costs of... Agent: Sughrue Mion, PLLC

20080180984 - Semiconductor memory device: Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080180986 - Semiconductor device and method for manufacturing the same: A first DRAM section including a first memory cell having a first capacitance and a second DRAM section including a second memory cell having a second capacitance different from the first capacitance are provided on the same semiconductor substrate.... Agent: Mcdermott Will & Emery LLP

20080180987 - Multi-state latches from n-state reversible inverters: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use... Agent: Diehl Servilla LLC

20080180988 - Direct writing method of magnetic memory cell and magetic memory cell structure: A direct writing method of a magnetic memory cell is provided. The magnetic memory cell includes a magnetic free stacked layer having a bottom and a top ferromagnetic layer. The bottom and top ferromagnetic layers respectively have a bi-directional easy axis in substantially the same direction. The method includes applying... Agent: Jianq Chyun Intellectual Property Office

20080180989 - Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second... Agent: Myers Bigel Sibley & Sajovec

20080180990 - Method to tighten set distribution for pcram: A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes applying an increasing first voltage across the memory cell and monitoring current in the memory cell to detect a beginning of a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080180991 - Current-confined effect of magnetic nano-current-channel (ncc) for magnetic random access memory (mram): One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC... Agent: Law Offices Of Imam

20080180992 - Storage element and memory: A storage element includes a storage layer for holding information depending on a magnetization state of a magnetic material; and a magnetization fixed layer in which magnetization direction is fixed, that is arranged relative to the storage layer through a nonmagnetic layer. The magnetization direction of the storage layer is... Agent: Bell, Boyd & Lloyd, LLP

20080180993 - Intergrated circuit with magnetic memory: An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080180994 - Memory system, semiconductor memory device and method of driving same: A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080180995 - Semiconductor device with electrically floating body: A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the... Agent: Courtney Staniford & Gregory LLP

20080180996 - Flash memory with improved programming precision: A memory includes a plurality of flash cells and circuitry for programming a first cell to store first data and one or more second cells to store second data. Either the circuitry itself, or a controller of he memory, or a host of the memory by executing driver code, causes... Agent: Mark M. Friedman

20080180998 - Method of reading nand memory to compensate for coupling between storage elements: A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent the word line written after word line; and... Agent: Vierra Magen/sandisk Corporation

20080181001 - Memory device with negative thresholds: A method for data storage in a memory that includes a plurality of analog memory cells includes storing data in the memory by writing first storage values to the cells. One or more read reference levels are defined for reading the cells, such that at least one of the read... Agent: Darby & Darby P.C.

20080181000 - Method of improving programming precision in flash memory: Data are stored in cells of a flash memory by assigning a first portion of the data to be stored in a first cell and a second portion of the data to be stored in one or more second cells. The first cell is programmed to store the first portion... Agent: Mark M. Friedman

20080181002 - Charge loss restoration method and semiconductor memory device: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read... Agent: Arent Fox LLP

20080181003 - Increased nand flash memory read throughput: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data... Agent: Schwegman, Lundberg & Woessner, P.A.

20080181004 - Memory system and data reading and generating method: An object of the present invention is to provide a memory system that offers enhanced security of ROM code that is data whose contents can be utilized for a given purpose in its intact form. In a memory system, data is read from a memory according to at least two... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181005 - Semiconductor storage device having page copying function: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to... Agent: Frommer Lawrence & Haug

20080181006 - Method of programming memory cell: A method of programming a memory cell is described. First, a first programming operation is performed to inject electrons into a nitride layer adjacent to a side of a drain. The first programming operation includes applying a first gate voltage to a gate, applying a first drain voltage to the... Agent: J C Patents, Inc.

20080181008 - Flash memory system capable of improving access performance and access method thereof: A flash memory system capable of improving an access performance and an access method thereof. The system includes: a flash memory device including a plurality of storage regions; a contents memory storing setting information corresponding to the plurality of storage regions, respectively; and a processing unit setting operation conditions of... Agent: F. Chau & Associates, LLC

20080181007 - Semiconductor device with reduced structural pitch and method of making the same: A method of manufacturing structures in a workpiece includes: providing a portion of a cover layer on a predetermined section of the workpiece, providing a resist layer over the workpiece and the cover layer, and patterning resist structures in the resist layer. The workpiece is patterned using the patterned resist... Agent: Edell, Shapiro & Finnan, LLC

20080181009 - Semiconductor memory device and write method thereof: A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181010 - Flash memory and method for determining logic states thereof: A method for determing the logic state of a memory cell of an array is provided. The array includes many word lines and bit lines. The method proceeds with the following steps. Firstly, a first voltage varing according to a sensing parasitic resistance of the memory cell is applied to... Agent: Rabin & Berdo, PC

20080181011 - Flash memory device capable of reduced programming time: A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls the word line voltage generator circuit so... Agent: Volentine & Whitt PLLC

20080180997 - High voltage regulator for non-volatile memory device: A high voltage regulator may include a first regulating unit, a second regulating unit, and an output node. The first regulating unit regulates the program voltage in a voltage-level-up interval of a program voltage of a memory cell. The second regulating unit regulates the program voltage in a voltage-level-down interval... Agent: Lee & Morse, P.C.

20080180999 - Method, system and circuit for operating a non-volatile memory array: As part of the present invention, a memory cell may be operated using reference cells having a threshold offset circuit. According to some embodiments of the present invention, a threshold offset value may be determined for a memory cell to be operated based on a location (e.g. memory segment within... Agent: Empk & Shiloh, LLP

20080181012 - Memory device with adaptive sense unit and method of reading a cell array: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including... Agent: Edell, Shapiro & Finnan, LLC

20080181013 - Method for reading a memory array with a non-volatile memory structure: A method for reading a memory array is disclosed. The method includes turning on the column of select gates; preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a... Agent: North America Intellectual Property Corporation

20080181015 - Memory systems and memory cards that use a bad block due to a programming failure therein in single level cell mode and methods of operating the same: A memory system includes a host, a flash memory that is configured to store multi-bit data in one memory cell, and a memory controller that is configured to control programming of multi-bit data provided by the host into the flash memory. When an nth bit is normally programmed, and a... Agent: Myers Bigel Sibley & Sajovec

20080181014 - Programming a non-volatile memory device: A non-volatile memory device that has a cache register coupled between each pair of bit lines and, in one embodiment, a data cache coupled between each pair of bit lines. The cache register toggles a bit when a memory cell on one of the bit lines to which it is... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20080181018 - Memory system and control method thereof: A memory system includes: a flash memory that stores data; a memory that stores a read count table that indicates the number of times of data read from the flash memory; and a controller that performs: reading out the data from the flash memory; updating the read count table when... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181019 - Semiconductor memory device capable of setting a negative threshold voltage: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181016 - Semiconductor memory device with mos transistors each having floating gate and control gate and method of controlling the same: A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix and a second cell array including... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181017 - Semiconductor memory device with refresh trigger: A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, an X decoder designating a position of an X axis of the memory cell, a Y decoder designating a position of a Y axis crossing the X axis, a controller collectively controlling operations of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181020 - Erase operation control sequencing apparatus, systems, and methods: The apparatus, systems, and methods described herein may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after... Agent: Schwegman, Lundberg & Woessner, P.A.

20080181021 - Memory module and method employing a multiplexer to replace a memory device: A memory module including memory devices, a spare memory device, a multiplexing unit, and a memory buffer is provided. The multiplexing unit is coupled with each of the memory devices and the spare memory device, while the memory buffer is coupled with the multiplexing unit. The memory buffer includes a... Agent: Hewlett Packard Company

20080181022 - Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same: A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080181023 - Semiconductor memory device: A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask... Agent: Arent Fox LLP

20080181024 - Low voltage sensing scheme having reduced active power down standby current: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping... Agent: Jones Day

20080181025 - Word line driver circuitry and methods for using the same: Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time... Agent: Ropes & Gray LLP

20080181028 - Data flow scheme for low power dram: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required... Agent: Saile Ackerman LLC

20080181027 - Memory device, memory controller and memory system: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of... Agent: Arent Fox LLP

20080181026 - Semiconductor memory device: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS... Agent: Miles & Stockbridge PC

20080181029 - Techniques for improving write stability of memory with decoupled read and write bit lines: In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line... Agent: Ryan, Mason & Lewis, LLP

20080181030 - Memory system, memory device and command protocol: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a... Agent: Volentine & Whitt PLLC

20080181031 - Data strobe synchronization circuit and method for double data rate, multi-bit writes: A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data... Agent: Karen Lenaburg, Esq. Dorsey & Whitney LLP

20080181033 - Pulse width control for read and write assist for sram circuits: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.... Agent: Texas Instruments Incorporated

20080181032 - Read operation control sequencing apparatus, systems, and methods: Apparatus, systems, and methods described herein may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in... Agent: Schwegman, Lundberg & Woessner, P.A.

20080181034 - Memory system with redundant ram memory cells having a different designed cell circuit topology: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array.... Agent: Freescale Semiconductor, Inc. Law Department

20080181035 - Method and system for a dynamically repairable memory: Systems and methods for a memory system capable of detection and repair of failures occurring during operation are disclosed. Embodiments of the present invention provide a memory system operable to detect an error at a memory cell of a memory and replace the failed memory cell. More specifically, in certain... Agent: SprinkleIPLaw Group

20080181036 - Method of testing semiconductor apparatus: A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080181037 - Multi-port semiconductor memory device: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080181038 - Reduced power bitline precharge scheme for low power applications in memory devices: A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power... Agent: Texas Instruments Incorporated

20080181039 - Integrated semiconductor memory and method for operating a data path in a semiconductor memory: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair... Agent: Eschweiler & Associates LLC

20080181040 - N-port memory circuits allowing m memory addresses to be accessed concurrently and signal processing methods thereof: Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a higher-order multi-port memory can be replaced by a lower-order multi-port or single-port memory. Consequently, smaller... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080181041 - Semiconductor memory device and refresh control method: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by... Agent: Scully Scott Murphy & Presser, PC

20080181043 - Configurable device id in non-volatile memory: Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, such as but not limited to the memory chip factory,... Agent: Intel Corporation C/o Intellevate, LLC

20080181042 - Method and system for efficiently organizing data in memory: A method and system for efficiently organizing data in memory is provided. Exemplary aspects of the invention may include storing linear data and block data in more than one DRAM device and accessing the data with one read/write access cycle. Common control signals may be used to control the DRAM... Agent: Mcandrews Held & Malloy, Ltd

20080181044 - Bus structure, memory chip and integrated circuit: A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising... Agent: Slater & Matsil LLP

20080181045 - Calibration circuit of a semiconductor memory device and method of operating the same: A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compares output signals of a data latch that... Agent: Lowe Hauptman Ham & Berner, LLP

20080181046 - Clock circuitry for ddr-sdram memory controller: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information,... Agent: Schwegman, Lundberg & Woessner / Atmel

20080181047 - Semiconductor device: A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to... Agent: Mcdermott Will & Emery LLP

20080181048 - Semiconductor memory device and memory cell accessing method thereof: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number... Agent: Lee & Morse, P.C.

20080175030 - Stored don't-care based hierarchical search-line scheme: In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory cell. Data are stored in the blocks in order according to the length of the prefix. Data... Agent: Sinorica, Llc

20080175031 - Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods: A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The... Agent: Volentine & Whitt Pllc

20080175032 - Semiconductor memory and method for manufacturing the same: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode connected serially to the resistance change element; and a source conductive layer spreading two-dimensionally to be connected to one ends... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080175034 - Ferroelectric memory and operating method of same: A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data... Agent: Arent Fox LLP

20080175033 - Method and system for improving domain stability in a ferroelectric media: A method of recording information on a media including a ferroelectric recording layer comprises writing the information by forming one or more domains within the ferroelectric recording layer, the one or more domains having a spontaneous polarization, and arranging the one or more domains in a pattern that improves a... Agent: Fliesler Meyer LLP

20080175035 - Non-volatile resistance changing for advanced memory applications: A resistance changing memory unit cell includes a resistance changing memory element coupled to a sense bit line and a diode coupled to the resistance changing memory element.... Agent: Eschweiler & Associates, Llc National City Bank Building

20080175036 - Resistance random access memory having common source line: A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite... Agent: Volentine & Whitt Pllc

20080175037 - Method and apparatus for high-efficiency operation of a dynamic random access memory: The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit... Agent: Duane Morris LLP

20080175038 - Semiconductor memory device: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of... Agent: Mcdermott Will & Emery LLP

20080175039 - Memory cell provided with dual-gate transistors, with independent asymmetric gates: at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F),... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080175040 - Semiconductor memory device: A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the first and second memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080175041 - Magnetic memory device, method for writing into magnetic memory device and method for reading magnetic memory device: A magnetic memory device comprises a first signal line (BL) and a second signal line (/BL) extended column-wise; a third signal line (WL) extended row-wise; a memory cell including a first parallelly connected set which is disposed at the intersection of the first signal line and the third signal line,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080175042 - Phase change layer and method of manufacturing the same and phase change memory device comprising phase change layer and methods of manufacturing and operating phase change memory device: Provided are a phase change layer and a method of forming the phase change layer and a phase change memory device including the phase change layer, and methods of manufacturing and operating the phase change memory device. The phase change layer may be formed of a quaternary compound including an... Agent: Harness, Dickey & Pierce, P.L.C

20080175044 - Magnetic memory cell and magnetic memory device: The present invention aims to reduce heat fluctuations of a memory cell and thereby provide a stable writing operation when a magnetization reversal process not involving a reversal magnetic field is used for writing into the memory cell. The magnetic memory cell has a structure where first and second magnetization... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080175043 - Method and apparatus for initializing reference cells of a toggle switched mram device: A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the... Agent: Cantor Colburn LLP-ibm Burlington

20080175045 - Depletion-mode mosfet circuit and applications: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS)... Agent: Synnestvedt Lechner & Woodbridge LLP

20080175048 - Memory cell programming method and semiconductor memory device: A memory cell programming method and related semiconductor memory device are disclosed. The method involves receiving and latching first through nth bits of write data in a corresponding plurality of first through nth latches, and programming a kth bit of write data in the memory cell, where k ranges from... Agent: Volentine & Whitt Pllc

20080175046 - Method of operating multi-level cell and integrate circuit for using multi-level cell to store data: A method of operating a multi-level cell is provided. The method includes the following the steps. (a) The multi-level cell is operated until a threshold voltage is larger than a pre-programming threshold voltage. And (b) the multi-level cell is operated until the threshold voltage is larger than a target programming... Agent: J C Patents, Inc.

20080175047 - Nonvolatile semiconductor memory device and programming method thereof: A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage... Agent: F. Chau & Associates, Llc

20080175049 - Non-volatile memory array: A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged... Agent: J C Patents, Inc.

20080175052 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write... Agent: Hogan & Hartson L.l.p.

20080175050 - Pfet nonvolatile memory: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which... Agent: Merchant & Gould P.c.

20080175051 - Semiconductor memory: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating... Agent: Buchanan, Ingersoll & Rooney Pc

20080175053 - Silicon on insulator and thin film transistor bandgap engineered split gate memory: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080175054 - Methods and systems for memory devices: One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a... Agent: Eschweiler & Associates, Llc National City Bank Building

20080175056 - Flash memory device and writing method thereof: A flash memory device includes a memory cell array including a plurality of memory cells. A data writing buffer temporarily stores data to be written into the memory cells. A control circuit controls a write operation of the memory cells. A decoder decodes write address of the memory cell in... Agent: F. Chau & Associates, Llc

20080175055 - Non-volatile memory device and self-compensation method thereof: A non-volatile memory device includes a memory cell array at least one block having a plurality of memory cells, and at least one reference cell with respect to each block, an X decoder and a Y decoder for selecting a memory cell for an operation according to an input address,... Agent: Townsend And Townsend And Crew, LLP

20080175058 - Non-volatile memory system and data read method of non-volatile memory system: In one aspect, a non-volatile memory system includes a plurality of memory cell arrays having different read stand-by times. For example, the non-volatile memory system may include a single-level cell (SLC) array composed of a plurality of SLCs, and a multi-level cell (MLC) array composed of a plurality of MLCs.... Agent: Volentine & Whitt Pllc

20080175057 - Non-volatile semiconductor memory: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080175059 - Flash memory device and method of operating the same: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the... Agent: Townsend And Townsend And Crew, LLP

20080175061 - Non-volatile memory devices and methods of operating the same: Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate... Agent: Harness, Dickey & Pierce, P.L.C

20080175060 - Non-volatile semiconductor memory based on enhanced gate oxide breakdown: A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell... Agent: Perkins Coie LLP Patent-sea

20080175062 - Integrated flash memory systems and methods for load compensation: Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage.... Agent: Dla Piper Us LLP

20080175065 - Method and apparatus for storing page data: A method of operating a non-volatile memory can include backing-up first data successfully programmed to a first target page of a non-volatile memory to provide local back-up data. A determination can be made that programming of second data to the first target page has failed and the local back-up data... Agent: Myers Bigel Sibley & Sajovec

20080175064 - Method of programming data in a flash memory device: A method of programming a most significant bit (MSB) data to a multi-level cell in a flash memory device including first and second cells includes performing a first program operation on the first cell using a first program voltage, the first cell being in a first state when the first... Agent: Townsend And Townsend And Crew, LLP

20080175063 - Nand flash memory device and method of improving characteristic of a cell in the same: A non-volatile memory device includes a memory cell array, a page buffer, a cell characteristic detecting circuit, an X decoder and a Y decoder. The memory cell array has memory cells coupled to bit lines and word lines. The page buffer programs data to a selected memory cell or read... Agent: Townsend And Townsend And Crew, LLP

20080175066 - Semiconductor device: The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are... Agent: Miles & Stockbridge Pc

20080175067 - Semiconductor memory device: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080175068 - Temperature dependent back-bias for a memory array: The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller also includes a voltage control circuit coupled to the temperature sensing circuit and... Agent: Texas Instruments Incorporated

20080175069 - Method of performing an erase operation in a non-volatile memory device: An erase method having a memory cell array which includes at least one blocks having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having highest level by pre-programming every cell in a block selected for erase, performing an erase operation on... Agent: Townsend And Townsend And Crew, LLP

20080175070 - Early read after write operation memory device, system and method: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory... Agent: Deniro/rambus

20080175071 - Methods of operating memory systems including memory devices set to different operating modes: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080175072 - Fast data access through page manipulation: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and,... Agent: Unity Semiconductor Corporation

20080175073 - Sense amplifiers and semiconductor memory devices for reducing power consumption and methods for operating the same: In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected current difference between a pair of input/output lines. A voltage amplifier generates a third and a... Agent: Harness, Dickey & Pierce, P.L.C

20080175076 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are... Agent: Dickinson Wright Pllc

20080175075 - Sense amplifier for non-volatile memories: A sense amplifier for reading a memory cell, comprising: a read node linked to the memory cell, an active stage connected to the read node and comprising means for supplying a read current on the read node, and a data output linked to a node of the active stage where... Agent: Seed Intellectual Property Law Group Pllc

20080175074 - Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values: A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the... Agent: Hogan & Hartson LLP

20080175077 - Novel write vccmin improvement scheme: A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled between the CVDD line and a complementary low... Agent: Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080175078 - Method and apparatus for synchronizing data from memory arrays: According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps.... Agent: Jones Day

20080175079 - Test scheme for fuse circuit: Provided is an apparatus and a method for testing an electrical fuse. In accordance therewith: a first test is performed on a plurality of memory cells arranged with a plurality of rows and a plurality of columns; a line related to a defective cell is repaired with a redundant line... Agent: Mills & Onello LLP

20080175080 - Semiconductor memory device and test method thereof: Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner... Agent: Mills & Onello LLP

20080175081 - Semiconductor memory device and operation control method thereof: A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system,... Agent: Harness, Dickey & Pierce, P.L.C

20080175082 - Serial power capacitor device: A serial power capacitor device is provided which includes a noise suppressing circuit which includes a plurality of capacitive elements for suppressing a power noise, and a stabilizing circuit which stabilizes an operation of the noise suppressing circuit by compensating for variations in leakage current of the capacitive elements. The... Agent: Volentine & Whitt Pllc

20080175083 - Memory cell access circuit: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors.... Agent: Ibm Microelectronics Intellectual Property Law

20080175084 - Semiconductor memory device and sense amplifier circuit: A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor... Agent: Miles & Stockbridge Pc

20080175085 - Differential and hierarchical sensing for memory circuits: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal... Agent: Ryan, Mason & Lewis, LLP

20080175086 - Multi-port dynamic memory structures: A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at... Agent: Ryan, Mason & Lewis, LLP Suite 205

20080175087 - Circuit for generating a reference voltage: A circuit for generating a reference voltage in a memory device includes a switching section, a first voltage generator, a second voltage generator and a comparator. The switching section controls a supply of a power supply voltage in response to a control signal. The first voltage generator generates a reference... Agent: Townsend And Townsend And Crew, LLP

20080175088 - Power voltage supplier of semiconductor memory device: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying... Agent: Mcdermott Will & Emery LLP

20080175089 - Flash memory card: A flash memory card including a main memory core, a removable supplementary memory core, and a controller operating to control the main and supplementary memory cores. The supplementary memory core includes a plurality of memory cores and is replaceable.... Agent: F. Chau & Associates, Llc

20080175090 - Memory device and method having programmable address configurations: A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080175091 - Synchronous memory circuit: A semiconductor integrated circuit device including a memory circuit with both high access efficiency and high memory efficiency in a simple configuration is provided. In a memory read control circuit, burst length is changed based on whether or not a read instruction is issued at a cycle after a cycle... Agent: Miles & Stockbridge Pc

20080170425 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: Zilka-kotab, PC- Mrm1

20080170424 - Semiconductor memory device capable of realizing a chip with high operation reliability and high yield: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080170426 - Novel rom cell array structure: A semiconductor memory cell array is disclosed which comprises an elongated continuous active region, a first transistor formed in the elongated continuous active region, the first transistor forming a first single-transistor memory cell, a second transistor also formed in the elongated continuous active region, the second transistor forming a second... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080170428 - Nonvolatile semiconductor memory device and method of writing into the same: The semiconductor memory device includes a resistance memory element 46 including a common electrode 38, a resistance memory layer 42 which is formed on the common electrode 38 and is switched between a high resistance state and a low resistance state by an application of a voltage, and a plurality... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080170427 - Resistive random access memory devices and methods of manufacturing the same: Example embodiments may provide resistive random access memory devices and/or methods of manufacturing resistive random access memory devices. Example embodiment resistive random access memory devices may include a switching device and/or a storage node connected to the switching device. The storage node may include a stack structure including a plurality... Agent: Harness, Dickey & Pierce, P.L.C

20080170429 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is... Agent: Wilmerhale/boston

20080170430 - Cmos sram/rom unified bit cell: A memory cell including a bit and bitnot sense lines as well as a random access memory (RAM) word line and a read only memory (ROM) word line. The memory cell particularly includes a static RAM (SRAM) bit cell and a ROM bit cell. The SRAM bit cell is coupled... Agent: Henneman & Associates, PLC

20080170431 - Driving method and system for a phase change memory: An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large... Agent: Quintero Law Office, PC

20080170432 - Magnetic random access memory and write method of the same: A magnetic random access memory includes a memory cell element which includes a first fixed layer, a first recording layer in which a magnetization direction reverses on the basis of a first threshold value, and a first nonmagnetic layer formed between the first fixed layer and the first recording layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080170434 - Memory cell programming methods capable of reducing coupling effects: In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used... Agent: Harness, Dickey & Pierce, P.L.C

20080170435 - Semiconductor storage device: A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080170433 - Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same: A word line driver system is described that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080170436 - Flash memory device with write protection: A flash memory device and a related method of write protecting data are disclosed. The flash memory device includes a protection controller having a latch circuit storing temporary protected/accessible data, a cell array storing persistent protected/accessible data, a write controller altering the persistent protected/accessible data, and a latch controller altering... Agent: Volentine & Whitt PLLC

20080170437 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent: Frommer Lawrence & Haug

20080170440 - Flash memory device with split string selection line structure: A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and... Agent: Volentine & Whitt PLLC

20080170439 - Multi-level memory: A storage system comprises a charge storage cell and a controller. The charge storage cell includes first and second charge storage regions, each capable of assuming a plurality of charge levels. The controller programs the first charge storage region to one of the plurality of charge levels and then programs... Agent: Harness, Dickey & Pierce P.L.C

20080170438 - Nand memory with virtual channel: A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma... Agent: Vierra Magen/sandisk Corporation

20080170442 - Column leakage compensation in a sensing circuit: A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a... Agent: Sawyer Law Group LLP

20080170441 - Sense architecture: A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier,... Agent: Sawyer Law Group LLP

20080170443 - Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a... Agent: Lee & Morse, P.C.

20080170444 - Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell: An integrated circuit comprises a resistive memory cell, at least one reference cell, a first device configured to apply a predetermined read voltage to the resistive memory cell and a second device configured to apply the predetermined read voltage to the reference cell. The resistive memory cell can be switched... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080170447 - Storing information in a memory: Systems and methods, including computer software products, can be used to update or modify data stored in a memory. One or more variables are represented with one or more cell values in a memory. Each variable is associated with one or more of the cell values. Multiple states of the... Agent: Fish & Richardson P.C.

20080170445 - Semiconductor memory having function to determine semiconductor low current: A semiconductor memory, including a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections between the plurality of word lines and the plurality of bit lines, and a sense amplifier for reading out what is stored in the memory cells, the semiconductor... Agent: Mcdermott Will & Emery LLP

20080170446 - High voltage generating circuit and semiconductor memory device having the same and method thereof: A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to... Agent: Harness, Dickey & Pierce, P.L.C

20080170448 - structure for redundancy programming of a memory device: A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuit means for implementing a method wherein it is assumed that all fails are row fails until determined to... Agent: Schmeiser, Olsen & Watts

20080170449 - Method and apparatus for implementing efuse sense amplifier testing without blowing the efuse: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080170451 - Method and circuit for setting test mode of semiconductor memory device: A test mode setting method and circuit that reduce the number of signal lines, thereby minimizing the number of wires of a semiconductor memory device. The method includes: sequentially activating a plurality of selection signals; when each selection signal is activated, activating one of a plurality of test mode addresses... Agent: F. Chau & Associates, LLC

20080170450 - Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit: In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.... Agent: Volentine & Whitt PLLC

20080170452 - Data output circuit in semiconductor memory device: A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data.... Agent: Law Office Of Monica H Choi

20080170453 - Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power... Agent: Dickstein Shapiro LLP

20080170454 - Sense amplifier with stages to reduce capacitance mismatch in current mirror load: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell... Agent: Sawyer Law Group LLP

20080170455 - Compensated current offset in a sensing circuit: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit... Agent: Lorenzo Bedarida

20080170456 - Memory refresh method and system: A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory rank, and an idle auto-refresh number of the memory rank is calculated if there is no access request... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080170457 - Method for sensing a signal in an integrated circuit complementary fuse arrangement: A method for sensing an electrical signal includes the steps of: providing an arrangement having a fuse connected in series to an antifuse, the arrangement further having an output tap connected to an intermediate node located between the fuse and the antifuse; programming the fuse and the antifuse; applying a... Agent: International Business Machines Corporation Dept. 18g

20080170458 - Apparatus and method for reducing leakage currents of integrated circuits having at least one transistor: An apparatus for reducing leakage currents of an integrated circuit having at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, the apparatus including a controller for controlling the first reference potential in dependence on the supply potential.... Agent: Dickstein Shapiro LLP

20080170459 - Memory macro: In a memory macro which can more largely reduce a leak current of a memory cell in a hold state, a power voltage between a power potential and a reference potential is supplied across power terminals of each CMOS inverter (across source electrodes of loading P channel FETs and source... Agent: Arent Fox LLP

20080170460 - Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The... Agent: Stanzione & Kim, LLP

20080170461 - Semiconductor memory apparatus, semiconductor integrated circuit having the same, and method of outputting data in semiconductor memory apparatus: A semiconductor memory apparatus includes a rising output data generator that generates rising output data from rising data in response to a rising clock and a rising output enable signal. A rising data output buffer buffers the rising output data. A falling output data generator generates falling output data from... Agent: Venable LLP

20080165557 - Method and system for providing a nonvolatile content addressable memory using a single flotox element: A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes... Agent: Benoit Godard

20080165559 - Data line layout and line driving method in semiconductor memory device: A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number... Agent: Mills & Onello LLP

20080165558 - Semiconductor memory device: A semiconductor memory device has memory cells each of which has a MIS type of transistor capable of setting one of two kinds of threshold potentials, reference cells used for determining data stored in the memory cells, which have the same size, shape and electrical properties as those of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080165562 - Fast, stable, sram cell using seven devices and hierarchical bit/sense line: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this... Agent: Cantor Colburn LLP-ibm Yorktown

20080165560 - Hierarchical 2t-dram with self-timed sensing: An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected... Agent: Cantor Colburn LLP-ibm Yorktown

20080165561 - Hierarchical six-transistor sram: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell... Agent: Cantor Colburn LLP-ibm Yorktown

20080165563 - Semiconductor memory device: In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying... Agent: Young & Thompson

20080165564 - Non-volatile semiconductor storage device: A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data from the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080165565 - Ferroelectric thin films and devices comprising thin ferroelectric films: A method of producing a device with a ferroelectric crystal thin film on a first substrate including the steps of providing a ferroelectric crystal, of irradiating a first surface of the ferroelectric crystal with ions so that a damaged layer is created underneath the first surface, of bonding a block... Agent: Rankin, Hill & Clark LLP

20080165566 - Non-volatile memory including sub cell array and method of writing data thereto: A non-volatile memory device, in which data values are determined by polarities at cell terminals, includes a memory cell array. The memory cell array is divided into multiple sub cell arrays, each sub cell array including at least one input/output line and an X-decoder/driver. First input/output lines included in different... Agent: Volentine & Whitt PLLC

20080165567 - Semiconductor memory device: There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active... Agent: Volentine & Whitt PLLC

20080165568 - Probes and media for high density data storage: A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact probes in accordance with the present invention can be applied... Agent: Fliesler Meyer LLP

20080165570 - Current compliant sensing architecture for multilevel phase change memory: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080165575 - Memory cell array biasing method and a semiconductor memory device: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first... Agent: F. Chau & Associates, LLC

20080165574 - Memory device including thermal conductor located between progammable volumes: In one aspect, a memory device is provided which includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction, an array of programmable volumes electrically connected between the bit lines and word lines, and thermally conductive striped patterns located... Agent: Volentine & Whitt PLLC

20080165573 - Memory including two access devices per phase change element: A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the... Agent: Dicke, Billig & Czaja

20080165571 - Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell: A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing a first process to program input data, including setting up bias voltages on bit lines and word lines on the memory cells, determining if the input data for... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080165572 - Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell: A method, system and computer program product for resetting a phase change memory cell having a memory cell threshold voltage is disclosed. The method includes reading a resistance of the memory cell. If the resistance is larger than a chosen resistance, the resetting of the memory cell ends. Otherwise, the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080165569 - Resistance limited phase change memory material: A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative... Agent: Michael L. Wise Ryan, Mason & Lewis, LLP

20080165576 - Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same: A memory storage device that contains alternating first and second ferromagnetic material layers is provided. Each first ferromagnetic material layer has a first layer thickness (L1) and a first critical current density (JC1), and each second ferromagnetic material layer has a second layer thickness (L2) and a second critical current... Agent: Scully, Scott, Murphy & Presser, P.C.

20080165577 - Semiconductor device: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for... Agent: Neil Steinberg

20080165580 - 3-level non-volatile semiconductor memory device and method of driving the same: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch... Agent: Marger Johnson & Mccollom, P.C.

20080165578 - Method of operating multi-level cell: A method of operating a multi-level cell is described, wherein the cell includes a substrate of a first conductivity type, a control gate, a charge-storing layer and two S/D regions of a second conductivity type. The method includes an erasing step that injects charges of a first type into the... Agent: J C Patents, Inc.

20080165579 - Programming method of multi-bit flash memory device for reducing programming error: A method of programming a plurality of memory cells of a flash memory device by selectively changing a threshold voltage distribution thereof from a first distribution to a second distribution, the method includes selecting at least one of the memory cells to be programmed, and programming the at least one... Agent: Lee & Morse, P.C.

20080165581 - Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control: A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080165582 - Scalable electrically eraseable and programmable memory: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080165583 - Non-volatile storage element: The invention relates to a non-volatile storage element comprising date connections (I1/O1, I2/O2) and two MOS transistors (60,70) of a first conductivity type, the source connections of the transistors being connected to a second supply voltage connection (10). A drain connection of the MOS transistor (60) is connected to the... Agent: Fish & Richardson PC

20080165584 - Flash memory array architecture: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading,... Agent: Akin Gump LLP - Silicon Valley

20080165585 - Erase verify method for nand-type flash memories: An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the... Agent: Lewis And Roca, LLP

20080165586 - Semiconductor device: A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080165587 - Operating method of p-channel non-volatile memory: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a... Agent: Jianq Chyun Intellectual Property Office

20080165588 - Reset method of non-volatile memory: A reset method of a non-volatile memory is described. The non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two... Agent: J C Patents, Inc.

20080165589 - Method and system for a serial peripheral interface: A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method... Agent: Townsend And Townsend And Crew, LLP

20080165590 - Dynamic module output device and method thereof: A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway... Agent: Larson Newman Abel Polansky & White, LLP

20080165591 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation... Agent: Mcdermott Will & Emery LLP

20080165593 - Semiconductor memory device and over driving method thereof: A semiconductor memory device may include a power line, an over driver, and/or an internal voltage driver. The power line may be connected to at least one sense amplifier. The at least one sense amplifier may be connected to a memory cell included in a memory block. The memory block... Agent: Harness, Dickey & Pierce, P.L.C

20080165592 - Semiconductor memory device, sense amplifier circuit and memory cell reading method: A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.... Agent: Rader Fishman & Grauer PLLC

20080165594 - Semiconductor memory device and driving method thereof: A semiconductor memory device is capable of reducing the current dissipation in a termination circuit and allowing a voltage level of a GIO line to rapidly reach a voltage level of a termination voltage when a termination operation is performed. The semiconductor memory device includes a global input/output line configured... Agent: Blakely Sokoloff Taylor & Zafman

20080165595 - Maximum likelihood statistical method of operations for multi-bit semiconductor memory: An operating procedure to provide a cost effective method to maximize the number of levels with respect to a characteristic parameter of a memory cell. The procedures utilize statistical analysis to determine the most likely binary value associated with the characteristic parameter value. In one embodiment, a receiving unit reads... Agent: Law Office Of Ido Tuchman (yor)

20080165596 - Semiconductor memory device and method thereof: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating... Agent: Harness, Dickey & Pierce, P.L.C

20080165597 - Semiconductor memory device with debounced write control signal: A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a... Agent: Rabin & Berdo, PC

20080165598 - Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto: A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a... Agent: Volentine & Whitt PLLC

20080165599 - Design structure used for repairing embedded memory in an integrated circuit: A design structure for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with... Agent: Ibm Microelectronics Intellectual Property Law

20080165600 - Repairing advanced-memory buffer (amb) with redundant memory buffer for repairing dram on a fully-buffered memory-module: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access... Agent: Stuart T Auvinen

20080165601 - Edram hierarchical differential sense amp: In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of... Agent: Cantor Colburn LLP-ibm Yorktown

20080165602 - Processor instruction cache with dual-read modes: A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the... Agent: Harness, Dickey & Pierce P.L.C

20080165603 - Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof: A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns,... Agent: F. Chau & Associates, LLC

20080165604 - Holographic storage medium, and method and apparatus for recording/reproducing data on/from the holographic storage medium: A holographic storage medium, and a method and an apparatus for recording/reproducing data on/from the holographic storage medium. The method including: dividing a datapage into a plurality of regions; modulating the data into codewords having different on-pixel rates; and arranging the codewords in the plurality of regions, based on the... Agent: Stein, Mcewen & Bui, LLP

20080165605 - Method and apparatus for variable memory cell refresh: The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or... Agent: Courtney Staniford & Gregory LLP

20080165606 - Semiconductor memory device for reducing peak current during refresh operation: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a... Agent: Blakely Sokoloff Taylor & Zafman

20080165607 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL... Agent: Blakely Sokoloff Taylor & Zafman

20080165608 - Power control circuit for semiconductor ic: A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a... Agent: Volentine & Whitt PLLC

20080165609 - Repairing integrated circuit memory arrays: A memory array 2 has an address decoder 12 responsive to a repair signal to operate either in a normal mode or a repair mode. In the normal mode a data bit is stored within a single memory cell 6. In the repair mode a data bit is stored within... Agent: Nixon & Vanderhye, PC

20080165610 - Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof: A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control... Agent: Volentine & Whitt PLLC

20080165611 - Synchronous semiconductor memory device: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or... Agent: Mcdermott Will & Emery LLP

20080158928 - Technique for cam width expansion using an external priority encoder: A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a... Agent: Texas Instruments Incorporated

20080158929 - Scalable embedded dram array: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080158930 - Semiconductor memory device for sensing voltages of bit lines in high speed: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell... Agent: Lowe Hauptman Ham & Berner, LLP

20080158931 - Apparatus and methods for optically-coupled memory systems: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein,... Agent: Karen Lenaburg, Esq. Dorsey & Whitney LLP

20080158932 - Memory having bit line with resistor(s) between memory cells: For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled... Agent: Intel/blakely

20080158933 - Method and apparatus to monitor circuit variation effects on electrically programmable fuses: A monitor bank consists of test one time programmable memory that is programmed distinctively from functional one time programmable memory in order to determine whether the functional one time programmable memory has or will program successfully. In a specific embodiment, each monitor bank consists of a first eFuse configured to... Agent: Ibm Corporation Rochester Ip Law Dept. 917

20080158934 - Semiconductor memory device with ferroelectric device and refresh method thereof: A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080158936 - Nonvolatile resistive memories having scalable two-terminal nanotube switches: A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having and a nanotube fabric article disposed between and in electrical communication with two conductive terminals. Selection circuitry is operable to select the... Agent: Wilmerhale/boston

20080158935 - Resistance changing memory cell architecture: A resistance changing memory unit cell includes a current control component operably coupled to a bit sense line, and a resistance changing memory element coupled between the current control component and a word line.... Agent: Eschweiler & Associates, Llc National City Bank Building

20080158937 - Memory device having a threshold voltage switching device and a method for storing information in the memory device: Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture The memory device includes: a plurality of word lines and a plurality of bit lines each regularly arranged, and a plurality of unit memory cells each formed at an intersection between an... Agent: Marshall, Gerstein & Borun LLP

20080158938 - Memory cells with lower power consumption during a write operation: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node,... Agent: Freescale Semiconductor, Inc. Law Department

20080158939 - Memory having improved power design: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power... Agent: Duane Morris LLP Ip Department (tsmc)

20080158942 - Memory having storage locations within a common volume of phase change material: A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage... Agent: Dicke, Billig & Czaja

20080158943 - Method of fabricating an integrated circuit having a memory including a low-k dielectric material: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the... Agent: Dicke, Billig & Czaja

20080158940 - Non-volatile memory device and method of operating the same: Provided are a non-volatile memory device and a method of operating the non-volatile memory device. The non-volatile memory device includes a switching device and a storage node connected to the switching device, wherein the storage node comprises: a first electrode connected to the switching device; a chalcogenide material layer formed... Agent: Harness, Dickey & Pierce, P.L.C

20080158941 - Nonvolatile memory device using variable resistive elements: The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared... Agent: Harness, Dickey & Pierce, P.L.C

20080158944 - Nonvolatile memory device and method for fabricating the same: A nonvolatile memory device includes a plurality of strings each of which is configured with a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first and second select transistors. A common source line is connected to a source of the... Agent: Blakely Sokoloff Taylor & Zafman

20080158945 - Semiconductor memory device: A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor... Agent: Mcdermott Will & Emery LLP

20080158946 - Alternating read mode: Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the... Agent: Vierra Magen/sandisk Corporation

20080158948 - Avoiding errors in a flash memory by using substitution transformations: To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string... Agent: Mark M. Friedman

20080158950 - Apparatus, method, and system for flash memory: Methods, apparatus, systems, and data structures are disclosed, including a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages;... Agent: Schwegman, Lundberg & Woessner, P.a.

20080158955 - Method of programming a multi bit flash memory device to avoid programming errors and a device implementing the same: A method of programming a multi bit flash memory device may perform a kth preliminary verify read operation before performing a kth program operation according to a kth page of program data, where n and k integers, n≧2, and 1≦k≦n. That is, where a (k−1)th program operation produces one or... Agent: Lee & Morse, P.c.

20080158954 - Multi-level operation in dual element cells using a supplemental programming level: The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss,... Agent: Amin, Turocy & Calvin, LLP

20080158953 - Non-volatile memory device and method of programming a multi level cell in the same: A non-volatile memory device of the present invention includes a page buffer having a bit line selecting circuit, a first register, a second register, a data comparing circuit, a first bit line voltage controller, and a second bit line voltage controller. The bit line selecting circuit couples selectively a certain... Agent: Townsend And Townsend And Crew, LLP

20080158951 - Non-volatile multilevel memory cell programming: The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page. One method includes programming a first lower page, programming a second lower page, programming a third lower page, programming an upper page, and... Agent: Brooks, Cameron & Huebsch , Pllc

20080158952 - Non-volatile multilevel memory cell programming: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell... Agent: Brooks, Cameron & Huebsch , Pllc

20080158949 - Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word... Agent: Vierra Magen/sandisk Corporation

20080158956 - Non-volatile memory module for preventing system failure and system including the same: A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed... Agent: F. Chau & Associates, Llc

20080158957 - Nonvolatile semiconductor memory device: A source line driver includes a first transistor, which has one end connected to one end of a second transistor. The first transistor has the other end connected to power supply. A third transistor has one end connected to the other end of the second transistor. The third transistor has... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080158958 - Memory device with reduced reading: A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first... Agent: Darby & Darby P.c.

20080158960 - Applying adaptive body bias to non-volatile storage: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or... Agent: Vierra Magen/sandisk Corporation

20080158962 - Method for managing bad memory blocks in a nonvolatile-memory device, and nonvolatile-memory device implementing the management method: A method for managing bad memory blocks of a nonvolatile-memory device, in which the available memory blocks are divided into a first set, formed by addressable memory blocks that are to be used by a user, and a second set, formed by spare memory blocks that are to replace bad... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080158963 - Nonvolatile memory: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address... Agent: Miles & Stockbridge Pc

20080158959 - Page by page ecc variation in a memory device: A method of storing memory device data overhead information in data cells in a row of cells, the row being one of a plurality of rows comprising a unit of data, is disclosed. The method includes storing user data attribute information in an overhead portion of a data sector in... Agent: Vierra Magen/sandisk Corporation

20080158961 - Semiconductor memory device in which redundancy (rd) of adjacent column is automatically repaired: A semiconductor memory device includes a memory cell array having a plurality of memory cells, a redundancy cell array having a plurality of redundancy cells, and a detection circuit which detects a bad bit line at an end of a bad column of the memory cell array. The semiconductor memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080158964 - Semiconductor memory device which includes stacked gate having charge accumulation layer and control gate: A semiconductor memory device includes memory cells, a memory cell array, a contact region, and first contact plugs. The memory cells include a control gate and a current path. The memory cells are arranged in the memory cell array in the first direction. The contact region is adjacent to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080158965 - Operating method of non-volatile memory: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates... Agent: Jianq Chyun Intellectual Property Office

20080158966 - Variable program and program verification methods for a virtual ground memory in easing buried drain contacts: Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080158970 - Biasing non-volatile storage to compensate for temperature variations: A body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature... Agent: Vierra Magen/sandisk Corporation

20080158971 - Method for reading nand flash memory device using self-boosting: A method for reading a NAND flash memory device is provided. The NAND flash memory device includes a first bit line that is selected and a second bit line that is not selected. Each bit line is connected to a cell string including a string selection transistor, a plurality of... Agent: Townsend And Townsend And Crew, LLP

20080158968 - Method of nand flash memory cell array with adaptive memory state partitioning: A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080158969 - Nand flash memory cell array with adaptive memory state partitioning: A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080158967 - Resistance sensing and compensation for non-volatile storage: When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more... Agent: Vierra Magen/sandisk Corporation

20080158974 - Apparatus with alternating read mode: Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the... Agent: Vierra Magen/sandisk Corporation

20080158976 - Biasing non-volatile storage based on selected word line: A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word... Agent: Vierra Magen/sandisk Corporation

20080158973 - Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word... Agent: Vierra Magen/sandisk Corporation

20080158978 - Memory read circuit and memory apparatus using the same: A memory read circuit includes k sense amplifiers provided for respective k bit lines and reading out data from their corresponding bit lines, where k is a natural number, a shift register that includes k flip-flops connected in cascade and arranged to hold outputs from corresponding sense amplifiers, and to... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20080158972 - Method of controlling bitline bias voltage: Controlling a bitline bias voltage by sensing the bitline bias voltage, modifying a bitline bias control signal in accordance with the sensed bitline bias voltage, and controlling the bitline bias voltage in accordance with the modified bitline bias control signal. The modifying the bitline bias control signal is carried out... Agent: Beyer Law Group LLP/ Sandisk

20080158975 - Non-volatile storage with bias for temperature compensation: A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of... Agent: Vierra Magen/sandisk Corporation

20080158977 - Semiconductor memory device having fuse circuits and method of controlling the same: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in... Agent: Volentine & Whitt Pllc

20080158981 - Method and apparatus for on chip sensing of sonos vt window in non-volatile static random access memory: A system and method for determining a SONOS VT window using a current sensing scheme is disclosed. The present invention creates a first current path and a second current path through the volatile and non-volatile sections of an nvSRAM memory cell. The erase threshold voltage of the first edge of... Agent: Holme Roberts & Owen, LLP

20080158979 - Method for programming with initial programming voltage based on trial: A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a... Agent: Vierra Magen/sandisk Corporation

20080158980 - Non-volatile storage system with initial programming voltage based on trial: A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a... Agent: Vierra Magen/sandisk Corporation

20080158947 - System for controlling voltage in non-volatile memory systems: System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell of the non-volatile memory system. For one of the plurality of modes, a first input value... Agent: Klein, O'neill & Singh, LLP

20080158986 - Flash memory and associated methods: In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation,... Agent: Schwegman, Lundberg & Woessner, P.a.

20080158984 - Margined neighbor reading for non-volatile memory read operations including coupling compensation: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20080158982 - Method and apparatus for adjusting a read reference level under dynamic power conditions: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080158988 - Method and apparatus for sensing flash memory using delta sigma modulation: A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting... Agent: Dickstein Shapiro LLP

20080158987 - Non-volatile memory device and data read method and program verify method of non-volatile memory device: A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array.... Agent: Townsend And Townsend And Crew, LLP

20080158983 - Non-volatile storage system with resistance sensing and compensation: When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more... Agent: Vierra Magen/sandisk Corporation

20080158985 - Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20080158995 - Flash eeprom system: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080158998 - Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high... Agent: Marger Johnson & Mccollom, P.c.

20080158994 - Method for erasing data of nand flash memory device: A method for erasing data of a NAND flash memory device including memory cell blocks may include using a first erase voltage applied to memory cells of a block to be erased. A first verification may be performed to verify erased states of the memory cells using a first verify... Agent: Marshall, Gerstein & Borun LLP

20080158993 - Non-volatile memory device and method capable of re-verifying a verified memory cell: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification... Agent: F. Chau & Associates, Llc

20080158992 - Non-volatile storage with adaptive body bias: A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased... Agent: Vierra Magen/sandisk Corporation

20080158989 - Retention margin program verification: Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence... Agent: Vierra Magen/sandisk Corporation

20080158990 - Retention margin program verification: A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality... Agent: Vierra Magen/sandisk Corporation

20080158997 - Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells: A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells.... Agent: Vierra Magen/sandisk Corporation

20080158996 - Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory: Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may... Agent: Vierra Magen/sandisk Corporation

20080158991 - Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages: Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to... Agent: Vierra Magen/sandisk Corporation

20080159000 - Method for controlling voltage in non-volatile memory systems: Method for controlling voltage in a non-volatile memory system is provided. The method includes selecting a first input value for a voltage generator system operating in one of a plurality of modes, the first input value controlling a temperature dependent component of a voltage applied to a memory cell; and... Agent: Klein, O'neill & Singh, LLP

20080158999 - Methods, apparatus, and systems for flash memory bit line charging: Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data information is received at the circuit. The control circuitry may program the data information into a selected memory cell... Agent: Schwegman, Lundberg & Woessner, P.a.

20080159001 - Apparatus for controlling bitline bias voltage: Controlling a bitline bias voltage by sensing the bitline bias voltage, modifying a bitline bias control signal in accordance with the sensed bitline bias voltage, and controlling the bitline bias voltage in accordance with the modified bitline bias control signal. The modifying the bitline bias control signal is carried out... Agent: Beyer Law Group LLP/ Sandisk

20080159006 - Non-volatile memory device and method of programming the same: A non-volatile memory device comprises an even bit line and an odd bit line contacting to a memory cell array. A register unit includes a first register and a second register for temporarily storing data. A detecting node detects a voltage level of the specific bit line or the specific... Agent: Townsend And Townsend And Crew, LLP

20080159002 - Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data: Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to... Agent: Vierra Magen/sandisk Corporation

20080159004 - Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages: Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to... Agent: Vierra Magen/sandisk Corporation

20080159005 - Selective bit line precharging in non volatile memory: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080159003 - Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data: Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to... Agent: Vierra Magen/sandisk Corporation

20080159007 - Non-volatile storage with bias based on selected word line: A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected... Agent: Vierra Magen/sandisk Corporation

20080159008 - Operating method of p-channel non-volatile memory: A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a... Agent: Jianq Chyun Intellectual Property Office

20080159009 - Method, apparatus, and system for improved erase operation in flash memory: Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a... Agent: Schwegman, Lundberg & Woessner, P.a.

20080159010 - Multi-use efuse macro: A multi-use eFuse macro is presented. A device includes multiplexers and selection logic that allow eFuse latches to store auxiliary data in addition to programming electronic fuses. The multiplexers and selection logic are coupled to the inputs and outputs of the eFuse latches, and are controlled by a processing unit... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080159011 - Address/data multiplexed device: The present invention provides a semiconductor device and a method of controlling the semiconductor device, the semiconductor device comprising: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at... Agent: Murabito, Hao & Barnes LLP

20080159013 - Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device: Provided in one example embodiment, a method of programming n bits of data to a semiconductor memory device may include outputting a first bit of data written in a memory cell from a first latch, storing the first bit of the data to a third latch, storing a second bit... Agent: Harness, Dickey & Pierce, P.L.C

20080159012 - Semiconductor memory device, and multi-chip package and method of operating the same: The present invention relates to a semiconductor device including a MLC capable of storing plural bits of data, wherein some of the MLC are set and operated as a buffer section in response to a control signal.... Agent: Townsend And Townsend And Crew, LLP

20080159017 - Bias voltage generator and method generating bias voltage for semiconductor memory device: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that... Agent: Volentine & Whitt Pllc

20080159018 - Semiconductor memory device having internal voltage generation circuits: A semiconductor memory device according to the present invention comprising: n memory banks, where n is an integer more than 1; a first internal voltage generation circuit allocated to corresponding m memory banks, where m is an integer equal to or smaller than the n; and a second internal voltage... Agent: Young & Thompson

20080159014 - Sram memory device with improved write operation and method thereof: s

20080159016 - Voltage generating circuit of semiconductor memory apparatus capable of reducing power consumption: A voltage generating circuit of a semiconductor memory apparatus is provided including a voltage generator that generates a core voltage in response to a voltage generating signal, a voltage drop part that drops a level of the core voltage to a predetermined target level when the level of the core... Agent: Venable LLP

20080159015 - Voltage pumping device: A voltage pumping device for generating a high voltage that is a boosted voltage is disclosed. The voltage pumping device includes an oscillator for generating a first pulse signal or second pulse signal in response to a control signal, and a high voltage pump for pumping a high voltage of... Agent: Cooper & Dunham, LLP

20080159019 - High speed interface for multi-level memory: A solid state memory system comprises a first memory chip that includes a plurality of storage elements, and a controller. Each of the plurality of storage elements have a measurable parameter that varies between a lower limit and an upper limit. The controller receives write data, converts the write data... Agent: Harness, Dickey & Pierce P.L.C

20080159020 - Word line driving circuit and semiconductor device using the same: A word line driving circuit and a semiconductor device using the same are disclosed. The word line driving circuit includes a second pad separated from a first pad, the first pad being applied with a first ground voltage, the second pad being applied with a second ground voltage, and a... Agent: Cooper & Dunham, LLP

20080159021 - Rfid device having nonvolatile ferroelectric memory device: A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted... Agent: Townsend And Townsend And Crew, LLP

20080159022 - Dynamic adaptive read return of dram data: An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of... Agent: Lemoine Patent Services, Pllc

20080159026 - Memory systems, on-die termination (odt) circuits, and method of odt control: According to one aspect, an on-die termination (ODT) circuit is controlled during transition from a first power mode to a second power mode of a memory device. The transition from an asynchronous ODT circuit path to a synchronous ODT circuit path is delayed to compensate for an operational latency of... Agent: Volentine & Whitt Pllc

20080159023 - Semiconductor memory device with a fixed burst length having column control unit: The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device including: a command decoder decoding external commands to be output as an internal command with fixed burst length information; a column controlling unit giving a bank address... Agent: Ladas & Parry LLP

20080159025 - Semiconductor memory device with various delay values: A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed... Agent: Mcdermott Will & Emery LLP

20080159024 - Sense amplifier enable signal generator for semiconductor memory device: A semiconductor memory device includes a bit line sense amplifier, a sense amplifier enable signal generator, a power line driver, and a driver controller. The bit line sense amplifier senses and amplifies data carried on a bit line. The sense amplifier enable signal generator generates a sense amplifier enable signal... Agent: Mcdermott Will & Emery LLP

20080159027 - Semiconductor memory device with mirror function module and using the same: A semiconductor memory device with a mirror function enables two memory devices such as two DRAMs to share the same address and control signals. A pair of semiconductor memory devices are mounted on both sides of a substrate to be symmetrical to each other. A mirror function transfers a first... Agent: Ladas & Parry LLP

20080159030 - Address pin reduction mode circuit with parallel input for semiconductor memory device and test method using the same: Example embodiments of the present invention include an address pin reduction mode circuit with parallel inputs and a method for testing a semiconductor memory device in an address pin reduction mode based on parallel input-based addressing. A reduction in the number of address pins is achieved by use of a... Agent: Marger Johnson & Mccollom, P.c.

20080159029 - Circuit for testing word line of semiconductor memory device: A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode... Agent: Cooper & Dunham, LLP

20080159031 - Parallel read for front end compression mode: Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of data lines required for transmitting compressed test data. Data lines effectively freed up due to compression of test data read from one bank... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080159028 - Sense amplifier screen circuit and screen method thereof: A sense amplifier screen circuit and a screen method thereof are disclosed. The sense amplifier screen circuit includes a test mode signal generator for generating a test mode signal, a voltage regulator for regulating a bit line precharge voltage in response to the test mode signal, and a driving controller... Agent: Cooper & Dunham, LLP

20080159032 - Method for burst mode, bit line charge transfer and memory using the same: A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080159033 - Precharge voltage supply circuit and semiconductor device using the same: A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first reference voltage having a first voltage level and outputting a first compare signal as a result of the comparison, a second... Agent: Cooper & Dunham, LLP

20080159034 - Method for controlling a semiconductor apparatus: A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power... Agent: Foley And Lardner LLP Suite 500

20080159035 - Array sense amplifiers, memory devices and systems including same, and methods of operation: A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080159036 - Scalable embedded dram array: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080159037 - Semiconductor memory device: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level... Agent: Mills & Onello LLP

20080159041 - Semiconductor memory and operating method of same: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command... Agent: Arent Fox LLP

20080159038 - Semiconductor memory device and method for driving the same: A semiconductor memory device performs a refresh operation stably even while a temperature continuously changes at near a specific temperature. The semiconductor memory device includes an on die thermal sensor (ODTS) and a control signal generator. The on die thermal sensor (ODTS) outputs a thermal code corresponding to a temperature... Agent: Mcdermott Will & Emery LLP

20080159040 - Semiconductor memory device operating a self refreshing and an auto refreshing: An oscillating period of an oscillator is configured to be adjustable by CODEi output from a ROM circuit, and a circuit is configured so that the oscillating period is equal to a period p times a tRAS period during self refreshing. An n-bit counter counts up based on the output... Agent: Sughrue Mion, Pllc

20080159039 - Semiconductor memory device with refresh signal generator and its driving method: A semiconductor memory device includes a level feedback circuit and a refresh signal generator. The level feedback circuit outputs a bulk voltage applied to a cell transistor as a feedback signal. The refresh signal generator generates an internal refresh signal for driving a refresh operation at predetermined intervals during a... Agent: Blakely Sokoloff Taylor & Zafman

20080159042 - Latch circuits and operation circuits having scalable nonvolatile nanotube switches as electronic fuse replacement elements: A non-volatile latch circuit is provided. The non-volatile latch circuit includes a nanotube switching element capable of switching between resistance states and non-volatilely retaining the resistance state. The non-volatile latch circuit includes a volatile latch circuit is capable of receiving and volatilely storing a logic state. When the nanotube switching... Agent: Wilmerhale/boston

20080159046 - Method for two-cycle sensing in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080159043 - Negative voltage generator for use in semiconductor memory device: A negative voltage generator of a semiconductor memory device includes: a flag signal generation unit for receiving a temperature information code from an On Die Thermal Sensor (ODTS) to output a plurality of flag signals containing temperature information of the semiconductor memory device; and a negative voltage detection unit for... Agent: Mcdermott Will & Emery LLP

20080159045 - Semiconductor memory device capable of controlling drivability of overdriver: A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying voltage difference between bit line pair... Agent: Lowe Hauptman Ham & Berner, LLP

20080159044 - Semiconductor memory device for independently controlling internal supply voltages and method of using the same: Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference... Agent: Mills & Onello LLP

20080159047 - Internal voltage generation circuit: Various examples of internal voltage generation circuit are provided. In one example, the internal voltage generation circuit includes a level control signal generator for generating a level control signal in response to a power down mode signal, which is activated synchronously with a clock enable signal, and a precharge flag... Agent: Cooper & Dunham, LLP

20080159049 - Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same: A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter... Agent: Harness, Dickey & Pierce, P.L.C

20080159048 - Semiconductor memory device having power supply wiring network: A semiconductor memory device according to the present invention comprising: a plurality of memory banks; n internal voltage generation circuits for active state each provided to one or more memory banks, activated when corresponding memory bank(s) are in an active state, and deactivated when corresponding memory bank(s) are in a... Agent: Young & Thompson

20080159050 - Semiconductor memory device: A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality... Agent: Mcdermott Will & Emery LLP

20080159051 - Semiconductor memory device: A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the first pair, a second inverter coupled between the second pair, a third inverter coupled between first and... Agent: Mcginn Intellectual Property Law Group, Pllc

20080159055 - Method and circuit for driving word line of memory cell: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an... Agent: Volentine & Whitt Pllc

20080159052 - Method for using a reversible polarity decoder circuit: A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits... Agent: Zagorin O'brien Graham LLP (023)

20080159053 - Reversible polarity decoder circuit: A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits... Agent: Zagorin O'brien Graham LLP (023)

20080159054 - Word line driving method of semiconductor memory device: A semiconductor memory device includes a low voltage supplier for supplying a low voltage lower than a ground voltage; a voltage selector for selecting one of the low voltage and the ground voltage; and a word line driving circuit for driving a word line in response to an output of... Agent: Mcdermott Will & Emery LLP

20080159056 - Internal address generation circuit and internal address generation method: An internal address generation circuit in a semiconductor memory receives an external address signal and generates an internal address. The internal address generation circuit includes a control unit outputting at least more than two address strobe signals which are different from an internal command signal in terms of a strobe... Agent: Ladas & Parry LLP

20080159057 - Column address enable signal generation circuit for semiconductor memory device: A semiconductor memory device includes a clock period detector, a column address enable signal generator, and a multiplexing circuit. The clock period detector detects a period of an external clock in response to a pulse width information signal having a pulse width corresponding to that of the external clock. The... Agent: Mcdermott Will & Emery LLP

20080159058 - Write latency tracking using a delay lock loop in a synchronous dram: A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.l.p.

20080159059 - Progressive memory initialization with waitpoints: A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison... Agent: Larson Newman Abel Polansky & White, LLP

20080159060 - Sequential memory and accessing method thereof: A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in... Agent: Birch Stewart Kolasch & Birch