Static information storage and retrieval inventions 06/08

20080151588 - Full-rail, dual-supply global bitline accelerator cam circuit: A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first... Agent: Ked & Associates, LLP

20080151589 - Semiconductor memory device and method for designing the same: A semiconductor memory device includes first and second column selection signal lines, first bit lines being and second bit lines. The first bit lines are associated with the first column selection signal line. The second bit lines are associated with the second column lines. At least one of the first... Agent: Young & Thompson

20080151590 - Method and apparatus for protection against process-induced charging: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the... Agent: Ingrassia Fisher & Lorenz, P.c.

20080151591 - Memory system with a configurable number of read data bits: In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes... Agent: Intel/blakely

20080151592 - Semiconductor device and method of fabricating a semiconductor device: Method of fabricating a semiconductor device, comprising the steps of providing a substrate with a plurality of contact portions; forming a plurality of electrical contacts such that a contact is electrically connected to each of the contact portions, the contacts each comprising a contact area for connecting to a further... Agent: Slater & Matsil LLP

20080151593 - Fuse cell array with redundancy features: An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are... Agent: Intel/blakely

20080151594 - Semiconductor device with a plurality of one time programmable elements: A semiconductor device with a plurality of one time programmable elements and to a method for programming a semiconductor device, and to a method for operating a semiconductor device is disclosed. One embodiment provides a method for programming a semiconductor device comprising a plurality of one time programmable elements that... Agent: Dicke, Billig & Czaja

20080151595 - Radiation tolerant sram bit: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter.... Agent: Lewis And Roca, LLP

20080151596 - Three-dimensional magnetic memory: Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. Bits may be written to a data storage layer in the form of magnetic domains. The bits can then be transferred between the stacked... Agent: Duft Bornsen & Fishman, LLP

20080151598 - Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory: Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a negative charge to a memory array bitline through a zero cancellation capacitor while a memory cell plateline signal is applied during a read operation, wherein one... Agent: Texas Instruments Incorporated

20080151600 - Logical operation circuit and logical operation device: To provide a logical operation circuit and a logical operation device which can performs a logical operation using a ferroelectric capacitor. The area ratio between the ferroelectric capacitors CF1 and CF2 are set such that the potential difference Vdef between voltages Va1 and Va0 is as large as possible, and... Agent: Hogan & Hartson L.l.p.

20080151599 - Semiconductor device including a ferroelectric field-effect transistor, and semiconductor integrated circuit device employing same: A semiconductor device has a ferroelectric field-effect transistor having a gate portion whose equivalent circuit is composed of a ferroelectric capacitor CF and a paraelectric capacitor CP connected in series, the ferroelectric field-effect transistor having a threshold voltage VTH corresponding to a residual polarization of the ferroelectric capacitor CF, and... Agent: Fish & Richardson P.c.

20080151597 - Wear-resistant multilayer probe: A data storage device includes a probe having a first conductive element, a second conductive element and an insulator layer positioned between the first conductive element and the second conductive element.... Agent: Pietragallo Gordon Alfano Bosick & Raspanti, LLP

20080151601 - Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices: A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive... Agent: Myers Bigel Sibley & Sajovec

20080151602 - Nonvolatile memory and semiconductor device including nonvolatile memory: An object is to provide a nonvolatile memory with reduced power consumption. The nonvolatile memory includes a memory element that has a low resistance state and a high resistance state, a writing circuit, a resistance element, a voltage source input terminal that inputs a writing voltage to the writing circuit,... Agent: Eric Robinson

20080151603 - Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube... Agent: Intel/blakely

20080151604 - Semiconductor memory device: In a semiconductor memory device including memory cells each having two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair and two access transistors, a plurality of word lines, and a plurality of bit lines, the potential of the selected one of the... Agent: Mcdermott Will & Emery LLP

20080151605 - 8-t sram cell circuit, system and method for low leakage current: An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage at different nodes, when either bit ‘0’ or ‘1’ is... Agent: Paul F. Rusyn

20080151606 - Semiconductor memory device: A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit... Agent: Mcdermott Will & Emery LLP

20080151611 - Method and system for providing a magnetic memory structure utilizing spin transfer: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element... Agent: Strategic Patent Group, P.c.

20080151609 - Method for operating a data storage apparatus employing passive matrix addressing: In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated... Agent: Birch Stewart Kolasch & Birch

20080151608 - Semiconductor memory device and write and read methods of the same: A semiconductor memory device includes first to fourth resistance change elements sequentially arranged apart from each other in a first direction, a first electrode which connects one terminals of the first and second resistance change elements, a second electrode which connects one terminals of the third and fourth resistance change... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080151610 - Spintronic devices with integrated transistors: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in... Agent: Knobbe Martens Olson & Bear LLP

20080151607 - Storage element and memory: Disclosed is a storage element having a storage layer retaining information based on a magnetization state of a magnetic material; a fixed-magnetization layer having a ferromagnetic layer; and an intermediate layer interposed between the storage layer and the fixed-magnetization layer. In the storage element, spin-polarized electrons are injected in a... Agent: Bell, Boyd & Lloyd, LLP

20080151612 - Method for multilevel programming of phase change memory cells using a percolation algorithm: A method and apparatus for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which... Agent: Seed Intellectual Property Law Group Pllc

20080151613 - Programming method for phase change memory: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the... Agent: Quintero Law Office, Pc

20080151614 - Spin transfer mram device with magnetic biasing: The addition of segmented write word lines to a spin-transfer MRAM structure serves to magnetically bias the free layer so that the precessional motion of the magnetization vector that is set in play by the flow of spin polarized electrons into the free layer allows said magnetic vector to be... Agent: Stephen B. Ackerman

20080151615 - Magnetic multilayer device, method for producing such a device, magnetic field sensor, magnetic memory and logic gate using such a device: This magnetic multilayer device comprises, on a substrate, an alternating sequence of magnetic metallic layers M and oxide, hydride or nitride layers O. The number of layers M equals at least two. The layers M are continuous. There is interfacial magnetic anisotropy perpendicular to the plane of the layers at... Agent: Burr & Brown

20080151616 - Method and apparatus to program both sides of a non-volatile static random access memory: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.... Agent: Holme Roberts & Owen, LLP

20080151618 - Flash memory device and system with randomizing for suppressing errors: A device for storing data includes a nonvolatile memory and a controller and/or circuitry that randomize original data to be stored in the memory while preserving the size of the original data, that store the original data in the memory, and that, in response to a request for the original... Agent: Mark M. Friedman

20080151621 - Multi-level cell memory devices and methods of storing data in and reading data from the memory devices: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order... Agent: Harness, Dickey & Pierce, P.L.C

20080151622 - Command-based control of nand flash memory: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer... Agent: Intel/blakely

20080151623 - Non-volatile memory in cmos logic process: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080151624 - Combination sram and nvsram semiconductor memory array: A semiconductor memory array having a first memory cell array with a number of first memory cells and a second cell array with a number of second memory cells. The memory cells in the first and second memory cell arrays are arranged in rows and columns. Each column of second... Agent: Holme Roberts & Owen, LLP

20080151625 - Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time: Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the... Agent: Mcdermott Will & Emery LLP

20080151626 - Semiconductor memory device: A memory cell array includes a plurality of memory cells arranged at intersections of bitline pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080151627 - Method of low voltage programming of non-volatile memory cells: A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node... Agent: Beyer Law Group LLP/ Sandisk

20080151629 - Semiconductor device: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first... Agent: Miles & Stockbridge Pc

20080151628 - System for low voltage programming of non-volatile memory cells: System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a... Agent: Beyer Law Group LLP/ Sandisk

20080151632 - Flash memory device having multi-level cell and reading and programming method thereof: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and... Agent: Marger Johnson & Mccollom, P.c.

20080151631 - Non-volatile memory device and method of operating the same: A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080151630 - System for reducing wordline recovery time: System for reducing wordline recovery time for a wordline having a wordline capacitance CWL by configuring the wordline capacitance CWL and a load capacitance CL in a series configuration with respect to a first node. Supplying a charging current at a first node from a charge pump having an initial... Agent: Beyer Law Group LLP/ Sandisk

20080151633 - Method of programming in a non-volatile memory device and non-volatile memory device for performing the same: Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are... Agent: Myers Bigel Sibley & Sajovec

20080151617 - Soft decoding of hard and soft bits read from a flash memory: To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each... Agent: Mark M. Friedman

20080151634 - Negative wordline bias for reduction of leakage current during flash memory operation: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight... Agent: Ingrassia Fisher & Lorenz, P.c.

20080151635 - Semiconductor memory devices and a method thereof: Semiconductor memory devices and a method thereof are provided. An example semiconductor memory device may include a control signal generation unit configured to generate a plurality of control signals in response to a bias current, a reference current generation unit configured to generate a reference current in response to the... Agent: Harness, Dickey & Pierce, P.L.C

20080151637 - Interleaved memory program and verify method, device and system: An interleaved memory programming and verification method, device and system includes a memory array includes first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory... Agent: Trask Britt, P.c./ Micron Technology

20080151636 - Repetitive erase verify technique for flash memory devices: Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure,... Agent: Ingrassia Fisher & Lorenz, P.c.

20080151638 - Selective threshold voltage verification and compaction: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution... Agent: Leffert Jay & Polglaze, P.a. Attn: Thomas W. Leffert

20080151639 - Flash memory device with external high voltage supply: A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage... Agent: Ingrassia Fisher & Lorenz, P.c.

20080151641 - Non-volatile memory device reducing data programming and verification time, and method of driving the same: Provided are a non-volatile memory device in which time required for programming may be saved, and a method of driving the same. The non-volatile memory device may include a memory cell array with a plurality of memory cells; an input/output buffer having a storage unit that stores data and indicator... Agent: Harness, Dickey & Pierce, P.L.C

20080151640 - Semiconductor integrated circuit device: This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080151644 - Cycling improvement using higher erase bias: Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined... Agent: Eschweiler & Associates, Llc National City Bank Building

20080151642 - Double-side-bias methods of programming and erasing a virtual ground array memory: The present invention provides a method for applying a double-side-bias operation to a virtual ground array memory composed of a matrix of N-bit memory cells. In a first embodiment, the virtual ground array is programmed by a double-side-bias method which applies the same or similar biasing voltage simultaneously on the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080151643 - Method and apparatus to create an erase disturb on a non-volatile static random access memory cell: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory... Agent: Holme Roberts & Owen, LLP

20080151645 - Operating method of non-volatile memory: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate... Agent: Jianq Chyun Intellectual Property Office

20080151619 - Method and apparatus for adaptive memory cell overerase compensation: A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more... Agent: Ingrassia Fisher & Lorenz, P.c.

20080151620 - Scheme of semiconductor memory and method for operating same: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then,... Agent: Rabin & Berdo, Pc

20080151646 - Flash memory device with improved erase operation: Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first... Agent: Schwegman, Lundberg & Woessner, P.a.

20080151651 - Semiconductor memory utilizing a method of coding data: A semiconductor memory device utilizing a data coding method in an initial operation. The semiconductor memory device includes a plurality of counters communicating with a data coding unit. The counters count the number of data bits and flag information data bits in a first logic state in a first data... Agent: Volentine & Whitt Pllc

20080151648 - High speed fanned out system architecture and input/output circuits for non-volatile memory: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include... Agent: Trop, Pruner & Hu, P.c.

20080151647 - Programmable sense amplifier multiplexer circuit with dynamic latching mode: Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment... Agent: Edell, Shapiro & Finnan, Llc

20080151649 - Nonvolatile latch circuit and system on chip with the same: A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time. The nonvolatile latch circuit does not require an additional data storage period but... Agent: Townsend And Townsend And Crew, LLP

20080151650 - Method of reducing wordline recovery time: Reducing wordline recovery time for a wordline having a wordline capacitance CWL by configuring the wordline capacitance CWL and a load capacitance CL in a series configuration with respect to a first node. Supplying a charging current at a first node from a charge pump having an initial low voltage... Agent: Beyer Law Group LLP/ Sandisk

20080151652 - Nonvolatile memory devices that utilize read/write merge circuits: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write... Agent: Myers Bigel Sibley & Sajovec

20080151653 - Semiconductor memory device: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with... Agent: Mcdermott Will & Emery LLP

20080151654 - Method and apparatus to implement a reset function in a non-volatile static random access memory: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all... Agent: Holme Roberts & Owen, LLP

20080151657 - Semiconductor memory device: Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable... Agent: Mcdermott Will & Emery LLP

20080151655 - Semiconductor memory device and burn-in test method thereof: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines... Agent: Mills & Onello LLP

20080151656 - Semiconductor memory device and write control mehod therefor: Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell for the time... Agent: Mcginn Intellectual Property Law Group, Pllc

20080151658 - Using common mode differential data signals of ddr2 sdram for control signal transmission: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output... Agent: Cantor Colburn LLP - Ibm Rochester Division

20080151660 - Semiconductor device: An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected... Agent: Eric Robinson

20080151659 - Semiconductor memory device: A semiconductor memory device includes at least one memory bank. Each memory bank includes: memory units that output data in response to a burst read command; a selector section that sequentially outputs the data output from the memory units in accordance with a select signal; a comparator section that compares... Agent: Sughrue Mion, Pllc

20080151661 - Semiconductor integrated circuit device comprising mos transistor having charge storage layer and method for testing semiconductor memory device: A semiconductor integrated circuit device includes a semiconductor memory and a test circuit. The semiconductor memory includes a memory block having a plurality of memory cells and tests the memory cells. The test circuit includes a controller and a counter. The controller consecutively increments a gate voltage of the memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080151662 - Leakage current control device of semiconductor memory device: A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control... Agent: Townsend And Townsend And Crew, LLP

20080151663 - Delayed sense amplifier multiplexer isolation: Methods and circuit arrangements are provided for improving equalization of sense nodes of a sense amplifier in a semiconductor memory device. When a memory array segment on a side a sense amplifier has a bitline leakage anomaly for which the sense amplifier is to be isolated when that memory is... Agent: Edell, Shapiro & Finnan, Llc

20080151665 - Semiconductor integrated circuit and method of operating the same: One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells... Agent: Harness, Dickey & Pierce, P.L.C

20080151664 - Sense amplifier circuit of semiconductor memory device and method of operating the same: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage... Agent: F. Chau & Associates, Llc

20080151667 - Method for decreasing program disturb in memory cells: The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for... Agent: Squire, Sanders & Dempsey L.l.p.

20080151666 - Method of decreasing program disturb in memory cells: The present invention provides a method of decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensure programming memory cell normally; selecting one parameter from the initial programming condition as a variable for the program disturb test; performing the program disturb test to the memory cell... Agent: Squire, Sanders & Dempsey L.l.p.

20080151668 - Semiconductor integrated circuit: One of a pair of data output units outputs data to one of the data line pair precharged to a reference voltage. A switch control unit couples the other of the data line pair to the data line, which corresponds to a data line to which data are not output,... Agent: Arent Fox LLP

20080151672 - Determining relative amount of usage of data retaining device based on potential of charge storing device: A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device.... Agent: Hoffman, Warnick & D'alessandro Llc

20080151670 - Memory device, memory controller and memory system: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a... Agent: Arent Fox LLP

20080151671 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080151669 - Use of periodic refresh in medium retention memory arrays: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of... Agent: Amin, Turocy & Calvin, LLP

20080151673 - Pg-gated data retention technique for reducing leakage in memory cells: A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept... Agent: Baker Botts L.l.p.

20080151675 - Reduction of power consumption of an integrated electronic system comprising distinct static random access resources for storing data: An integrated circuit includes an array of memory cells arranged in a plurality of sectors. Each sector includes a plurality of distinct random access memory resources able to be accessed differently in different modes. Peripheral circuitry is commonly shared by at least some of the sectors for addressing and reading/writing... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.a.

20080151674 - Semiconductor memory device and method of driving the same: A semiconductor memory device includes a first circuit which generates a first potential lower than the external power supply voltage, a second circuit which generates a second potential lower than the first potential, a capacitor charged to the first potential, a bit line connected to a memory cell, a sense... Agent: Young & Thompson

20080151676 - Semiconductor integrated circuit: A semiconductor integrated circuit in which a semiconductor chip 4 having a semiconductor memory and a mother chip 2 having logic circuit are mounted in a single package, wherein the leak current of the semiconductor chip 4 is reduced in standby state. A switch cell 20 that connects to the... Agent: Oliff & Berridge, Plc

20080151677 - Memory device, memory controller and memory system: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of... Agent: Arent Fox LLP

20080151678 - Memory device, memory controller and memory system: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within... Agent: Arent Fox LLP

20080151679 - Synchronous semiconductor memory device: A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by... Agent: Blakely Sokoloff Taylor & Zafman

20080151680 - Circuit for outputting data of semiconductor memory apparatus: A circuit for outputting data of a semiconductor memory apparatus is provided. A circuit for outputting data of a semiconductor memory apparatus according to an embodiment of the present invention includes a data clock generating unit that generates a data clock, a delayed clock generating unit that receives the data... Agent: Venable LLP

20080144345 - Semiconductor memory device: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the... Agent: Miles & Stockbridge Pc

20080144346 - Semiconductor memory device having plural memory cell arrays: A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region,... Agent: Young & Thompson

20080144347 - Semiconductor device: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080144348 - High performance single event upset hardened sram cell: An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between... Agent: Schmeiser, Olsen & Watts

20080144349 - Memory device, semiconductor device, and driving method thereof: To provide a memory device which operates with low power consumption, has high reliability of the stored data, and is small-size, light-weight and inexpensive, and a driving method thereof. In addition, to provide a semiconductor device which operates with low power consumption, has high reliability of the stored data and... Agent: Eric Robinson

20080144350 - Voltage programming switch for one-time-programmable (otp) memories: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for... Agent: Mendelsohn & Associates, P.c.

20080144352 - Ferroelectric memory device and method of manufacturing the same: A ferroelectric memory device includes: a substrate; a first insulating film formed above the substrate, the first insulating film including a plug; a ferroelectric capacitor formed above the first insulating film; the ferroelectric capacitor including a lower electrode formed above the plug, a ferroelectric film formed on the lower electrode,... Agent: Harness, Dickey & Pierce, P.L.C

20080144351 - Methods and systems for accessing a ferroelectric memory: One embodiment relates to a method for accessing ferroelectric memory cells in a ferroelectric memory device. A first memory access is performed on the cell, and a second memory access is performed on the cell. An approximately same bias is applied to the bitline and plateline of the cell for... Agent: Peter Mclarty, Esq. Texas Instruments Incorporated

20080144355 - Dielectric antifuse for electro-thermally programmable device: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080144357 - Method for sensing a signal in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080144353 - Method, apparatus and computer program product for read before programming process on programmable resistive memory cell: A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The method further comprises executing the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080144356 - Nonvolatile memory devices having multi-filament variable resistivity memory cells therein: There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and... Agent: Myers Bigel Sibley & Sajovec

20080144354 - Resistive memory array using p-i-n diode select device and methods of fabrication thereof: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such... Agent: Paul J. Winters

20080144358 - Read state retention circuit and method: A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit is coupled to the charge storage unit for charging the charge storage unit. The sensing circuit is coupled to the charge... Agent: Rabin & Berdo, Pc

20080144360 - Semiconductor device: A semiconductor device comprises a first memory cell comprising more than seven transistors and storing data in a latch circuit; and a second memory cell storing data in a capacitor; a sense amplifier having about the same circuit configuration of the first memory cell and detecting data stored in the... Agent: Young & Thompson

20080144359 - Semiconductor memory and method of writing data into the semiconductor memory: A non-volatile semiconductor memory including a silicon substrate having first and second diffusion layers at its surface and a control gate located above a channel region defined by the first and the second diffusion layers and formed on the silicon substrate. The memory further includes first, second and third capacitors... Agent: Junichi Mimura Oki America Inc.

20080144361 - Static random access memory architecture: An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit line pairs, and a second set or group or stage of SRAM banks are coupled... Agent: Schwegman, Lundberg & Woessner, P.a.

20080144362 - Asymmetrical memory cells and memories using the cells: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control... Agent: Ryan, Mason & Lewis, LLP

20080144363 - Method of testing pram device: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data... Agent: Volentine & Whitt Pllc

20080144364 - Multi-bit electro-mechanical memory device and method of manufacturing the same: There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line... Agent: Mills & Onello LLP

20080144365 - Semiconductor integrated circuit and manufacturing method therefor: In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and... Agent: Miles & Stockbridge Pc

20080144366 - Dual-bit memory device having trench isolation material disposed near bit line contact areas: A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory device comprises a substrate, first and second buried bit... Agent: Ingrassia Fisher & Lorenz, P.c.

20080144367 - Sensing device for floating body cell memory and method thereof: A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide... Agent: Larson Newman Abel Polansky & White, LLP

20080144372 - Flash memory device with multi level cell and burst access method therein: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words... Agent: Marger Johnson & Mccollom, P.c.

20080144370 - Method of programming multi-level cells and non-volatile memory device including the same: A non-volatile memory device has multi-level cells (MLCs), which are programmed such that one page is written in the MLCs having previous states corresponding to at least one previous page. The non-volatile memory device includes a memory cell array, a row selection circuit and a page buffer block. The memory... Agent: Volentine & Whitt Pllc

20080144369 - Multi-level memory cell sensing: The delay arising from wordline capacitance in multi-level memories may be reduced by adding switched transistors along the wordline path. Also, the wordline may be pre-charged to a high level and then the first wordline voltage level for reading may be a center level. The switched transistors may be p-devices... Agent: Trop Pruner & Hu, Pc

20080144373 - Single level cell programming in a multiple level cell non-volatile memory device: A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20080144371 - Systems and methods for programming a memory device: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming.... Agent: Baker & Mckenzie LLP Patent Department

20080144376 - External clock tracking pipelined latch scheme: A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second... Agent: Schwegman, Lundberg & Woessner, P.a.

20080144375 - Flash memory device with shunt: A flash memory with a shunt is disclosed. A shunt activation signal is transmitted by an external control terminal through an external transmission interface to switch a flash memory controller in a shunt mode. The shunt activation signal of the external transmission interface can set up a switch as shunt.... Agent: Jianq Chyun Intellectual Property Office

20080144374 - Nonvolatile memory: A memory cell for storing 1-bit data is formed by using at least two memory elements in the OTP type nonvolatile memory using a memory element that have two states and can transit only in one direction. In the OTP type nonvolatile memory using a memory element that has two... Agent: Eric Robinson

20080144378 - Nonvolatile semiconductor memory device having reduced electrical stress: A nonvolatile semiconductor memory includes a floating formation switch coupled to a bit line in a memory cell array. The floating formation switch maintains a channel voltage of memory cells coupled to the bit line at a level above a power supply voltage when the bit line is a non-selected... Agent: Volentine & Whitt Pllc

20080144377 - Nonvolatile semiconductor storage unit and production method therefor: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon... Agent: Mcginn Intellectual Property Law Group, Pllc

20080144379 - Implementation of column redundancy for a flash memory with a high write parallelism: A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with... Agent: Schwegman, Lundberg & Woessner / Atmel

20080144380 - Nonvolatile memory device having flag cells for storing msb program state: A nonvolatile memory device comprises a memory cell array comprising memory cells arranged in rows and first columns and flag cells arranged in the rows and second columns. The device further comprises a page buffer configured to read flag data bits from flag cells in a selected row via the... Agent: Volentine & Whitt Pllc

20080144381 - Flash memory device and method of changing block size in the same using address shifting: According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external... Agent: Harness, Dickey & Pierce, P.L.C

20080144384 - Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices: A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also... Agent: Weaver Austin Villeneuve Sampson LLP

20080144383 - Nonvolatile semiconductor memory device: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the... Agent: Mcdermott Will & Emery LLP

20080144382 - Semiconductor memory device: When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory... Agent: Stroock & Stroock & Lavan LLP

20080144368 - Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory: Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may... Agent: Vierra Magen/sandisk Corporation

20080144386 - Indirect measurement of negative margin voltages in endurance testing of eeprom cells: An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled... Agent: Schwegman, Lundberg & Woessner, P.a.

20080144385 - Nonvolatile memory device: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed. The memory device comprising: a first current detecting circuit comprising a first transistor... Agent: Murabito, Hao & Barnes LLP

20080144387 - Flash memory device and method of erasing flash memory device: A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory... Agent: Volentine & Whitt Pllc

20080144388 - Nonvolatile storage device and control method thereof: A nonvolatile memory device that responds to a decrease in electric charge stored in memory cells attributed to the charge loss phenomenon occurring during program operation by adjusting the level of a program verify operation according to the degree of the charge loss so that the program operation can be... Agent: Murabito, Hao & Barnes LLP

20080144390 - Drain voltage regulator: A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated.... Agent: Eschweiler & Associates, Llc National City Bank Building

20080144389 - Word line driver design in nor flash memory: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word... Agent: Duane Morris, LLP Ip Department

20080144391 - Methods and systems for memory devices: m

20080144392 - Methods for reducing write time in nonvolatile memory devices and related devices: A method of operating a non-volatile memory device includes maintaining a write voltage at a predetermined voltage level for programming and/or erasing a memory cell of the non-volatile memory device during a time between execution of consecutive write operations. For example, the write voltage may be activated at the predetermined... Agent: Myers Bigel Sibley & Sajovec

20080144393 - Bit line pre-settlement circuit and method for flash memory sensing scheme: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of... Agent: Lewis And Roca, LLP

20080144394 - Nonvolatile semiconductor memory having suitable crystal orientation: An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second... Agent: Mcginn Intellectual Property Law Group, Pllc

20080144395 - Operating method of non-volatile memory: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate.... Agent: Jianq Chyun Intellectual Property Office

20080144396 - Erasing flash memory using adaptive drain and/or gate bias: A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase... Agent: Ingrassia Fisher & Lorenz, P.c.

20080144397 - Pipe latch circult of multi-bit prefetch-type semiconductor memory device with improved structure: Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first... Agent: Lowe Hauptman Ham & Berner, LLP

20080144398 - Input buffer and method with ac positive feedback, and a memory device and computer system using same: An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080144399 - Latch circuit and deserializer circuit: A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supply 150 is connected to... Agent: Katten Muchin Rosenman LLP

20080144400 - Scanning latches using selecting array: A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By... Agent: Dillon & Yudell LLP

20080144401 - Self-timing read architecture for semiconductor memory and method for providing the same: A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block with... Agent: Seed Intellectual Property Law Group Pllc

20080144402 - Semiconductor memory device: A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080144403 - Method and circuitry to generate a reference current for reading a memory cell, and device implementing same: There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by read circuitry to read the data state... Agent: Neil Steinberg

20080144404 - Semiconductor memory device: The semiconductor memory device includes a plurality of band groups each including a plurality of banks sharing one of a plurality of global input/output line groups, a data input unit configured to transfer external data to data input global lines in response to write commands corresponding to the respective bank... Agent: Mcdermott Will & Emery LLP

20080144405 - Data strobe timing compensation: A method, apparatus, and system are disclosed. In one embodiment, the method receiving data from a memory on a first interconnect of at least one interconnect, receiving a source-synchronous data strobe from the memory, creating at least a nominal, an early, and a delayed compensated data strobe from the received... Agent: Intel/blakely

20080144406 - Memory system, memory device, and output data strobe signal generating method: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more... Agent: Harness, Dickey & Pierce, P.L.C

20080144408 - Asynchronous, high-bandwidth memory component using calibrated timing elements: Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are... Agent: Rambus/shemwell Mahamedi LLP

20080144407 - Stacked inverter delay chain: Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20080144409 - Byte writeable memory with bit-column voltage selection and column redundancy: A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one... Agent: Freescale Semiconductor, Inc. Law Department

20080144411 - Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a... Agent: Deniro/rambus

20080144410 - Redundancy circuit and semiconductor memory device: Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and... Agent: Foley And Lardner LLP Suite 500

20080144412 - Method and device for testing memory: A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular... Agent: Qualcomm Incorporated

20080144413 - Memory device of sram type: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080144414 - Semiconductor memory devices and method of sensing bit line thereof: A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided... Agent: Myers Bigel Sibley & Sajovec

20080144415 - On-chip temperature sensor: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20080144418 - Dynamic random access memory device and method for self-refreshing memory cells: A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080144417 - Semiconductor memory, operating method of semiconductor memory, memory controller, and system: A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory... Agent: Arent Fox LLP

20080144416 - Semiconductor storage device: A potential level of a word line when it is inactive is made different between during a self-refresh operation and during other than the self-refresh operation. The potential level is set to a ground potential GND during the self-refresh operation and set to a negative potential during other than the... Agent: Mcginn Intellectual Property Law Group, Pllc

20080144419 - Power switching circuit: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080144420 - Voltage control circuit, a voltage control method and a semiconductor memory device having the voltage control circuit: The present invention relates to a semiconductor memory device and more particularly there is disclosed a voltage control circuit, a voltage control method and a semiconductor memory device having the voltage control circuit which can reduce leakage currents and improve precharge performance. The present invention includes a voltage control circuit... Agent: Ladas & Parry LLP

20080144421 - Universal structure for memory cell characterization: An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes,... Agent: Texas Instruments Incorporated

20080144422 - Apparatus and method for data outputting: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of... Agent: Mcdermott Will & Emery LLP

20080144423 - Timing synchronization circuit with loop counter: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback... Agent: Williams, Morgan & Amerson

20080137387 - Low-power cam cell: In one embodiment, a CAM cell is provided that includes: an SRAM cell adapted to store a bit; a data line adapted to provide a corresponding comparand bit; an XOR gate adapted to XOR the stored bit and the comparand bit to provide an XOR output, and a switch adapted... Agent: Macpherson Kwok Chen & Heid LLP

20080137388 - Novel match mismatch emulation scheme for an addressed location in a cam: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write... Agent: Texas Instruments Incorporated

20080137391 - Dram architecture: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than... Agent: Macpherson Kwok Chen & Heid LLP

20080137390 - Dram with reduced power consumption: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of... Agent: Macpherson Kwok Chen & Heid LLP

20080137389 - Multi-stack memory device: Provided is a multi-stack memory device that includes a storage unit group including a plurality of storage units that are vertically stacked and form a plurality of storage unit rows, and a plurality of transistors connected to the storage unit group, wherein the transistors that are connected to the storage... Agent: Harness, Dickey & Pierce, P.L.C

20080137392 - 6f2 dram cell design with 3f-pitch folded digitline sense amplifier: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F2 is disclosed which has a plurality of dual bit active areas, each of the... Agent: Williams, Morgan & Amerson

20080137393 - Semiconductor memory device: This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137394 - Semiconductor memory device: One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to... Agent: Mcdermott Will & Emery LLP

20080137395 - Data storage device using magnetic domain wall movement and method of operating the same: Provided are a data storage device using magnetic domain wall movement and a method of operating the data storage device. The data storage device includes a first magnetic layer for writing data having two magnetic domains magnetized in opposite directions to each other and a second magnetic layer for storing... Agent: Harness, Dickey & Pierce, P.L.C

20080137396 - Spin glass memory cell: A memory cell includes a first electrode, a second electrode, and spin glass material. The spin glass material is coupled between the first electrode and the second electrode.... Agent: Dicke, Billig & Czaja

20080137397 - Non-volatile switching and memory devices using vertical nanotubes: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.... Agent: Schmeiser, Olsen & Watts

20080137398 - Static random access memory: A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of... Agent: Birch Stewart Kolasch & Birch

20080137399 - Single chip having magnetoresistive memory: A single chip has a substrate and at least one magnetoresistive memory layer. The substrate has an underlying memory and a control circuit. The magnetoresistive memory layer is placed on the substrate, and has a plurality of magnetoresistive random access memory cells controlled by the control circuit.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080137402 - Apparatus and systems using phase change memories: Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver... Agent: Myers Bigel Sibley & Sajovec

20080137401 - Memory that limits power consumption: One embodiment provides a memory including resistive memory cells, a pulse generator, and a circuit. Each of the resistive memory cells is programmable to each of at least two states. The pulse generator provides write pulses to program the resistive memory cells. The circuit receives a first current and limits... Agent: Dicke, Billig & Czaja

20080137400 - Phase change memory cell with thermal barrier and method for fabricating the same: A memory cell has thermal isolation material between a bottom electrode and a plug contact to confine heat in a memory element during programming and reset operations. In a particular embodiment, the memory element is a chalcogenide, such as GST. An electrically conductive barrier layer deposited over the contact and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080137403 - Semiconductor memory: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction... Agent: Miles & Stockbridge Pc

20080137404 - Memory device and method of manufacturing a memory device: A memory device includes a bit line, a first word line, a bit line contact, an electrode, a second word line and a contact tip. The bit line may extend along a first direction. The first word line is formed over the bit line and extends in a second direction.... Agent: Stanzione & Kim, LLP

20080137405 - Current injection magnetic domain wall moving element: The present invention provides a current injection-type magnetic domain wall-motion device which requires no external magnetic field for reversing the magnetization direction of a ferromagnetic body and which has low power consumption. The current injection-type magnetic domain wall-motion device includes a microjunction structure including two magnetic bodies (a first magnetic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137406 - Magnetic domain information storage device and method of manufacturing the same: Example embodiments may provide magnetic domain information storage devices with trenches and a method of manufacturing the information storage device. Example embodiment information storage devices may include a magnetic layer on a substrate having a plurality of magnetic domains and a power unit for moving magnetic domain walls. Magnetic layers... Agent: Harness, Dickey & Pierce, P.L.C

20080137407 - Memory structure and operating method thereof: A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that... Agent: Birch Stewart Kolasch & Birch

20080137410 - Non-volatile memory embedded in a conventional logic process and methods for operating same: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080137411 - Reducing read disturb for non-volatile storage: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of... Agent: Vierra Magen/sandisk Corporation

20080137418 - Method and apparatus for sensing in charge trapping non-volatile memory: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080137416 - Multi bit flash memory device and method of programming the same: A method of programming a flash memory device may include dividing a plurality of memory cells into a plurality of groups according to a threshold voltage state, the memory cells configured to store multi bit data. The plurality of memory cells may be programmed with a program data. The memory... Agent: Harness, Dickey & Pierce, P.L.C

20080137415 - Multi-bit flash memory device and program method thereof: A method for programming a flash memory device including a plurality of memory cells, each storing multi-bit data, includes reading data from selected memory cells. An error of the read data is detected and corrected. Input program data is programmed into the selected memory cells based upon the error-corrected read... Agent: F. Chau & Associates, Llc

20080137414 - Multi-level cell memory device and method thereof: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and... Agent: Harness, Dickey & Pierce, P.L.C

20080137413 - Multi-level cell memory devices using trellis coded modulation and methods of storing data in and reading data from the memory devices: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a TCM modulator that applies a program pulse to the MLC memory cell to write the data in the... Agent: Harness, Dickey & Pierce, P.L.C

20080137417 - Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same: The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within... Agent: F. Chau & Associates, Llc

20080137419 - Non-volatile memory with redundancy data buffered in remote buffer circuits: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080137408 - Single poly cmos logic memory cell for rfid application and its programming and erasing method: An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080137420 - Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats: A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.... Agent: Myers Bigel Sibley & Sajovec

20080137421 - Pattern layout of integrated circuit: In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080137423 - Reducing read disturb for non-volatile storage: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of... Agent: Vierra Magen/sandisk Corporation

20080137424 - Reducing read disturb for non-volatile storage: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of... Agent: Vierra Magen/sandisk Corporation

20080137422 - Semiconductor memory device and method of erasing data therein: A semiconductor memory device comprises a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137429 - Data processing device: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines... Agent: Miles & Stockbridge Pc

20080137430 - Low-voltage reading device in particular for mram memory: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080137426 - Non-volatile storage with early source-side boosting for reducing program disturb: Non-volatile storage with reduced program disturb is provided by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach,... Agent: Vierra Magen/sandisk Corporation

20080137428 - Power supply circuit and semiconductor memory: A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137427 - Programming scheme for non-volatile flash memory: An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to... Agent: Akin Gump LLP - Silicon Valley

20080137425 - Reducing program disturb in non-volatile storage using early source-side boosting: Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a... Agent: Vierra Magen/sandisk Corporation

20080137432 - Program time adjustment as function of program voltage for improved programming speed in memory system: In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080137431 - Starting program voltage shift with cycling of non-volatile memory: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period... Agent: Vierra Magen/sandisk Corporation

20080137412 - Flash memories with adaptive reference voltages: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of... Agent: Mark M. Friedman

20080137409 - Semiconductor memory device and method for erasing the same: A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137435 - Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has... Agent: Myers Bigel Sibley & Sajovec

20080137433 - Methods and apparatuses for trimming reference cells in semiconductor memory devices: A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a... Agent: Harness, Dickey & Pierce, P.L.C

20080137434 - Semiconductor memory device: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises... Agent: Mcdermott Will & Emery LLP

20080137436 - Programming method for non-volatile memory and non-volatile memory-based programmable logic device: A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a... Agent: Sierra Patent Group, Ltd.

20080137437 - Non-volatile memory embedded in a conventional logic process and methods for operating same: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080137438 - Non-volatile memory embedded in a conventional logic process and methods for operating same: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080137439 - Configurable inputs and outputs for memory stacking system and method: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal,... Agent: Fletcher Yoder (micron Technology, Inc.)

20080137440 - Sram cell with separate read and write ports: This invention discloses a dual port static random access memory (SRAM) cell, which comprises at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and an output terminals, at least one PMOS transistor with its gate, source and... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080137441 - Image processing apparatus capable of handling image file stored in another apparatus, image processing system, and image processing method: According to an image processing apparatus, if image data designated to be stored in a storage unit within the image processing apparatus is stored in a storage device outside the image processing apparatus, a memory remaining amount or the like of the image processing apparatus is calculated as if the... Agent: Morrison & Foerster LLP

20080137442 - Memory data reading circuit: A data read circuit for a memory without a complex pre-charge circuit is provided. A diode is coupled between a pair of bit lines to replace the pre-charge circuit. A voltage drop caused by the diode is substantially half the operating voltage of the memory.... Agent: Joe Mckinney Muncy

20080137443 - Multi-level nonvolatile semiconductor memory device and method for reading the same: A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array.... Agent: Volentine & Whitt Pllc

20080137445 - Apparatus and method of generating dbi signal in semiconductor integrated circuit: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry terminal, each of which receives data, performs an operation on the received data, and outputs a sum and a carry. A DBI determining unit determines a... Agent: Venable LLP

20080137446 - Semiconductor integrated circuit and relief method and test method of the same: A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a multi-bit structure, a plurality of comparison circuit which are connected to output sides of the respective memory circuits, and compare... Agent: Amin, Turocy & Calvin, LLP

20080137444 - Systems and methods for managing power: One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with... Agent: Texas Instruments Incorporated

20080137447 - Write circuit of memory device: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the... Agent: Mcdermott Will & Emery LLP

20080137448 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080137449 - Dynamic power control for expanding sram write margin: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080137450 - Apparatus and method for sram array power reduction through majority evaluation: A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.

20080137451 - Methods and apparatus for low power sram based on stored data: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted... Agent: Kaplan Gilman Gibson & Dernier L.l.p.

20080137452 - Nonvolatile memory system: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an... Agent: Miles & Stockbridge Pc

20080137453 - Data i/o control signal generating circuit in a semiconductor memory apparatus: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the... Agent: Baker & Mckenzie LLP Patent Department

20080137454 - Semiconductor memory device and method for repairing the same: A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that... Agent: Harness, Dickey & Pierce, P.L.C

20080137456 - Method of testing memory device: A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said... Agent: Katten Muchin Rosenman LLP

20080137455 - Storage cell design evaluation circuit including a wordline timing and cell access detection circuit: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.l.c.

20080137457 - Semiconductor memory device and control method thereof: A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines... Agent: Young & Thompson

20080137458 - Open digit line array architecture for a memory array: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20080137459 - Semiconductor memory device allowing high-speed data reading: Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory... Agent: Mcdermott Will & Emery LLP

20080137460 - Temperature compensation of memory signals using digital signals: A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature.... Agent: Leffert Jay & Polglaze, P.a.

20080137461 - Memory system and method with serial and parallel modes: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a... Agent: Smart & Biggar P.o. Box 2999, Station D

20080137462 - Two-bit per i/o line write data bus for ddr1 and ddr2 operating modes in a dram: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge... Agent: Hogan & Hartson LLP

20080137464 - Dynamic semiconductor memory with improved refresh mechanism: Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at... Agent: Townsend And Townsend And Crew, LLP

20080137463 - Semiconductor memory device: A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be... Agent: Sughrue Mion, Pllc

20080137465 - Semiconductor memory device: A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080137466 - Semiconductor memory: In a semiconductor memory having a plurality of word lines and bit lines and memory cells arranged at the positions of intersection thereof, a word driver circuit that drives the word line has a drive PMOS transistor and drive NMOS transistor which are connected in series between a first node... Agent: Arent Fox LLP

20080137467 - Apparatus and method for capturing serial input data: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080137469 - Circuit and method for selecting word line of semiconductor memory apparatus: A word line selecting circuit of a semiconductor memory apparatus having at least two memory areas and a plurality of word lines formed across the two memory areas is provided. The circuit includes: a decoder configured to decode an input address and configured to decode a word line corresponding to... Agent: Venable LLP

20080137468 - Circuit having relaxed setup time via reciprocal clock and data gating: An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second logic gates. The first logic gate has a first input coupled to the clock input, a second input... Agent: Dillon & Yudell LLP

20080137470 - Memory with data clock receiver and command/address clock receiver: One embodiment provides a memory device including a memory bank, a first receiver, and a second receiver. The memory bank includes memory cells. The first receiver is configured to receive a clock signal and provide a data clock signal based on the clock signal. The second receiver is configured to... Agent: Dicke, Billig & Czaja

20080137472 - Memory including first and second receivers: One embodiment provides a memory device including a first receiver and a second receiver. The first receiver is configured to receive a single ended clock signal and provide a first clock signal based on the single ended clock signal to provide a memory function. The second receiver is configured to... Agent: Dicke, Billig & Czaja

20080137471 - Memory with clock distribution options: One embodiment provides a memory including a first receiver, a second receiver, a circuit, a first buffer, and a second buffer. The first receiver is situated on one side of the memory and configured to receive a first clock signal and provide a first clock tree signal. The second receiver... Agent: Dicke, Billig & Czaja

20080130341 - Adaptive programming of analog memory: A part of the data is stored in the analog memory cells by programming at least a first group of the cells using the first nominal programming value. A statistical characteristic of the first group of the cells is measured after programming the first group of the cells using the... Agent: Darby & Darby P.c.

20080130342 - Hybrid-level three-dimensional memory: The present invention discloses a hybrid-level three-dimensional memory (HL-3DM). Some of its memory levels are separated, i.e. there is an inter-level dielectric between adjacent memory levels; while others are interleaved, i.e. adjacent memory levels share address-selection lines. The HL-3DM is particularly suitable for 3D-M with a large number of memory... Agent: Guobiao Zhang

20080130343 - Techniques for implementing accurate device parameters stored in a database: Memory modules and methods for fabricating and implementing memory modules wherein unique device parameters corresponding to specific memory devices on the memory modules are accessed from a database such that the device parameters may be implemented to improve system performance. The device parameters may include sizes, speeds, operating voltages, or... Agent: Fletcher Yoder (micron Technology, Inc.)

20080130344 - Semiconductor storage device: An excess region on a chip plane is eliminated to reduce a chip size. A plurality of data pads, which input/output data, are arranged near one side of an outer periphery of a substrate in parallel with the aforementioned one side, and a plurality of data pads, which input/output data,... Agent: Nixon Peabody, LLP

20080130345 - Semiconductor memory device: A semiconductor memory device comprising multiple memory cells, main bit lines, a sub-bit line, a differential amplifier circuit, a precharge circuit, a first control circuit generating first and second control signals, and a second control circuit generating third and fourth control signals, wherein the differential amplifier circuit amplifies the voltage... Agent: Dickinson Wright Pllc

20080130347 - Ferroelectric memory device and electronic equipment: A ferroelectric memory device, having: a first charge-transfer MISFET, connected between a first bit line and a first node; a second charge-transfer MISFET, connected between a second bit line and a second node; a first capacitance, connected to the first node; a second capacitance, connected to the second node; a... Agent: Harness, Dickey & Pierce, P.L.C

20080130346 - Ferroelectric nanostructure having switchable multi-stable vortex states: A ferroelectric nanostructure formed as a low dimensional nano-scale ferroelectric material having at least one vortex ring of polarization generating an ordered toroid moment switchable between multi-stable states. A stress-free ferroelectric nanodot under open-circuit-like electrical boundary conditions maintains such a vortex structure for their local dipoles when subject to a... Agent: Wright, Lindsey & Jennings LLP

20080130348 - Extraction of a binary code based on physical parameters of an integrated circuit: An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080130349 - Non-volatile memory device, method of manufacturing the same, and method of operating the same: A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable... Agent: Marger Johnson & Mccollom, P.c.

20080130350 - Dram with metal-layer capacitors: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a substrate including a plurality of access transistors, and a plurality of storage capacitors corresponding uniquely to the plurality of access transistors, each storage capacitor being formed in a plurality of semiconductor manufacturing process metal layers adjacent... Agent: Macpherson Kwok Chen & Heid LLP

20080130351 - Multi-bit resistive memory: A memory includes a first multi-bit resistive memory cell and a single bit resistive memory cell. The single bit resistive memory cell is for storing a bit indicating whether data stored in the first multi-bit resistive memory cell is inverted.... Agent: Dicke, Billig & Czaja

20080130353 - Resistive memory device: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access... Agent: Fletcher Yoder (micron Technology, Inc.)

20080130352 - Structure and method for biasing phase change memory array for reliable writing: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory... Agent: Patent Dept., Sandisk Corporation

20080130354 - Structure of magnetic random access memory using spin-torque transfer writing and method for manufacturing same: A nano-magnetic device includes a first hard magnet having a first magnetization direction and having a central axis. The device also includes a second hard magnet separated from the first hard magnet by a dielectric liner. The second hard magnet has a second magnetization direction opposite to the first magnetization... Agent: Akin Gump LLP - Silicon Valley

20080130355 - Magneto-resistance effect element and magnetic memory device: A magneto-resistance effect element is formed by including at least: a magnet wire 1 for forming magnetic domain wall potential 7 binding a single magnetic domain wall 2; a magnetic field applying means for generating a magnetic field for introducing the single magnetic domain wall 2 into the magnet wire... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080130356 - Memory device: A memory device, and associated methods of manufacture and operation are described. The memory device includes at least one memory unit comprising a substrate (120) supporting mobile charge carriers. Insulative features (130, 132, 134) formed on the substrate surface define first and second substrate areas (122, 124) on either side... Agent: Morrison & Foerster LLP

20080130357 - Method of programming memory device: In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across... Agent: Paul J. Winters

20080130358 - Semiconductor memory device having floating body cell: According to the semiconductor memory device of the embodiment, in the sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080130359 - Multiple use memory chip: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.... Agent: Empk & Shiloh, LLP

20080130360 - Flash memory program inhibit scheme: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080130364 - Novel multi-state memory: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080130365 - Bitline selection circuitry for nonvolatile memories: Interleaving even and odd bit lines in combination with alternating selection and discharge of banks reduces a cross coupling voltage. A discharge delay ensures that a sense amplifier does not detect any signal during a discharge phase. The discharge delay is much shorter than the cross coupling delay required with... Agent: Schneck & Schneck

20080130367 - Byte-erasable nonvolatile memory devices: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor... Agent: Myers Bigel Sibley & Sajovec

20080130366 - Memory cell, erasing method of information recorded in the memory cell, and nonvolatile semiconductor memory device comprising the memory cell: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor comprising two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and... Agent: Morrison & Foerster LLP

20080130368 - Starting program voltage shift with cycling of non-volatile memory: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period... Agent: Vierra Magen/sandisk Corporation

20080130361 - Circuit and method for generating a reference voltage in memory devices having a non-volatile cell matrix: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage... Agent: Seed Intellectual Property Law Group Pllc

20080130362 - Method for reducing charge loss in analog floating gate cell: A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080130363 - Semiconductor memory device and method for erasing the same: A semiconductor memory device includes NAND cell units each having memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit and dummy cells disposed between the select gate transistors and the memory cells neighbored to them. The dummy cells are set in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080130369 - Semiconductor memory device: The invention provides a semiconductor memory device which realizes high speed reading by automatically adjusting and optimizing charge and discharge timings even when a change in an operation environment such as a variation in an operation voltage, an operation temperature, a process parameter and so on occurs. First and second... Agent: Morrison & Foerster LLP

20080130370 - Method for increasing programming speed for non-volatile memory by applying direct-transitioning waveforms to word lines: Non-volatile storage elements are programmed using counter-transitioning waveform portions on neighboring word lines which reduce capacitive coupling to a selected word line. In one approach, the waveform portions extend between pass or isolation voltages of a boosting mode, which are applied during a programming pulse on the selected word line,... Agent: Vierra Magen/sandisk Corporation

20080130371 - Method and apparatus for high voltage operation for a high performance semiconductor memory device: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous... Agent: Ingrassia Fisher & Lorenz, P.c.

20080130373 - Programming memory devices: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory... Agent: Leffert Jay & Polglaze, P.a. Attn: Tod A. Myrum

20080130372 - Trench memory structures and operation: Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over... Agent: Leffert Jay & Polglaze, P.a. Attn: Thomas W. Leffert

20080130374 - Semiconductor memory device: The invention provides a semiconductor memory device where a circuit area is minimized and a voltage drop in a high voltage supply path to a source line is reduced. An output of a high voltage generation circuit is connected to a source line through a first transfer gate, and connected... Agent: Morrison & Foerster LLP

20080130375 - High speed, leakage tolerant, double bootstrapped multiplexer circuit with high voltage isolation: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and... Agent: Daffer Mcdaniel, LLP M/s: 5298

20080130377 - Circuit and method for calibrating data control signal: A circuit for calibrating a data control signal comprises a time-delay compensation circuit and a voltage-control delay circuit. The time-delay compensation circuit receives two complementary signals and a direct current voltage which has two voltage cross points with the two complementary signals respectively, and outputs a control voltage according to... Agent: Lowe Hauptman Ham & Berner, LLP

20080130376 - Semiconductor memory device including floating body memory cells and method of operating the same: A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source line to store data. A controller applies a first voltage to the common source line, a negative second... Agent: Volentine & Whitt Pllc

20080130378 - Memory device and method for performing write operations in such a memory device: A memory device and method of performing a write operation in such a memory device are provided. The memory device comprises a memory array having a plurality of memory cells, and a plurality of word lines and a plurality of bit lines via which the plurality of memory cells are... Agent: Nixon & Vanderhye, Pc

20080130379 - Semiconductor memory device: This disclosure concerns a memory comprising a memory cell including a floating body provided between a source and a drain and storing therein data according to number of majority carriers accumulated in the floating body; a word line connected to a gate of the memory cell; a bit line connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080130381 - Methods of programming and erasing resistive memory devices: In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing),... Agent: Paul J. Winters

20080130380 - Single-port sram with improved read and write margins: The present invention relates generally to an integrated circuit (IC) design, and more particularly to a method and apparatus for providing an SRAM cell with improved read and write margins. The method includes providing a first negative voltage to a bit-line and a supply voltage to an inverse bit-line to... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080130382 - Write circuit of memory device: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the... Agent: Mcdermott Will & Emery LLP

20080130383 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080130384 - Delay locked loop circuit: A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a... Agent: Mcdermott Will & Emery LLP

20080130386 - Circuit and method for testing multi-device systems: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system,... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080130385 - Method and system for in-situ parametric sram diagnosis: This invention is about a system for diagnosing memory cells in a memory module. A first multiplexer module selectively connects a diagnosis signal in response to a multiplexer control signal to a data line associated with a predetermined memory cell. A second multiplexer module connects the data line to the... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080130387 - Method for evaluating memory cell performance: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.l.c.

20080130388 - Semiconductor device having a system in package structure and method of testing the same: A memory chip and an integrated circuit chip are electrically connected via a plurality of bonding wires, and thereby, a semiconductor device is assembled as a SIP product. A test circuit required for testing the memory chip is built in the memory chip only, and the integrated circuit chip is... Agent: Amin, Turocy & Calvin, LLP

20080130389 - Semiconductor storage apparatus: A cell array selection circuit, a cell array bit line precharge circuit, and a sense amplifier bit line precharge circuit are provided in a semiconductor storage apparatus. In a standby state of read/write operation, the cell array selection circuit is controlled to an inactive state, and the bit line precharge... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080130390 - Semiconductor storage apparatus: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or... Agent: Mcginn Intellectual Property Law Group, Pllc

20080130391 - Ram with trim capacitors: In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell... Agent: Macpherson Kwok Chen & Heid LLP

20080130392 - Method of erasing a resistive memory device: In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive... Agent: Paul J. Winters

20080130393 - Semiconductor memory and electronic device: A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control... Agent: Arent Fox LLP

20080130394 - Semiconductor memory device: A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode,... Agent: Mcginn Intellectual Property Law Group, Pllc

20080130395 - Self-identifying stacked die semiconductor components: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.l.p.

20080130396 - Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods: A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was received first. In response, the phase decision circuit generates respective... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080130397 - Semiconductor memory device having low jitter source synchronous interface and clocking method thereof: Provided are a semiconductor memory device having a source synchronous interface capable of reducing jitter while minimizing overhead and a clocking method thereof. The semiconductor memory device comprises a phase locked loop (PLL) circuit receiving a first external clock signal for a command and address signal and generating a first... Agent: Marger Johnson & Mccollom, P.c.