Static information storage and retrieval inventions 05/08

20080123384 - Select transistor using buried bit line from core: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory... Agent: Harrity & Snyder, L.L.P.

20080123385 - Interconnecting bit lines in memory devices for multiplexing: Methods and apparatus are provided. A plurality of conductive plugs are formed on a semiconductor substrate, and first and second bit lines are formed overlying the conductive plugs so that a pair of successively adjacent first and second bit lines are in contact with each of the conductive plugs.... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20080123386 - Semiconductor memory device having improved voltage transmission path and driving method thereof: Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the... Agent: Marger Johnson & Mccollom, P.C.

20080123387 - Semiconductor memory device having replica circuit: A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the column direction. The row decoder is connected to the... Agent: Amin, Turocy & Calvin, LLP

20080123388 - Methods and systems for read-only memory: One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memory cell also... Agent: Texas Instruments Incorporated

20080123391 - Memory system and resistive memory device including buffer memory for reduced overhead: A resistive memory device includes a memory core unit and a buffer memory for reducing overhead of a memory controller in a memory system. The buffer memory stores input data associated with a write command. The memory core unit includes resistive memory cells for storing the input data from the... Agent: Law Office Of Monica H Choi

20080123389 - Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance... Agent: Volentine & Whitt PLLC

20080123390 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage... Agent: Harness, Dickey & Pierce, P.L.C

20080123394 - Nonvolatile memory devices using variable resistors as storage elements and methods of operating the same: A nonvolatile memory device includes a first electrode and a second electrode, and a variable resistor interposed between the first and second electrodes. The variable resistor has a critical voltage, and a resistance-voltage characteristic of the variable resistor is switched at a voltage higher than the critical voltage, so that... Agent: Myers Bigel Sibley & Sajovec

20080123392 - Nonvolatile semiconductor memory device and method of writing into the same: In a method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, a variable resistor is parallelly... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080123393 - Nonvolatile semiconductor memory device and method of writing into the same: A method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, includes the step of applying the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080123395 - Nonvolatile memory device and control method thereof: To provide a nonvolatile memory including a word-line drive circuit that supplies a selective voltage to a selective transistor connected in series to a nonvolatile memory device. The word-line drive circuit applies a first selective voltage VDD to a control electrode of the selective transistor in a first period, and... Agent: Sughrue Mion, PLLC

20080123397 - Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication: A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer... Agent: Dickstein Shapiro LLP

20080123400 - Integrated circuit including circuitry to perform write and erase operations: An integrated circuit including circuitry configured to perform erase and write functions. One embodiment includes a programmable metallization memory cell, a conductive line connected to a first node of the memory cell, and a bitline connected to a second node of the memory cell. The memory device also includes circuitry... Agent: Dicke, Billig & Czaja

20080123398 - Memory cell with trigger element: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.... Agent: Eschweiler & Associates LLC

20080123399 - Non-volatile memory devices, method of manufacturing and method of operating the same: A non-volatile memory device includes a substrate having a recess thereon, a resistant material layer pattern in the recess, a lower electrode on the resistant material layer pattern in the recess, a dielectric layer, and an upper electrode formed on the dielectric layer. The resistant material layer pattern includes a... Agent: Myers Bigel Sibley & Sajovec

20080123396 - Semiconductor device and driving method of the same: The invention provides a semiconductor device including a memory of a simple structure to provide an inexpensive semiconductor device and a driving method thereof. The semiconductor device of the invention includes a phase change memory including a memory cell array having a plurality of memory cells, a control circuit that... Agent: Eric Robinson

20080123401 - Damascene metal-insulator-metal (mim) device with improved scaleability: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing... Agent: Paul J. Winters

20080123402 - Method for programming a flash memory device: A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass... Agent: Townsend And Townsend And Crew, LLP

20080123414 - Alternate sensing techniques for non-volatile memories: The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080123406 - Dynamic program and read adjustment for multi-level cell memory array: A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080123405 - Implanted multi-bit nand rom: The market for re-programmable Non-Volatile Memory is growing very fast with the storage of pictures, movies and games. The current NAND technology for mass storage is still limited by density limitations and cost. The volume storage market is composed of applications that require re-programmability and those that are one time... Agent: Mammen Thomas

20080123412 - Method of managing a multi-bit-cell flash memory: A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value.... Agent: Mark M. Friedman

20080123407 - Method of programming a nand flash memory device: A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided... Agent: Townsend And Townsend And Crew, LLP

20080123413 - Multiple use memory chip: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.... Agent: Empk & Shiloh, LLP

20080123408 - Non-volatile semiconductor storage system: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080123411 - Page buffer for multi-level nand electrically-programmable semiconductor memories: A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080123410 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080123409 - Semiconductor memory device and test method thereof: A semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, wherein the device has such a test mode that includes a page searching sequence for searching a fast page with the fastest write speed in the memory cell array.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080123415 - Low voltage column decoder sharing a memory array p-well: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and... Agent: Schwegman, Lundberg & Woessner / Atmel

20080123416 - Program and erase methods and structures for byte-alterable flash memory: An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a... Agent: Slater & Matsil, L.L.P.

20080123417 - Semiconductor device including a high voltage generation circuit and method of a generating high voltage: A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The... Agent: Volentine & Whitt PLLC

20080123418 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the... Agent: Law Office Of Alan W. Cannon

20080123421 - Memory architecture for separation of code and data in a memory device: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.... Agent: Intel Corporation C/o Intellevate, LLC

20080123419 - Methods of varying read threshold voltage in nonvolatile memory: Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges... Agent: Winston & Strawn, LLP

20080123420 - Nonvolatile memory with variable read threshold: Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges... Agent: Winston & Strawn, LLP

20080123422 - Non-volatile memory devices capable of reading data during multi-sector erase operation, and data read methods thereof: The data read method for a non-volatile memory device includes a multi-sector erase operation and a Read While Write (RWW) operation. In the multi-sector erase operation, a plurality of sectors, which are to be erased, are sequentially erased. In the RWW operation, if a read command instructing reading of a... Agent: Myers Bigel Sibley & Sajovec

20080123423 - Non-volatile memory serial core architecture: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080123424 - Non-volatile semiconductor memory device: The local row decoder includes a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and a second MOS transistor of a second conductivity type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080123426 - Non-volatile memory using multiple boosting modes for reduced program disturb: A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode.... Agent: Vierra Magen/sandisk Corporation

20080123425 - Reducing program disturb in non-volatile memory using multiple boosting modes: A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to... Agent: Vierra Magen/sandisk Corporation

20080123403 - Method and apparatus for trimming reference voltage of flash memory device: The present invention relates to a method and apparatus for trimming a reference voltage. The method may include at least one steep of performing an erase operation of a flash memory resistor; performing a program operation of the flash memory resistor; performing a current read operation of the flash memory... Agent: Sherr & Nourse, PLLC

20080123404 - Reading voltage generator for a non-volatile eeprom memory cell matrix of a semiconductor device and corresponding manufacturing process: A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate... Agent: Seed Intellectual Property Law Group PLLC

20080123427 - Flash memory, program circuit and program method thereof: A program circuit and method for a flash memory is provided. This invention utilizes a constant current to program the flash memory and modulate the threshold voltage of the flash memory. While a program circuit programming the flash memory, the present invention determines whether the threshold voltage reaches the anticipated... Agent: J C Patents, Inc.

20080123429 - Program method of flash memory device: The present invention relates to a method of programming a flash memory device. According to the present invention, after a program operation is completed, a program verify operation is repeatedly performed, wherein a threshold voltage of a programmed memory cell is also detected. If there are memory cells whose threshold... Agent: Townsend And Townsend And Crew, LLP

20080123428 - Semiconductor memory device and method of verifying the same: Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the... Agent: Harness, Dickey & Pierce, P.L.C

20080123431 - Flash memory device and programming method of flash memory device: A flash memory device and a method of programming a flash memory device include selecting bit lines connected to program cells of multiple memory cells coupled to a selected word line. The selected bit lines are driven to a bit line program voltage through a write driver circuit connected to... Agent: Volentine & Whitt PLLC

20080123430 - Non-volatile memory unit and array: A memory unit comprising a gate electrode, a gate dielectric under said gate electrode, an active area and a metal-semiconductor compound layer is provided. The active area comprises a first source/drain region, a second source/drain region, a normal field channel region formed under said gate electrode, a fringing field channel... Agent: Birch Stewart Kolasch & Birch

20080123432 - Flash memory device and method of reading data from flash memory device: A method of reading data from a flash memory device that includes a multiple block memory cell array, each block having a cell string connected to a bit line and comprising a string select transistor connected to a string select line, a memory cell connected to a wordline and a... Agent: Volentine & Whitt PLLC

20080123433 - Flash memory device and method of manufacturing the same: A flash memory device is disclosed. The flash memory device includes a substrate, a memory cell transistor and a selection transistor. The substrate has a first region where the memory cell transistor is to be formed and a second region where the selection transistor is to be formed. The first... Agent: Marger Johnson & Mccollom, P.C.

20080123434 - Erase discharge control method of nonvolatile semiconductor memory device: According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well... Agent: Harness, Dickey & Pierce, P.L.C

20080123436 - Non-volatile memory device and erasing method thereof: In one aspect, a non-volatile NAND-flash semiconductor memory device is provided which is configured to execute at least one of a pre-program operation and a post-program operation before and after an erase operation, respectively. Each of the pre-program and post-program operations includes applying a program voltage to a subset of... Agent: Volentine & Whitt PLLC

20080123435 - Operation of nonvolatile memory having modified channel region interface: The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080123439 - Semiconductor integrated circuit and method of operating the same: One embodiment includes a plurality of word lines, a plurality of source lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines. Each of the plurality... Agent: Harness, Dickey & Pierce, P.L.C

20080123437 - Apparatus for floating bitlines in static random access memory arrays: An apparatus for floating read bitlines of a static random access memory (SRAM) is disclosed. The SRAM includes a first and second SRAM cell columns, a first and second read bitlines, and a multiplexor. The multiplexor is coupled to the first and second SRAM cell columns via the first and... Agent: Dillon & Yudell LLP

20080123438 - Evaluation unit in an integrated circuit: An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080123440 - Memory controller and output signal driving circuit thereof: A memory controller for controlling a memory, where the memory controller includes: a pad, coupled to the memory, for generating an output signal to the memory according to a signal value of the memory controller; a voltage pull-up device, coupled to the pad, comprising a first N type transistor and... Agent: North America Intellectual Property Corporation

20080123442 - Method to improve performance of sram cells, sram cell, sram array, and write circuit: A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit.... Agent: International Business Machines Corporation Dept. 18g

20080123441 - Reducing the format time for bit alterable memories: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.... Agent: Trop Pruner & Hu, PC

20080123443 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: an internal command signal generator for receiving an external command signal and a command strobe signal from a chipset to generate an internal command signal by decoding the external command signal in response to the command strobe signal; and a plurality of operation circuits for... Agent: Mcdermott Will & Emery LLP

20080123444 - Adaptive memory calibration using bins: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and... Agent: Qualcomm Incorporated

20080123445 - Circuits to delay a signal from ddr-sdram memory device including an automatic phase error correction: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an... Agent: Sierra Patent Group, Ltd.

20080123446 - Randomizing current consumption in memory devices: In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory... Agent: Fish & Richardson P.C.

20080123447 - Dram concurrent writing and sensing scheme: This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080123450 - Memories with front end precharge: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080123451 - Memories with selective precharge: Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a subset of memory cells, where the subset of memory cells contains fewer memory cells than the device as a whole and where... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080123448 - Memory device architecture and method for high-speed bitline pre-charging: A memory device is presented that includes a plurality of memory cells coupled to a bitline, and two or more pre-charging circuits coupled to the bitline. Each of the pre-charging circuits is operable to supply a pre-charge voltage to the bitline, thereby reducing the effective R-C time constant of the... Agent: Slater & Matsil LLP

20080123452 - Semiconductor memory device including a write recovery time control circuit: A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The... Agent: Harness, Dickey & Pierce, P.L.C

20080123449 - Systems and methods for reading data from a memory array: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by... Agent: Texas Instruments Incorporated

20080123453 - Circuit and method for controlling sense amplifier of a semiconductor memory apparatus: A sense amplifier control unit include: a control unit that detects a variation in the level of an external voltage and outputs a delay time selection signal on the basis of the result of the detection. A variable delay unit delays an active signal by a delay time corresponding to... Agent: Venable LLP

20080123454 - Circuit and methods for eliminating skew between signals in semiconductor integrated circuit: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data... Agent: Volentine & Whitt PLLC

20080123455 - Sense amplifier of semiconductor memory device: A sense amplifier of a semiconductor device is disclosed. The sense amplifier includes first and second PMOS transistors connected to each other at sources of the first and second PMOS transistors, and first and second NMOS transistors connected to each other at sources of the first and second NMOS transistors,... Agent: Cooper & Dunham, LLP

20080123456 - Semiconductor memory device suitable for mounting on portable terminal: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal,... Agent: Buchanan, Ingersoll & Rooney PC

20080123457 - Power supply circuit for sense amplifier of semiconductor memory device: A power supply circuit for a sense amplifier of a semiconductor memory device is disclosed. The power supply circuit includes a control signal generator for generating a control signal which is activated upon a write operation, a multiplexer for selecting and outputting one of a first reference voltage and a... Agent: Cooper & Dunham, LLP

20080123459 - Combined signal delay and power saving system and method for use with a plurality of memory circuits: A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.... Agent: Zilka-kotab, PC- Mrm1

20080123460 - Deep power down mode control circuit: A deep power down mode control circuit is disclosed. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for... Agent: Cooper & Dunham, LLP

20080123458 - Virtual power rails for integrated circuits: Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails,... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080123461 - Semiconductor memory device including a column decoder array: A semiconductor memory device is presented that exhibits an enhanced read/write data retrieval efficiency brought about in part by a uniquely shared column array communication scheme. The semiconductor memory device includes: at least one group of banks, the banks being disposed adjacent to each other to form a radially symmetrical... Agent: Ladas & Parry LLP

20080123462 - Multiple-port sram device: A multiple-port SRAM cell includes a latch having a first node and a second node for retaining a value and its complement, respectively. The cell has a write port separate from a read port for parallel operation. A number of transistors are used to connect the first and second nodes... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080123463 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word... Agent: Foley And Lardner LLP Suite 500

20080117659 - Semiconductor memory device: There is provided a semiconductor memory device which offers enhanced speed in burst mode. The semiconductor memory device has a burst mode for serially reading multiple bits of data in a fixed order in synchronization with both edges of a clock. Multiple memory blocks are geometrically arranged correspondingly to the... Agent: Miles & Stockbridge Pc

20080117660 - Method, apparatus and system providing a one-time programmable memory device: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.... Agent: Dickstein Shapiro LLP

20080117661 - Method, apparatus and system providing memory cells associated with a pixel array: A method, apparatus, and system are disclosed providing an imaging device with memory cells containing anti-fuse elements located with or outside a pixel array. The memory cells are read out using control signal lines which are used to readout imaging pixels.... Agent: Dickstein Shapiro LLP

20080117662 - Photon-based memory device and method thereof: A memory device includes a bit cell including an adjustable transmittance component having a first side and a second side. The adjustable transmittance component has an adjustable transmittance state representative of a bit value of the bit cell. The memory device further includes a photon detector optically coupled to a... Agent: Larson Newman Abel Polansky & White, LLP

20080117663 - Resistive memory including refresh operation: A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.... Agent: Dicke, Billig & Czaja

20080117664 - Resistance memory element and nonvolatile semiconductor memory: A resistance memory element, which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, includes a pair of electrodes and a resistance memory layer sandwiched between the pair of electrodes and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080117666 - Memory with increased write margin bitcells: A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to... Agent: Freescale Semiconductor, Inc. Law Department

20080117665 - Two-port sram having improved write operation: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the... Agent: Freescale Semiconductor, Inc. Law Department

20080117669 - Memory readout circuit and phase-change memory device: In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold... Agent: Young & Thompson

20080117668 - Phase change memory device having a uniform set and reset current: A phase change memory device having a uniform set and reset current includes a first and second sense amplifiers that are respectively placed adjacent to both ends of a plurality of active regions. The active regions include a first active region and a second active region. The first active region... Agent: Ladas & Parry LLP

20080117667 - Resistive memory including bipolar transistor access devices: A memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor and the first bit line. The memory includes a second bit line, a second resistive memory element coupled between an emitter of the first... Agent: Dicke, Billig & Czaja

20080117670 - Thin film magnetic memory device including memory cells having a magnetic tunnel junction: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, to which a data read current is supplied. In the selected memory cell column, a read gate drives the respective voltages on a read... Agent: Mcdermott Will & Emery LLP

20080117671 - Memory devices using carbon nanotube (cnt) technologies: Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions,... Agent: Schmeiser, Olsen & Watts

20080117673 - Gated diode nonvolatile memory operation: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080117672 - Gated diode nonvolatile memory structure with diffusion barrier structure: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080117675 - Reducing read disturb in non-volatile multiple- level cell memories: The supply voltage to a selected cell may be turned off after sensing. In one embodiment, this may be done by providing the output of the sense amplifier through a control circuit to simply turn off the voltage to the selected column or bitline. This may reduce the drain disturb... Agent: Trop Pruner & Hu, Pc

20080117677 - Vertical nonvolatile memory cell, array, and operation: A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080117678 - Memory with a core-based virtual ground and dynamic reference sensing scheme: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the... Agent: Amin, Turocy & Calvin, LLP

20080117679 - Securing a flash memory block in a secure device system and method: A technique for securing a flash memory block in a secure device system involves cryptographic techniques including the generation of a Message Authentication Code (MAC). The MAC may be generated each time a file is saved to one or more data blocks of a flash memory device and stored with... Agent: Perkins Coie LLP

20080117680 - Non-volatile memory and semiconductor device: There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080117681 - Detection and correction of defects in semiconductor memories: A non-volatile memory may have memory portions, such as blocks or other granularities of units of memory, which may fail in actual use. These defective portions can be replaced with other portions which may, in some cases, be of corresponding size. In some embodiments, defects may be detected using a... Agent: Trop Pruner & Hu, Pc

20080117682 - Multi-chip package flash memory device and method for reading status data therefrom: A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of memory chips through multiple channels... Agent: Harness, Dickey & Pierce, P.L.C

20080117683 - Controlled boosting in non-volatile memory soft programming: A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The... Agent: Vierra Magen/sandisk Corporation

20080117684 - Systems for controlled boosting in non-volatile memory soft programming: A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The... Agent: Vierra Magen/sandisk Corporation

20080117674 - Flash memory device and smart card including the same: A flash memory device includes an array having memory cells arranged in rows and columns. A high voltage generator is configured to supply a high voltage to the array during a programming operation. Write buffers corresponding to selected memory cells drive the selected memory cells with a program voltage or... Agent: F. Chau & Associates, Llc

20080117685 - Memory device with retained indicator of read reference level: A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference... Agent: Larson Newman Abel Polansky & White, LLP

20080117686 - Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices: A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080117687 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory for setting control voltages to be supplied to an internal circuit, to an external reference voltage inputted from outside, has a parameter control circuit. The parameter control circuit causes a parameter register to sequentially output the plurality of parameters to a voltage generating control circuit. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080117688 - Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower... Agent: Myers Bigel Sibley & Sajovec

20080117689 - Flash memory device with improved program performance and smart card including the same: A flash memory device including; a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the... Agent: F. Chau & Associates, Llc

20080117690 - Method and apparatus for operating nonvolatile memory with floating voltage at one of the source and drain regions: Methods and apparatuses are discussed which operate a nonvolatile memory cell or at least one cell in an array of such cells, such that a drain region or a source region is floating while adding charge to the charge storage structure.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080117676 - Method for preventing memory from generating leakage current and memory thereof: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell... Agent: Rabin & Berdo, Pc

20080117691 - Erasing circuit of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device allowing a chip area to be small without complicating the control of erasing process and providing a boundary region for insulating each memory cell block electrically, comprises a memory cell array formed in a well region of a second conductivity type on a semiconductor substrate... Agent: Morrison & Foerster LLP

20080117692 - Semiconductor memory device having the operating voltage of the memory cell controlled: An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080117693 - Data reading circuit: Disclosed is a data reading circuit, including: a first register, for receiving a first data signal and generating a second data signal by sampling the first data signal via the first edge of a first predetermined signal; a second register, for sampling a second data signal by the second edge... Agent: North America Intellectual Property Corporation

20080117694 - Semiconductor device and semiconductor chips: High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data... Agent: Mcginn Intellectual Property Law Group, Pllc

20080117695 - Delay mechanism for unbalanced read/write paths in domino sram arrays: A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory... Agent: Ibm Corporation Rochester Ip Law Dept. 917

20080117696 - Method for repairing defects in memory and related memory system: A method for repairing defects in a memory is disclosed. The method includes: performing a defect test on the memory to obtain at least one defect address of the memory, storing the at least one defect address into a storage media, storing the at least one defect address stored in... Agent: North America Intellectual Property Corporation

20080117697 - System that prevents reduction in data retention: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the... Agent: Dicke, Billig & Czaja

20080117698 - Circuit and method for a high speed dynamic ram: An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the associated sense amplifier to the global bit lines using a circuit optimized for high speed operation. The... Agent: Slater & Matsil, L.l.p.

20080117700 - Dynamic semiconductor storage device and method for operating same: The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and... Agent: Michael J. Le Strange International Business Machines Corporation

20080117699 - Semiconductor memory device having a control unit receiving a sensing block selection address signal and related method: Embodiments of the invention provide a semiconductor memory device and a method for operating the semiconductor memory device. The invention provides a semiconductor memory device comprising a memory cell array block comprising a plurality of first memory cells connected to a plurality of first bit lines and a plurality of... Agent: Volentine & Whitt Pllc

20080117701 - Method for compensated sensing in non-volatile memory: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080117702 - Integrated circuit having a memory with process-voltage-temperature control: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response... Agent: Mendelsohn & Associates, P.c.

20080117703 - Memory structure, programming method and reading method therefor, and memory control circuit thereof: The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates... Agent: Rabin & Berdo, Pc

20080117704 - Resistive memory including selective refresh operation: A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.... Agent: Dicke, Billig & Czaja

20080117705 - Flash memory device and method of testing a flash memory device: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second... Agent: Volentine & Whitt Pllc

20080117706 - Semiconductor device: A semiconductor device reduces a number of boost voltage pumps by controlling an operation of the boost voltage pumps in accordance with the number of activated memory banks, thereby reducing an area which the boost voltage pumps occupy in a memory. The semiconductor device includes memory banks, a boost voltage... Agent: Lowe Hauptman Ham & Berner, LLP

20080117709 - Delay mechanism for unbalanced read/write paths in domino sram arrays: A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines, and design structure therefor. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow... Agent: Ibm Corporation Rochester Ip Law Dept. 917

20080117710 - Look-up table cascade circuit, look-up table cascade array circuit and a pipeline control method thereof: A look-up table cascade circuit having N look-up tables connected in cascade for implementing a desired logic function, comprising: N memory cell arrays for storing data of the look-up table in memory cells; N input select circuits for selecting a word line and bit lines to specify memory cells based... Agent: Sughrue Mion, Pllc

20080117708 - Memory array with bit lines countering leakage: Bit lines in a memory array are configured by a select switch matrix to apply the same VD voltage to two adjacent bit lines on the drain side of a selected memory cell for the purpose of blocking charge leakage through the cell adjacent to the selected or addressed cell.... Agent: Schneck & Schneck

20080117707 - Memory device having concurrent write and read cycles and method thereof: A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell comprising a storage component, and a write... Agent: Larson Newman Abel Polansky & White, LLP

20080112203 - Power line layout: A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines... Agent: Lee & Morse, P.c.

20080112205 - Circuit and method for patching for program rom: This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080112204 - Circuit configurations and methods for manufacturing five-volt one time programmable (otp) memory arrays: This invention discloses a circuit trimming system that includes a one-time programmable memory (OTP). The OTP further includes a forward biased trim device connected between a voltage supply Vcc and a ground voltage wherein the Vcc having a reduced voltage substantially lower than a trimming voltage for a reversed biased... Agent: Bo-in Lin

20080112206 - Method of selecting operating characteristics of a resistive memory device: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device... Agent: Paul J. Winters

20080112210 - Semiconductor memory device: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow... Agent: Mcdermott Will & Emery LLP

20080112208 - Semiconductor memory device and method for biasing dummy line therefor: A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of... Agent: F. Chau & Associates, Llc

20080112209 - Semiconductor memory device having a three-dimensional cell array structure: A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines... Agent: Myers Bigel Sibley & Sajovec

20080112207 - Solid electrolyte memory device: A solid electrolyte memory device includes at least one solid electrolyte memory cell, each of which including a reactive electrode, an inert electrode, and solid electrolyte positioned between the reactive electrode and the inert electrode, and at least one charge storing unit storing an electric charge, the at least one... Agent: Slater & Matsil LLP

20080112211 - Phase changing memory device: A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080112212 - Circuits for improving read and write margins in multi-port srams: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at... Agent: Howard Chen, Esq., Preston Gates & Ellis LLP

20080112213 - Novel word-line driver design for pseudo two-port memories: This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080112214 - Electronic assembly having magnetic tunnel junction voltage sensors and method for forming the same: A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies.... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080112216 - Magnetic memory device: There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a first direction, takes a low-resistance-state having a resistance value lower than that in the high-resistance-state when receiving a write current in a second direction opposite to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080112215 - Storage element and memory: A storage element and memory are provided. The storage element includes a storage layer that stores information based on a magnetic state of a magnetic material; and a fixed magnetization layer a magnetization direction of which is fixed and which is provided for the storage layer with a nonmagnetic layer... Agent: Bell, Boyd & Lloyd, LLP

20080112217 - Read window in chalcogenide semiconductor memories: Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb where a bit unintentionally changes phase.... Agent: Trop Pruner & Hu, Pc

20080112218 - Semiconductor memory device and write control method thereof: A semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory elements arranged at intersecting points between the word lines and the bit lines, respectively, a row selector selectively activating the word lines, a plurality of write drivers provided to correspond to... Agent: Sughrue Mion, Pllc

20080112219 - Method and enhanced sram redundancy circuit for reducing wiring and required number of redundant elements: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements, and a design structure on which the subject SRAM redundancy circuit resides is provided. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080112221 - Multi-bit flash memory device including memory cells storing different numbers of bits: A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operations of the memory cells. A control logic unit... Agent: Volentine & Whitt Pllc

20080112222 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory chip configured to be electrically rewritable and store such multi-level data as being defined by n-bits/cell (where n≧2); and a memory controller configured to control read and write of the memory chip, wherein the operation mode of the memory chip is changed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080112223 - Method and apparatus for collecting data related to the status of an electrical power system: A method and an apparatus for collecting data related to a status of an electrical power system, wherein data is continuously acquired from the electrical power system and is stored, at least temporarily, in a first volatile memory. Upon the occurrence of an event, the data stored in the first... Agent: Abb Inc. Legal Dept. - 4u6

20080112224 - Mini flash disk with data security function: A mini flash disk with data security function conforms to the hard disk specification of the Technical Committee T13 that describes the width of shell is 2.5 inches or 1.8 inches. The shell of the mini flash disk comprises a control chipset for connecting with the external connecting port, a... Agent: Rosenberg, Klein & Lee

20080112225 - Modified-layer eprom cell: An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal layer, and a control gate, including a second metal layer. The floating gate is disposed adjacent to the source and drain regions and separated... Agent: Hewlett Packard Company

20080112227 - Non-volatile memory device and programming, reading and erasing methods thereof: A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings. Each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory... Agent: Volentine & Whitt Pllc

20080112226 - Non-volatile memory with boost structures: A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost... Agent: Vierra Magen/sandisk Corporation

20080112228 - Non-planar flash memory array with shielded floating gates on silicon mesas: A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions.... Agent: Leffert Jay & Polglaze, P.a. Att: Kenneth W. Bolvin

20080112220 - Input circuit of a non-volatile semiconductor memory device: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or... Agent: Harness, Dickey & Pierce, P.L.C

20080112229 - Sense amplifiers including multiple precharge circuits and associated memory devices and sensing methods: A sense amplifier of a flash memory device maintains a bit line precharge level before a memory cell is sensed. The sense amplifier maintains the voltage of a bias signal sufficiently high using a second precharging circuit in a precharging operation to stably maintain the bit line precharge level set... Agent: Myers Bigel Sibley & Sajovec

20080112230 - Operating non-volatile memory with boost structures: A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or... Agent: Vierra Magen/sandisk Corporation

20080112231 - Semiconductor devices and methods of manufacture thereof: A method of operating a memory array includes providing an array of memory cells arranged in rows and columns. Each column comprises a NAND unit cell including a plurality of memory cells coupled together serially. The plurality of memory cells of each NAND unit cell share a common well. The... Agent: Slater & Matsil LLP

20080112232 - Method and apparatus for fast programming of nonvolatile memory: Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080112233 - On-die termination circuit for semiconductor memory devices: An ODT circuit performs termination control on at least one pair of differential mode signals within a memory chip. The ODT circuit may include a switching unit. The switching unit may include a plurality of switching blocks. The switching blocks may include termination resistance devices connected in parallel between first... Agent: Harness, Dickey & Pierce, P.L.C

20080112234 - Methods and apparatus for low power sram using evaluation circuit: Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global... Agent: Kaplan Gilman Gibson & Dernier L.l.p.

20080112235 - Control signal training: A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080112236 - Systems and methods for improving memory reliability by selectively enabling word line signals: Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment... Agent: Law Offices Of Mark L. Berrier

20080112238 - Hybrid flash memory device and method for assigning reserved blocks thereof: A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area The device includes a hidden area including a first reserved block area and a second reserved block area, wherein the first... Agent: Frank Chau, Esq. F. Chau & Associates, Llc

20080112240 - Memory device and method of repairing the same: A memory device includes a main memory cell having a plurality of first memory cells for storing data, wherein a special block for storing a column address corresponding to a first memory cell having at least one failure is disposed in a part of area of the main memory cell;... Agent: Townsend And Townsend And Crew, LLP

20080112237 - Method and enhanced sram redundancy circuit for reducing wiring and required number of redundant elements: A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time,... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080112239 - Repair fuse circuit for storing i/o repair information therein: A repair fuse circuit includes an address comparator, and a plurality of I/O bus select bit output units. The address comparator outputs repair signals for selecting a redundant column that will replace a fail column of a plurality of redundant columns according to a column address. The plurality of I/O... Agent: Townsend And Townsend And Crew, LLP

20080112241 - Integrated circuit device: An integrated circuit device according to an embodiment of this invention includes: a memory having: a first port to which a first clock signal is input, and a second port to which a second clock signal is input; and a built-in self test circuit having: a first signal generating circuit... Agent: Amin, Turocy & Calvin, LLP

20080112242 - Multichip and method of testing the same: A multichip and method of testing a multichip, the multichip including a control chip having a central processing unit (CPU) and a plurality of memories, each memory of the plurality of memories storing information related to testing the multichip, comprises connecting one of the memories to the control chip; reading,... Agent: Mills & Onello LLP

20080112243 - Memory bus output driver of a multi-bank memory device and method therefor: In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a... Agent: Qualcomm Incorporated

20080112244 - Semiconductor memory device including a sense amplifier having a reduced operating current: A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit... Agent: Foley And Lardner LLP Suite 500

20080112245 - Bit line dummy core-cell and method for producing a bit line dummy core-cell: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080112246 - Digital calibration circuits, devices and systems including same, and methods of operation: A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080112247 - Data conversion circuit, and semiconductor memory apparatus using the same: A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects either a first operation mode to... Agent: Venable LLP

20080112248 - Refresh period adjustment technique for dynamic random access memories (dram) and integrated circuit devices incorporating embedded dram: A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention,... Agent: Hogan & Hartson LLP

20080112249 - Circuit and method of generating voltage of semiconductor memory apparatus: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and... Agent: Venable LLP

20080112250 - Memory including deep power down mode: A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first... Agent: Dicke, Billig & Czaja

20080112251 - Semiconductor memory devices having optimized memory block organization and data line routing for reducing chip size and increasing speed: Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.... Agent: F. Chau & Associates, Llc

20080112252 - Apparatus for controlling gio line and control method thereof: A control apparatus of a GIO line includes a plurality of GIO line termination units, and a GIO control unit for generating a control signal to activate an operation of a specific one of the plurality of GIO termination units according to a data transmission method. Further, a method of... Agent: Lowe Hauptman Ham & Berner, LLP

20080112253 - Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density: Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased i