Static information storage and retrieval inventions 04/08

20080094869 - Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to nwells and pwells: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address... Agent: Stanley P. Fisher Reed Smith LLP

20080094870 - Semiconductor memory device: A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array.... Agent: Mcdermott Will & Emery LLP

20080094871 - Sequential and video access for non-volatile memory arrays: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry... Agent: Ovonyx, Inc

20080094872 - Method for forming organic layer pattern, organic layer pattern prepared by the same and organic memory devices comprising the pattern: Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and... Agent: Harness, Dickey & Pierce, P.L.C

20080094873 - Method and apparatus for non-volatile multi-bit memory: A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094875 - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094874 - Multiple-read resistance-variable memory cell structure and method of sensing a resistance thereof: Disclosed herein is a multiple read-port nonvolatile memory cell structure, and related method of sensing a resistance state of memory cell, for high-speed and high-bandwidth applications. It provides about a 2× bandwidth gain over conventional cells during the read cycle in embodiments where two read ports are constructed. For example,... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080094876 - Sensing a signal in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080094877 - Faster initialization of dram memory: A method of initializing dynamic random access memory (DRAM) comprises allocating one or more rows of a plurality of cells in the DRAM; signaling an initialization request to initialize the allocated one or more rows; and simultaneously initializing all cells in each of the one or more allocated rows upon... Agent: Honeywell International Inc.

20080094878 - Ring oscillator row circuit for evaluating memory cell performance: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080094879 - Semiconductor memory device: A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs control so that in writing data into the memory cell, a voltage at one of the two storage nodes holding... Agent: Mcdermott Will & Emery LLP

20080094881 - Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell: A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment... Agent: Edell , Shapiro & Finnan , LLC

20080094883 - Magnetic memory: To provide a magnetic memory capable of reducing the amount of write current, even when the element size is 0.7 μm or less. Each of storage areas has a transistor for read/write control, which is connected electrically to either one of the fixed layer and the free layer of each... Agent: Oliff & Berridge, PLC

20080094880 - Magneto-resistance element and magnetic random access memory: A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and... Agent: Sughrue Mion, PLLC

20080094882 - Non-volatile memory device: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the... Agent: Zilka-kotab, PC- Ibm

20080094884 - Reference cell scheme for mram: An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a... Agent: Saile Ackerman LLC

20080094885 - Bistable resistance random access memory structures with multiple memory layers and multilevel memory states: A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094886 - Non-uniform switching based non-volatile magnetic based memory: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the... Agent: Law Offices Of Imam

20080094887 - Semiconductor device using magnetic domain wall movement and method of manufacturing the same: A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain... Agent: Sughrue Mion, PLLC

20080094888 - Magnetic tunnel junction devices and magnetic random access memory: A magnetic random access memory (MRAM) is disclosed. The MRAM includes a first electrode, an antiferromagnetic layer formed over the first electrode, a pinned layer formed over the antiferromagnetic layer, a barrier layer formed over the pinned layer, a composite free layer formed over the barrier layer, and a second... Agent: Quintero Law Office, PC

20080094889 - Semiconductor integrated circuit: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground... Agent: Volentine & Whitt PLLC

20080094892 - Method for protecting memory cells during programming: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when... Agent: Technology & Innovation Law Group, PC

20080094893 - Nonvolatile memory system and associated programming methods: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level... Agent: Volentine & Whitt PLLC

20080094891 - Parallel threshold voltage margin search for mlc memory application: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094894 - Nonvolatile semiconductor memory and memory system: A nonvolatile semiconductor memory includes a plurality of memory cells each configured to store M bits of data, where M is an integer greater than 1. In addition, the memory includes a selection circuit configured to select a first or second mode according to an instruction from outside of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094895 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space... Agent: Mills & Onello LLP

20080094896 - Non volatile memory rad-hard (nvm-rh) system: The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080094897 - Non-volatile semiconductor memory device and method for recovering data in non-volatile semiconductor memory device: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing... Agent: Harness, Dickey & Pierce, P.L.C

20080094899 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device, allocates data contained in an ECC frame as a first data group to be stored in a first memory cell group composed of a plurality of first memory cells selected by a first word line and a second data group to be stored in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094898 - Non-volatile semiconductor storage device: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the... Agent: Amin, Turocy & Calvin, LLP

20080094900 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an example of the present invention includes first and second word lines extending in a first direction and having the same row address, a first block including the first word line and having a first block address, a second block including the second word... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094901 - Flash memory device capable of preventing coupling effect and program method thereof: The present invention provides a flash memory device that comprises a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in... Agent: Mills & Onello LLP

20080094902 - Flash memory devices and methods of operating the same: A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage... Agent: Harness, Dickey & Pierce, P.L.C

20080094903 - Nand flash memory: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094904 - Flash memory device operating at multiple speeds: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first... Agent: Volentine & Whitt PLLC

20080094905 - Nonvolatile memory: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the... Agent: Miles & Stockbridge PC

20080094906 - Voltage regulator for the programming circuit of a memory cell: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080094890 - Semiconductor memory device and data write and read method thereof: A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the... Agent: Volentine & Whitt PLLC

20080094907 - Flash memories with adaptive reference voltages: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of... Agent: Mark M. Friedman

20080094909 - Low power multiple bit sense amplifier: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20080094908 - Temperature compensation of voltages of unselected word lines in non-volatile memory based on word line position: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen Marcus & Deniro LLP

20080094910 - Flash memory device and program method thereof: A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality... Agent: F. Chau & Associates, LLC

20080094911 - Non-volatile memory with improved program-verify operations: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080094912 - Selective slow programming convergence in a flash memory device: A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to... Agent: Leffert Jay & Polglaze, P.A.

20080094913 - Memory device for protecting memory cells during programming: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when... Agent: Beyer Weaver LLP

20080094914 - Methods of restoring data in flash memory devices and related flash memory device memory systems: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit... Agent: Myers Bigel Sibley & Sajovec

20080094916 - Memory device for controlling current during programming of memory cells: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and... Agent: Beyer Weaver LLP

20080094915 - Method for controlling current during programming of memory cells: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and... Agent: Beyer Weaver LLP

20080094917 - Method of operating a semiconductor memory device having a recessed control gate electrode: A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the... Agent: Harness, Dickey & Pierce, P.L.C

20080094918 - Memory read control circuit and control method thereof: A control circuit to which a read requirement signal for data read of a memory and a burst length information signal for the read requirement are input controls a pull-up circuit so as to pull-up a data strobe signal if the read requirement signal is active. A mask signal is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080094919 - Noise resistant small signal sensing circuit for a memory device: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080094920 - Memory and low offset clamp bias circuit thereof: A memory and a low offset clamp bias circuit thereof are provided. The low offset clamp bias circuit is adapted for any existing memory and is used for reducing the variation of a drain side voltage Vd supplied to a memory cell in a memory cell array area through the... Agent: J C Patents, Inc.

20080094921 - Semiconductor storage device: A semiconductor storage device according to the present invention comprises a plurality of memory cells each provided with an access transistor in which a source is connected to a bit line and a gate is connected to a word line and a capacitor in which a storage electrode is connected... Agent: Mcdermott Will & Emery LLP

20080094922 - Semiconductor device: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read... Agent: Miles & Stockbridge PC

20080094923 - Non-volatile memory device capable of reducing threshold voltage distribution: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080094924 - Memory device having selectively decoupleable memory portions and method thereof: In response to determining a bit cell of a bit cell array of a memory device is a defective bit cell, a portion of the bit cell array including the defective bit cell is decoupled from a power source of the memory device. The portion can be decoupled via a... Agent: Larson Newman Abel Polansky & White, LLP

20080094925 - Soft error robust static random access memory cells: A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell comprises the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to... Agent: Gowling Lafleur Henderson LLP

20080094926 - Portable device for storing private information such as medical, financial or emergency information: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to... Agent: Stmicroelectronics, Inc.

20080094927 - Flash memory device with word line discharge unit and data read method thereof: Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies voltages for a read operation to the... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080094928 - Semiconductor memory having data line separation switch: A semiconductor memory comprises a data line separation switch circuit, which controls connection and separation of digit lines DT/DB connected to a memory cell and sense amplifier, and a control circuit, which performs a control of switching the data line separation switch circuit from turning-on to turning-off according to the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080094929 - Two-cycle sensing in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080094930 - Temperature compensation of select gates in non-volatile memory: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen/sandisk Corporation

20080094931 - Memory device performing partial refresh operation and method thereof: The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit storing part for storing refresh check bits corresponding to the memory blocks, respectively;... Agent: Mills & Onello LLP

20080094933 - Low-power dram and method for driving the same: A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured... Agent: Mcdermott Will & Emery LLP

20080094932 - Semiconductor memory device and methods thereof: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated... Agent: Harness, Dickey & Pierce, P.L.C

20080089106 - Memory circuit and semiconductor device: A semiconductor circuit of the invention comprises: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers each for amplifying data of the memory cell connected to a selected word... Agent: Mcginn Intellectual Property Law Group, PLLC

20080089104 - Semiconductor memory device and method for fabricating semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device, including, a semiconductor substrate, a phase-change element formed on the semiconductor substrate, the phase-change element including a phase-change film and electrode films, a joule heat portion contacting with the electrode film, the phase-change film being... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089107 - Memory chip architecture with high speed operation: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a... Agent: Blakely Sokoloff Taylor & Zafman

20080089105 - Variable resistance memory device and method of manufacturing the same: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed... Agent: F. Chau & Associates, LLC

20080089108 - Probe-based storage device: In one embodiment, the present invention includes an apparatus having a conductive storage medium to store information in the form of electrostatic charge. The conductive storage medium can be disposed in a non-conductive layer that is formed over a charge blocking layer, which in turn may be disposed over an... Agent: Trop Pruner & Hu, PC

20080089109 - Ferroelectric memory: A ferroelectric memory comprises a memory cell block of plural serially connected memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel therewith. And the ferroelectric memory comprises a cell transistor resistance measuring circuit, a word line voltage controller, and a word line voltage generator. The... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080089110 - Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems: Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a... Agent: Hewlett Packard Company

20080089111 - Resistance type memory device and fabricating method and operating method thereof: A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and... Agent: J C Patents, Inc.

20080089112 - Memory element and memory device comprising memory layer positioned between first and second electrodes: A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a... Agent: Wolf Greenfield & Sacks, P.C.

20080089113 - Organic-complex thin film for nonvolatile memory applications: An electronic or electro-optic device according to an embodiment of this invention has a first electrode, a second electrode spaced apart from the first electrode, and an organic composite layer disposed between the first electrode and the second electrode. The organic composite layer is composed of an electron donor material,... Agent: Venable LLP

20080089114 - Memory cell array: A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells... Agent: Edell, Shapiro & Finnan, LLC

20080089115 - Semiconductor memory device: In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in... Agent: Mcdermott Will & Emery LLP

20080089116 - Sram voltage control for improved operational margins: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of... Agent: International Business Machines Corporation Dept. 18g

20080089118 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes a magnetoresistive effect element having a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction is reversible, and a nonmagnetic layer formed between the fixed layer and the recording layer, a hollow portion being formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089117 - Memory cell and magnetic random access memory: A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings... Agent: Sughrue Mion, PLLC

20080089119 - Offset compensated sensing for magnetic random access memory: An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and... Agent: Dickstein Shapiro LLP

20080089120 - Resistive memory devices having a cmos compatible electrolyte layer and methods of operating the same: Example embodiments may provide a resistive memory having an amorphous solid electrolyte layer and/or a method of operating the memory. The resistive memory may include a switching device and/or a storage node connected to the switching device. The storage node may include a lower electrode, an upper electrode crossing the... Agent: Harness, Dickey & Pierce, P.L.C

20080089121 - Semiconductor memory device and method of controlling the same: A semiconductor memory device comprising: first and second wirings arranged in a matrix; and a memory cell being provided at an intersecting point of the first and second wirings and including a resistance change element and an ion conductor element connected to each other in a cascade arrangement between the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089123 - Method for programming a multi-level non-volatile memory device: A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by a least significant bits (LSBs) and a most significant bits (MSBs) are programmed first with LSBs and then with MSBs. The programmed storage cells... Agent: F. Chau & Associates, LLC

20080089124 - Removable data storage device and method: Applicant's teachings relate to a removable data storage device and method. Various embodiments of applicant's teachings show a removable data storage device comprising an external connector to removably connect the data storage device to a computing device, a memory device mounted on a first printed circuit board, a flexible connector... Agent: Bereskin And Parr

20080089125 - Memory device: An embodiment of a non-volatile memory device is provided. The memory device includes a memory matrix comprising a plurality of memory cells, arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines; each word line is associated with... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20080089126 - Circuitry for reliability testing as a function of slew: A reliability test chain includes: a stress chain; and transition time control circuits coupled to tap points along the stress chain such that transition times of a signal on the stress chain are controlled.... Agent: Texas Instruments Incorporated

20080089129 - Flash memory device with flexible address mapping scheme: A flash memory device includes a flash memory cell array which includes a plurality of memory cells arranged in rows and columns, reading and programming circuitry configured to read data from and program data into the memory cells of the flash memory cell array, and a control logic block configured... Agent: Volentine & Whitt PLLC

20080089127 - Non-volatile memory with dual voltage select gate structure: A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an... Agent: Vierra Magen/sandisk Corporation

20080089128 - Programming non-volatile memory with dual voltage select gate structure: A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an... Agent: Vierra Magen/sandisk Corporation

20080089130 - Non-volatile memory devices and methods of programming the same: A non-volatile semiconductor memory device and method of programming the non-volatile semiconductor memory device are disclosed. The non-volatile semiconductor memory device includes a selected word-line and unselected word-lines including at least one unselected word-line to which a first voltage signal is applied. The selected word-line is coupled to a selected... Agent: Harness, Dickey & Pierce, P.L.C

20080089131 - Flash memory device including blocking voltage generator: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is... Agent: Myers Bigel Sibley & Sajovec

20080089122 - Sense amplifying circuit capable of operating with lower voltage and nonvolatile memory device including the same: A sense amplifying circuit capable of operating with a lower voltage and/or a nonvolatile memory device including the same may be provided. The nonvolatile memory device may include a nonvolatile memory cell array including a first bit line connected with a first memory cell and/or a second bit line connected... Agent: Harness, Dickey & Pierce, P.L.C

20080089132 - Partitioned soft programming in non-volatile memory: Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of... Agent: Vierra Magen/sandisk Corporation

20080089133 - Systems for partitioned soft programming in non-volatile memory: Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of... Agent: Vierra Magen/sandisk Corporation

20080089136 - Non-volatile memory device, method of manufacturing the same and method of operating the same: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have... Agent: F. Chau & Associates, LLC

20080089134 - Partitioned erase and erase verification in non-volatile memory: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of... Agent: Vierra Magen/sandisk Corporation

20080089135 - Systems for partitioned erase and erase verification in non-volatile memory: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of... Agent: Vierra Magen/sandisk Corporation

20080089137 - Semiconductor device: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1”... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080089138 - Concurrent status register read: Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits.... Agent: Qualcomm Incorporated

20080089139 - Memory accessing circuit system: A configurable memory system and method is described wherein an integrated circuit coupled to a memory device includes application logic and memory interface logic in communication with the application logic, the memory interface logic configured to access a memory array within the memory device. The memory interface logic provides logic... Agent: Carr & Ferrell LLP

20080089140 - Adaptive regulator for idle state in a charge pump circuit of a memory device: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of... Agent: Volpe And Koenig, P.C.

20080089142 - Voltage generation circuit, flash memory device including the same and method for programming the flash memory device: A voltage generation circuit of a flash memory device includes a high voltage generator, a word line voltage generator, and a column selection voltage switch. The high voltage generator is configured to increase an internal power voltage from a first voltage to a second voltage which is higher than the... Agent: Volentine & Whitt PLLC

20080089143 - Voltage monitoring device in semiconductor memory device: An apparatus or method for monitoring an internal power voltage and generating a digital signal based on a monitored result for use in a semiconductor device includes a conversion device for converting a difference between an internal power voltage and a reference power voltage into a digital signal and an... Agent: Blakely Sokoloff Taylor & Zafman

20080089141 - Voltage regulator in a non-volatile memory device: System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage (VDD) and a mirror voltage (Vmirror). When the voltage VDD is greater than the voltage Vmirror beyond a threshold value, a control signal turns off a... Agent: Klein, O'neill & Singh, LLP

20080089144 - Very small swing high performance asynchronous cmos static memory (multi-port register file) with power reducing column multiplexing scheme: The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements... Agent: Mcandrews Held & Malloy, Ltd

20080089145 - Dual port sram with dedicated read and write ports for high speed read operation and low leakage: A dual port static random access memory (SRAM) having dedicated read and write ports provides high speed read operation with reduced leakages. The dual port SRAM includes at least one write word line, at least one read word line, at least one pair of write bit line and read bit... Agent: Hogan & Hartson LLP

20080089146 - Semiconductor device: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080089147 - Circuit and method for generating column path control signals in semiconductor device: A circuit for generating column path control signals in a semiconductor device is provided. The circuit includes a strobe signal delay unit configured to receive a strobe signal, and delay the received strobe signal for different delay periods, to generate a plurality of respective delayed strobe signals, and a control... Agent: Cooper & Dunham, LLP

20080089149 - Semiconductor memory apparatus for allocating different read/write operating time to every bank: A semiconductor memory apparatus includes an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal, a precharge signal generation unit that delays at least one of the active signals to generate at least one precharge signal for enabling... Agent: Venable LLP

20080089148 - Voltage contol apparatus and method of controlling voltage using the same: A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either... Agent: Venable LLP

20080089151 - Methods of determining laser alignment and related structures, devices, and circuits: Methods may be provided to determine an alignment of a laser with respect to an integrated circuit device including a fuse pattern and a monitoring pattern adjacent the fuse pattern. More particularly, the fuse pattern may be cut with radiation from the laser. After cutting the fuse pattern, an electrical... Agent: Myers Bigel Sibley & Sajovec

20080089150 - Semiconductor memory apparatus and method of controlling redundancy thereof: A semiconductor memory apparatus includes a memory cell array. A redundancy controller that determines whether to activate a redundancy enable signal on the basis of a refresh signal and outputs the redundancy enable signal. A comparator outputs a redundancy selection signal in response to the redundancy enable signal and an... Agent: Venable LLP

20080089152 - Semiconductor memory device: A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the... Agent: Young & Thompson

20080089153 - Semiconductor memory device and method thereof: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20080089154 - Memory device: A memory device is provided which includes a substrate, lower electrodes, selecting elements, memory elements formed of chalcogenide material and upper electrodes. The selecting elements and the memory elements are arranged to be disposed between the upper electrodes and the lower electrodes. In addition, the lower electrodes, the memory elements... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080089155 - Data receiver and semiconductor device including the data receiver: The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In... Agent: Volentine & Whitt PLLC

20080089156 - Semiconductor memory device having replica circuit: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second... Agent: Amin, Turocy & Calvin, LLP

20080089157 - Photonic-interconnect systems for reading data from memory cells and writing data to memory integrated circuits: Various embodiments of the present invention are related to photonic-interconnect systems for reading data from and writing data to memory cells of memory chips at approximately the same time. In one embodiment of the present invention, A photonic-interconnect system comprises a photonic interconnect coupled to a photonic device. The photonic... Agent: Hewlett Packard Company

20080089158 - Memory device and method having data path with multiple prefetch i/o configurations: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080089159 - Apparatus and method for programming an electronically programmable semiconductor fuse: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective... Agent: International Business Machines Corporation Dept. 18g

20080089160 - Semiconductor device: A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing... Agent: Sughrue Mion, PLLC

20080089161 - Method for testing flash memory power loss recovery: Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt/stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing... Agent: Leffert Jay & Polglaze, P.A.

20080089162 - Protection of non-volatile memory component against data corruption due to physical shock: A device, a computer readable medium, and a method are provided. The device includes, but is not limited to, a sensor, a processor, a non-volatile memory, and a computer-readable medium. The computer-readable medium includes, but is not limited to, computer-readable instructions stored therein that, upon execution by the processor, perform... Agent: Foley & Lardner LLP

20080089163 - Semiconductor memory device and method for arranging and manufacturing the same: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two... Agent: Myers Bigel Sibley & Sajovec

20080089164 - Method and apparatus for increasing clock frequency and data rate for semiconductor devices: An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.... Agent: Edell, Shapiro & Finnan, LLC

20080089166 - Output control signal generating circuit: An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used... Agent: Mcdermott Will & Emery LLP

20080089165 - Semiconductor device: A semiconductor device which continuously outputs data in synchronism with a first clock includes a clock generator which generates a second clock from the first clock which is externally supplied, a flip-flop circuit which operates in synchronism with the second clock, and receives the data, an output buffer circuit which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080089167 - Semiconductor memory and memory module: A semiconductor memory is provided in which a verification result of a circuit operation in a test mode can be output from a memory module complying with the FB-DIMM even if the semiconductor memory is mounted on the memory module. The semiconductor memory includes: a command decoding section that decodes... Agent: Sughrue Mion, PLLC

20080084725 - 3d chip arrangement including memory manager: Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface... Agent: Hollingsworth & Funk, Llc

20080084727 - Scaleable memory systems using third dimension memory: A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays... Agent: Unity Semiconductor Corporation

20080084729 - Semiconductor device with three-dimensional array structure: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory... Agent: Myers Bigel Sibley & Sajovec

20080084724 - System and method for providing content-addressable magnetoresistive random access memory cells: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic... Agent: Orrick, Herrington & Sutcliffe, LLP Ip Prosecution Department

20080084726 - Semiconductor integrated circuit device and method for designing the same: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric... Agent: Mcdermott Will & Emery LLP

20080084728 - Semiconductor device: A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080084730 - Semiconductor memory device: The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080084731 - Dram devices including fin transistors and methods of operating the dram devices: A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central portion of the active fin; one or more dummy gate structures on a peripheral portion of the active... Agent: Harness, Dickey & Pierce, P.L.C

20080084732 - Nbti-resilient memory cells with nand gates: An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience... Agent: Carrie A. Boone, P.c.

20080084733 - Back-gate controlled asymmetrical memory cell and memory using the cell: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect... Agent: Ryan, Mason & Lewis, LLP

20080084734 - Balanced and bi-directional bit line paths for memory arrays with programmable memory cells: Disclosed are embodiments of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080084736 - Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same: A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate... Agent: Lee & Morse, P.c.

20080084735 - Method for reading phase change memories and phase change memory: A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents may be... Agent: Seed Intellectual Property Law Group Pllc

20080084739 - Method for programming a multi-level non-volatile memory device: A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores data of a least significant bit (LSB) and a most significant bit (MSB). The cells are programmed with LSB data such that programmed storage cells have... Agent: F. Chau & Associates, Llc

20080084740 - Programming and reading five bits of data in two non-volatile memory cells: Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first... Agent: Myers Bigel Sibley & Sajovec

20080084738 - Semiconductor device including multi-bit memory cells and a temperature budget sensor: One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares a first signal from the first temperature budget sensor... Agent: Dicke, Billig & Czaja

20080084741 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality... Agent: Hogan & Hartson L.l.p.

20080084742 - Semiconductor storage device: Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock... Agent: Rader Fishman & Grauer Pllc

20080084743 - Memory stucture capable of bit-wise write or overwrite: An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile.... Agent: Imperium Patent Works

20080084744 - Method of making and operating a semiconductor memory array of floating gate memory cells with program/erase and select gates: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion... Agent: Dla Piper Us LLP

20080084745 - Dual-gate device and method: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080084746 - Non-volatile memory device adapted to reduce coupling effect between storage elements and related methods: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within... Agent: Volentine & Whitt Pllc

20080084748 - Apparatus with reduced program disturb in non-volatile storage: A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.... Agent: Vierra Magen/sandisk Corporation

20080084749 - Circuit and method generating program voltage for non-volatile memory device: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller... Agent: Volentine & Whitt Pllc

20080084747 - Reducing program disturb in non-volatile storage: A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected non-volatile storage elements that may be partially programmed.... Agent: Vierra Magen/sandisk Corporation

20080084750 - Nonvolatile semiconductor memory device and a method of word lines thereof: A nonvolatile semiconductor memory device having a first circuit for selecting one from a plurality of blocks, the first circuit having a plurality of transistors connected to word lines connected to some of the nonvolatile memory cells, and a second circuit for generating a first voltage V1, a second voltage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080084752 - Systems utilizing variable program voltage increment values in non-volatile memory program operations: The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells... Agent: Vierra Magen/sandisk Corporation

20080084751 - Variable program voltage increment values in non-volatile memory program operations: The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells... Agent: Vierra Magen/sandisk Corporation

20080084753 - Decoding method in an nrom flash memory array: A read operation method is provided for a flash memory array having a plurality of memory cells, wordlines, even bitlines, odd bitlines and a plurality of bitline transistors. The method includes pre-charging the plurality of even bitlines to about Vcc/n and pre-charging the plurality of odd bitlines to ground. The... Agent: Panitch Schwarze Belisario & Nadel LLP

20080084756 - Loading data with error detection in a power on sequence of flash memory device: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory... Agent: Panitch Schwarze Belisario & Nadel LLP

20080084757 - Memory cell: A method of reading memory includes sensing a plurality of memory cells simultaneously and providing a data signal corresponding to one of a plurality of programming states. The plurality of programming states include a number of programming states equal to twice a number of memory cells in the plurality of... Agent: Slater & Matsil LLP

20080084754 - Reverse reading in non-volatile memory with compensation for coupling: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where... Agent: Vierra Magen/sandisk Corporation

20080084758 - Sense amplifier for non-volatile memory: A sense amplifier comprising a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit, a charge control circuit for providing a precharge signal based on the output of the sense output circuit... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080084755 - Systems for reverse reading in non-volatile memory with compensation for coupling: Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where... Agent: Vierra Magen/sandisk Corporation

20080084759 - Nitride trapping memory device and method for reading the same: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according... Agent: Birch Stewart Kolasch & Birch

20080084760 - Efficient circuit and method to measure resistance thresholds: The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080084761 - Hybrid programming methods and systems for non-volatile memory storage elements: A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to... Agent: Beyer Weaver LLP/ Sandisk

20080084762 - Method of identifying logical information in a programming and erasing cell by on-side reading scheme: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage... Agent: Rabin & Berdo, Pc

20080084764 - Nrom memory device with enhanced endurance: The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected,... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080084737 - Method of achieving zero column leakage after erase in flash eprom: There is provided a method of correcting over-erased memory cells in a flash EPROM memory device so as to achieve zero column leakage after erase. A ground potential is applied to all of the word lines in the memory device. First positive pulse voltages are applied to each bit line... Agent: Davis Chin

20080084766 - Flash memory device and method of erasing memory cell block in the same: A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block... Agent: Townsend And Townsend And Crew, LLP

20080084765 - Method and apparatus for sector erase operation in a flash memory array: A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the sectors for erasure. Each of the sectors share the same common sector select transistor, and the common P-well.... Agent: Ingrassia Fisher & Lorenz, P.c.

20080084767 - Apparatus for eliminating leakage current of a low vt device in a column latch: An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is... Agent: Schneck & Schneck

20080084768 - Memory device and method thereof: A memory device and method thereof are provided. The example memory device may include a first buffer receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell, a second buffer loading stored LSB data stored from the memory cell and a... Agent: Harness, Dickey & Pierce, P.L.C

20080084769 - Memory system and method for operating a memory system: A memory system, in particular a buffered memory system, e.g. a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. In one embodiment, the memory system includes at least one buffered memory module, and a device for... Agent: Dicke, Billig & Czaja

20080084770 - Semiconductor memory device: A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a... Agent: Mcdermott Will & Emery LLP

20080084771 - Semiconductor device: A semiconductor device of the invention comprises: a plurality of unit blocks aligned at least in a bit line extending direction, into which a memory cell array is divided; a plurality of sense amplifiers provided in each of the unit blocks for amplifying data of memory cells through bit lines;... Agent: Mcginn Intellectual Property Law Group, Pllc

20080084772 - Semiconductor device: A semiconductor memory device includes a high voltage generator for generating a high voltage and applying the generated high voltage to a memory unit, a converter for converting an output voltage of the high voltage generator into a digital signal, and a mode selection unit for outputting an output of... Agent: Townsend And Townsend And Crew, LLP

20080084773 - Methods and systems for accessing memory: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated... Agent: Texas Instruments Incorporated

20080084774 - Floating body control in soi dram: A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to... Agent: Scully, Scott, Murphy & Presser, P.c.

20080084775 - Low leakage and data retention circuitry: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal.... Agent: Carr & Ferrell LLP

20080084776 - Semiconductor memory device: A semiconductor memory device includes: a global input/output line; a first global core line; a second global core line; a global core line controller disposed between the first global core line and the second global core line; a first bank coupled to the global core line controller through the first... Agent: Mcdermott Will & Emery LLP

20080084778 - Dynamic word line drivers and decoders for memory arrays: In a particular illustrative embodiment, a circuit device that includes first logic and second logic is disclosed. The first logic receives a clock signal and a first portion of a memory address of a memory array, decodes the first portion of the memory address, and selectively applies the clock signal... Agent: Qualcomm Incorporated

20080084779 - Semiconductor memory devices having control circuitry to avoid recovering a charge pump when executing consecutive sections of a continuous operation command and methods of operating the same: A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The... Agent: Myers Bigel Sibley & Sajovec

20080084777 - Ultra high-speed nor-type lsdl/domino combined address decoder: An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address hits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.c.

20080084780 - Memory write timing system: A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.... Agent: Iandiorio & Teska Intellectual Property Law Attorneys

20080084781 - Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith: A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the... Agent: Garlick Harrison & Markison

20080084782 - Data storage device and its controlling method: A data storage device includes: a first nonvolatile memory section; a second nonvolatile memory section having a smaller memory capacity than the first nonvolatile memory section; a first write control section that performs a cyclic write control including sequentially writing received data to one-dimensionally arranged data areas in the first... Agent: Harness, Dickey & Pierce, P.L.C

20080080223 - Cam asynchronous search-line switching: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A... Agent: Robert Walsh Patent Attorney, IBM Vlf

20080080222 - Systems and methods for digital transport of paramagnetic particles on magnetic garnet films: Systems and methods are provided for digital transport of paramagnetic particles. The systems and methods may include providing a magnetic garnet film having a plurality of magnetic domain walls, disposing a liquid solution on a surface of the magnetic garnet film, wherein the liquid solution includes a plurality of paramagnetic... Agent: Sutherland Asbill & Brennan LLP

20080080224 - Ferroelectric memory device, its driving method and electronic apparatus: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization... Agent: Harness, Dickey & Pierce, P.L.C

20080080225 - Semiconductor memory device, data storage device and method for controlling semiconductor memory device: A semiconductor memory device includes: a memory section; and a control section that controls writing and reading of data with respect to the memory section, wherein the memory section includes a first memory region formed from nonvolatile memory cells, each of the memory cells storing binary data corresponding to a... Agent: Harness, Dickey & Pierce, P.L.C

20080080226 - Memory system and method of operating the memory system: A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the... Agent: Slater & Matsil LLP

20080080228 - Resistive memory having shunted memory cells: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current... Agent: Dicke, Billig & Czaja

20080080227 - Tunable resistor and method for operating a tunable resistor: A tunable resistor includes a resistor input terminal, a resistor output terminal, and at least one current path connected between the resistor input terminal and the resistor output terminal. The at least one current path runs through at least one memory cell of an arrangement of programmable microelectronic memory cells.... Agent: Slater & Matsil LLP

20080080229 - Variable resistive memory wordline switch: A variable resistive memory device includes a main wordline, a wordline connecting switch in signal communication with the main wordline, a sub-wordline in signal communication with the wordline connecting switch, and a variable resistive memory cell having a variable resistance in signal communication with a first terminal of a switching... Agent: F. Chau & Associates, LLC

20080080231 - Nonvolatile latch circuit and nonvolatile flip-flop circuit: A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080230 - Two-port sram with a high speed sensing scheme: A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080080232 - Active write current adjustment for magneto-resistive random access memory: In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a... Agent: Slater & Matsil LLP

20080080233 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080234 - Magnetic memory device and write/read method of the same: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080236 - Flash memory device and program method: A method for programming a flash memory device includes selecting bit lines connected to a plurality of memory strings and selecting a word line. A lower bit is programmed into the memory cells connected to the selected word line and programming a upper bit into the memory cells. The step... Agent: Townsend And Townsend And Crew, LLP

20080080237 - Method of programming a multi level cell: The present invention relates to a method of programming a multi level cell capable of storing above 1 data bit. The method includes storing first data in a first storing unit, storing second data in a second storing unit, programming a least significant bit data in accordance with the data... Agent: Townsend And Townsend And Crew, LLP

20080080238 - Method of programming a semiconductor nonvolatile memory cell and memory with multiple charge traps: A semiconductor nonvolatile memory has a memory cell array in which each memory cell has a pair of charge traps and each charge trap stores data with at least three possible values. Different data values produce different read current values. To store data, a controller and a voltage supplying unit... Agent: Nixon Peabody, LLP

20080080235 - Power line compensation for flash memory sense amplifiers: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can... Agent: Dla Piper US LLP

20080080239 - Nonvolatile semiconductor memory device: A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080240 - Memory devices and memory systems having the same: A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller... Agent: Harness, Dickey & Pierce, P.L.C

20080080241 - Method for recycling flash memory: A method for recycling a flash memory includes rearranging the capacity of cells, centralizing bad sectors at a cell, labeling the cell as a useless cell, examining the bad sectors in each cell of the flash memory to determine whether or not the number of bad sectors in each cell... Agent: Schmeiser, Olsen & Watts

20080080242 - Flash memory device and erase method using the same: A flash memory device includes a plurality of block selection circuits and a plurality of memory blocks. The plurality of block selection circuits generate a block select signal in response to a plurality of decoded block address signals and a block control signal. The plurality of memory blocks are connected... Agent: Townsend And Townsend And Crew, LLP

20080080243 - Semiconductor memory device: There is provided a semiconductor memory device with NAND strings arranged therein, the NAND string having a plurality of electrically rewritable and non-volatile memory cells connected in series, including: a first data area; and a second data area, which is smaller in capacitance than the first data area and random... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080244 - Non-volatile memory devices including local control gates on multiple isolated well regions and related methods and systems: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided... Agent: Myers Bigel Sibley & Sajovec

20080080245 - P-channel memory and operating method thereof: A P-channel memory is provided. Each memory unit is constructed of a substrate, a gate structure, a first charge trapping layer, a second charge trapping layer, a first source/drain, and a second source/drain. The gate structure is located above the substrate. The first charge trapping layer and the second charge... Agent: Jianq Chyun Intellectual Property Office

20080080246 - Flash memory device which includes strapping line connected to selection line: A NAND flash array includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, memory cells operably coupled to word lines and connected to each other in series between the first and second selection transistors, and a strapping line... Agent: Volentine & Whitt PLLC

20080080248 - Cell operation methods using gate-injection for floating gate nand flash memory: A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from... Agent: Panitch Schwarze Belisario & Nadel LLP

20080080250 - Flash memory device and program method thereof: The present invention comprises a method of programming a flash memory device comprising performing a first program for programming cells to a first state and a second state higher than the first state, and performing a second program simultaneously together with the first program, for programming cells to the second... Agent: Townsend And Townsend And Crew, LLP

20080080247 - Low voltage low capacitance flash memory array: In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating... Agent: Macpherson Kwok Chen & Heid LLP

20080080251 - Method of reading dual-bit memory cell: A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a... Agent: Bacon & Thomas, PLLC

20080080249 - Non-volatile memory, fabricating method and operating method thereof: A non-volatile memory having a memory cell formed on a substrate is provided. A trench is formed in the substrate. The memory cell has a first gate, a second gate, a charge storage layer, a first source/drain region and a second source/drain region. The first gate is disposed in the... Agent: Jianq Chyun Intellectual Property Office

20080080252 - Methods of programming a memory cell and memory cell arrangements: A method of programming a memory cell is provided that includes determining whether the memory cell has been neutralized in accordance with a predefined program neutralizing criterion. If the memory cell has not been neutralized in accordance with the predefined program neutralizing criterion, the memory cell is neutralized in accordance... Agent: Slater & Matsil LLP

20080080253 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080255 - Dual voltage flash memory card: A voltage regulation circuit in a nonvolatile memory card accepts an input voltage from a host at two or more different voltage levels and provides an output voltage at a single level to components including a memory die. The voltage regulation circuit can provide an output voltage that is higher... Agent: Winston & Strawn, LLP

20080080254 - Dual voltage flash memory methods: A voltage regulation circuit in a nonvolatile memory card accepts an input voltage from a host at two or more different voltage levels and provides an output voltage at a single level to components including a memory die. The voltage regulation circuit can provide an output voltage that is higher... Agent: Winston & Strawn, LLP

20080080256 - Delay circuit for controlling a pre-charging time of bit lines of a memory cell array: A semiconductor memory device includes an array of memory cells and an adjustment circuit for adjusting the pulse width of an address transition detect equalizer (ATDEQ) signal. The adjustment circuit receives an address transition detection (ATD) signal and is responsive to the level changes of voltages Vp and Vn to... Agent: Nixon Peabody, LLP

20080080258 - Flash memory device and erase method thereof: The present invention relates to a flash memory device and an erase method thereof. The erase method includes performing an erase operation of a memory cell block including a plurality of pages, performing an erase verify operation and storing unerased page information about a page including unerased memory cells that... Agent: Townsend And Townsend And Crew, LLP

20080080257 - Flash memory device and its reading method: The present invention relates to a flash memory device and a reading method thereof wherein, in a page buffer of a flash memory device, a transmitting unit is disposed between a bit line and a sensing node and the lengths of the sensing node wiring are configured to be the... Agent: Lowe Hauptman Ham & Berner, LLP

20080080259 - 6 transistor memory circuit pair supporting simultaneous read/write and method therefore: A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read... Agent: International Business Machines Corporation

20080080262 - Data alignment circuit and data alignment method for semiconductor memory device: Data externally inputted in series are output aligned in parallel for a prefetch operation by a data alignment circuit. In the prefetch operation, sequential odd numbered data are latched in response to a rising data strobe signal and sequential even numbered data are latched in response to a falling data... Agent: Ladas & Parry LLP

20080080260 - Page buffer circuit of memory device and program method: A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and... Agent: Townsend And Townsend And Crew, LLP

20080080263 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a signal at an... Agent: Mcdermott Will & Emery LLP

20080080261 - Memory system topologies including a buffer device and an integrated circuit memory device: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices... Agent: Deniro/rambus

20080080264 - Internal voltage generator: An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by... Agent: Mcdermott Will & Emery LLP

20080080265 - Semiconductor memory and method for testing semiconductor memories: A semiconductor memory and method for testing semiconductor memory is disclosed. One embodiment provides a method including activating a first master word line. An electric voltage difference between the first master word line and an adjacent master word line is generated. The leakage current between the first master word line... Agent: Dicke, Billig & Czaja

20080080266 - Memory driver circuits with embedded level shifters: A memory line driver system may include a first input line to receive a clock-gated signal associated with a first supply power level, a second input line to receive an information signal associated with a second supply power level, and an output to drive a memory cell line according to... Agent: Buckley, Maschoff & Talwalkar LLC Attorneys For Intel Corporation

20080080267 - Data output control circuit and data output control method: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency... Agent: Ladas & Parry LLP

20080080269 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent: Frommer Lawrence & Haug

20080080268 - Semiconductor memory device, memory system having semiconductor memory device, and method for testing memory system: Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying... Agent: Volentine & Whitt PLLC

20080080270 - Apparatus and related method for controlling switch module in memory by detecting operation voltage of memory: An apparatus for controlling a switch module in a memory is disclosed. The apparatus includes first and second pulse width adjusting units, a decoder, and a detector. The first pulse width adjusting unit receives an input instruction signal and selectively adjusts a pulse width of the input instruction signal to... Agent: North America Intellectual Property Corporation

20080080271 - Delay selecting circuit for semiconductor memory device: A delay selection circuit for use in a semiconductor memory device prevents a tAA from increasing at a read operation due to a delayed command type of signal. The delay selection circuit includes a delay line unit, a power supply voltage detection unit and a path selection unit. The delay... Agent: Blakely Sokoloff Taylor & Zafman

20080080273 - Over-drive control signal generator for use in semiconductor memory device: An over-drive control signal generator for use in a semiconductor memory device includes a delay control unit and a pulse generation unit. The delay control unit delays a bit line sense amplifier (BLSA) enable signal for a first delay time in response to an auto refresh signal to thereby output... Agent: Blakely Sokoloff Taylor & Zafman

20080080272 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a first count unit for counting a delayed locked loop (DLL) clock in response to a clock enable signal; a first delay unit for delaying the clock enable signal for a delay time which corresponds to a delay amount of a delay model included in... Agent: Blakely Sokoloff Taylor & Zafman

20080080275 - Multi-chip and repairing method thereof: In accordance with aspects of the present invention, there is provided a repair method of a multi-chip that comprises a plurality of memory chips, each of the memory chips storing information with respect to remaining redundancy cells after repairing at a chip level. The repair method includes testing one of... Agent: Mills & Onello LLP

20080080274 - Method and apparatus for in-system redundant array repair on integrated circuits: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing... Agent: Scully, Scott, Murphy & Presser, P.C.

20080080276 - Clock frequency doubler method and apparatus for serial flash testing: Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory... Agent: Townsend And Townsend And Crew, LLP

20080080277 - Method and system of analyzing failure in semiconductor integrated circuit device: A method of analyzing a failure in a semiconductor integrated circuit device may include storing defects and analog characteristics correlated with the defects in a database, detecting a fail bit in a first wafer, measuring analog characteristics of the fail bit in the first wafer, and identifying which defect has... Agent: Harness, Dickey & Pierce, P.L.C

20080080279 - Semiconductor memory device: A semiconductor memory device includes a bit line precharge voltage generator, a bit line precharge circuit, a voltage drop circuit, and a voltage supply driver. The bit line precharge voltage generator generates a bit line precharge voltage. The bit line precharge circuit precharges a bit line. The voltage drop circuit... Agent: Mcdermott Will & Emery LLP

20080080280 - Semiconductor memory device: A semiconductor memory device includes a bank, a data transfer line, a precharge control circuit, and a precharge line. The bank includes a multiplicity of cell mats arranged in a matrix form. Each of the cell mats has a plurality of unit cells. The data transfer line arranged between the... Agent: Blakely Sokoloff Taylor & Zafman

20080080278 - Semiconductor memory device including write driver control circuit and write driver control method: A write driver control circuit controls operations of a write driver, which amplifies and transmits data of a pair of global input/output lines to a pair of local input/output lines in a write operation. A single type latch section compares states of first and second data of the pair of... Agent: Ladas & Parry LLP

20080080282 - Layout structures and methods of fabricating layout structures: Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of... Agent: Harness, Dickey & Pierce, P.L.C

20080080281 - Semiconductor memory device: A semiconductor memory device having a bit line sense amplifier supporting an over driving operation includes a voltage divider; a plurality of signal converters; a delay unit; and a drive control signal generator. The voltage divider divides an external voltage to generate a plurality of different voltage levels. The signal... Agent: Blakely Sokoloff Taylor & Zafman

20080080283 - Coupling device for transmitting data: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a... Agent: Dickstein Shapiro LLP

20080080284 - Method and apparatus for refreshing memory cells of a memory: Method and apparatus for refreshing selective memory cells. A refresh circuit is connected with the memory cells and operates to refresh data stored in the memory cells on the basis of the values of valid bits having a predefined association with the memory cells.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080080285 - Refresh circuit and refresh method in semiconductor memory device: A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received,... Agent: Harness, Dickey & Pierce, P.L.C

20080080286 - Semiconductor memory device with partial refresh function: A semiconductor memory device includes a timing signal circuit to generate a refresh timing signal comprised of a series of pulses, a refresh address circuit to generate a refresh address in synchronization with each pulse of the refresh timing signal, a pulse selecting circuit to assert a refresh request signal... Agent: Arent Fox LLP

20080080287 - High voltage generating device of semiconductor device: A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and... Agent: Townsend And Townsend And Crew, LLP

20080080289 - Internal voltage generator of semiconductor memory device: An internal voltage generator of a semiconductor memory device controls generating an internal voltage according to an increase of the internal voltage during an active mode, to thereby decrease current consumption. The internal voltage generator of a semiconductor memory device includes a voltage sensor, a plurality of first control units,... Agent: Mcdermott Will & Emery LLP

20080080288 - Semiconductor memory device: A semiconductor memory device includes: a plurality of cell array blocks; a boosted voltage driving unit for selectively supplying a boosted voltage to the cell array blocks; and a controller controlling a driving operation of the boosted voltage driving unit in response to a cell array block select signal.... Agent: Mcdermott Will & Emery LLP

20080080290 - Memory device having small clock buffer: A semiconductor memory device includes a clock enable buffer; a clock enable controller; a clock controller; a clock buffer; and a small clock buffer. The clock enable buffer buffers a clock enable signal to provide an internal clock enable signal. The clock enable controller synchronizes the internal clock enable signal... Agent: Blakely Sokoloff Taylor & Zafman

20080080292 - Control component for controlling a semiconductor memory component in a semiconductor memory module: A semiconductor memory module includes a control component connected via various buses to semiconductor memory components on the top and bottom of a module board. Depending on the storage capacity and the rank configuration of the semiconductor memory module, address terminals are actuated via selection circuits either with address signals... Agent: Edell, Shapiro & Finnan, LLC

20080080295 - Embedded semiconductor memory device having self-timing control sense amplifier: A semiconductor memory device includes a precharge unit to precharge a reference bit line and a selection bit line with the same potential, the selection bit line being connected to a target nonvolatile storage element from which data is to be read, a charge extraction unit to extract charges from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080080291 - Interleaved input signal path for multiplexed input: System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080080293 - Semiconductor memory apparatus having column decoder for low power consumption: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select... Agent: Mcdermott Will & Emery LLP

20080080294 - Semiconductor memory device: A semiconductor memory device includes decoding units for decoding input address signals efficiently. The semiconductor memory device includes a predecoding circuit, a first main decoding circuit, and a second main decoding circuit. The predecoding circuit predecodes address signals. The first main decoding circuit decodes output signals of the predecoding circuit,... Agent: Mcdermott Will & Emery LLP

20080080296 - Wordline driving circuit and method for semiconductor memory: Provided is a wordline driving circuit and method for a semiconductor memory, in which the wordline driving circuit includes an address decoding signal generator and a wordline voltage supplier. The address decoding signal generator receives a first row address decoding signal (URA) and generates a delayed URA signal (PXID). The... Agent: F. Chau & Associates, LLC

20080080297 - Self-timed memory having common timing control circuit and method therefor: A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that... Agent: Freescale Semiconductor, Inc. Law Department

20080080298 - Memory data transfer: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c