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Static information storage and retrieval March list of patents 03/08

20080074943 - Semiconductor memory device and method of controlling timing: In a semiconductor memory device, in addition to a sense amplifier connected to bit lines of a memory cell array having a plurality of memory cells in a disconnectable manner, the sense amplifier performing confinement operation to disconnect the bit lines of the memory cell array and amplify a data... Agent: Arent Fox LLP

20080068872 - Content addressable memory cell and content addressable memory using phase change memory: According to an example embodiment, a CAM cell included in a CAM may include a phase change memory device, a connector, and/or a developer. The phase change memory device may be configured to store data. The phase change memory device may have a resistance that may be varied according to... Agent: Harness, Dickey & Pierce, P.L.C

20080068873 - Ferroelectric memory apparatus and control method of the same: The ferroelectric memory apparatus stores data, and includes: a ferroelectric memory element; a temperature sensor which detects a temperature of the apparatus; a control unit that outputs a control signal indicating a voltage, the voltage increasing as the temperature detected by the temperature sensor decreases; and a voltage generating unit... Agent: Greenblum & Bernstein, P.L.C

20080068874 - Semiconductor memory device: This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080068875 - Variable resistive memory: A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of... Agent: F. Chau & Associates, LLC

20080068876 - Reduced leakage memory cells: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region... Agent: Schwegman, Lundberg & Woessner, P.A.

20080068877 - Semiconductor memory device and semiconductor integrated circuit: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080068879 - Phase change memory devices including memory cells having different phase change materials and related methods and systems: A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include... Agent: Myers Bigel Sibley & Sajovec

20080068878 - Resistive memory having shunted memory cells: A memory includes a bit line, a plurality of resistive memory cells coupled to the bit line, and a resistor. The resistor is coupled to the bit line to form a current divider with a selected memory cell during a read operation.... Agent: Dicke, Billig & Czaja

20080068880 - Memory device employing magnetic domain wall movement: Provided is a memory device employing magnetic domain wall movement. The memory device includes a writing track and a column structure. The writing track forms magnetic domains that have predetermined magnetization directions. The column structure is formed on the writing track and includes at least one interconnecting layer and at... Agent: Sughrue Mion, PLLC

20080068881 - Memory device employing magnetic domain wall movement: Provided is a memory device employing magnetic domain wall movement. The memory device includes a first track, an interconnecting layer, and a second track. The first track including a magnetic material is formed in a first direction. The interconnecting layer is formed on the first track. The second track including... Agent: Sughrue Mion, PLLC

20080068882 - Semiconductor device: A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and... Agent: Neil Steinberg

20080068883 - Flash memory devices and programming methods for the same: Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells... Agent: Harness, Dickey & Pierce, P.L.C

20080068885 - Method and apparatus for programming multi level cell flash memory device: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic... Agent: Volentine & Whitt PLLC

20080068884 - Method of controlling copy-back operation of flash memory device including multi-level cells: A method of controlling a copy-back operation of a flash memory device including multi-level cells. In the method, the copy-back operation can be executed even without an additional storage space. Accordingly, a program time can be shortened and operational performance of a flash memory device can be improved.... Agent: Lowe Hauptman Ham & Berner, LLP

20080068886 - Flash memory devices having multi-page copyback functionality and related block replacement methods: Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command.... Agent: Myers Bigel Sibley & Sajovec

20080068887 - Program methods for split-gate memory: An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first... Agent: Slater & Matsil, L.L.P.

20080068888 - Non-volatile memory devices having multi-page programming capabilities and related methods of operating such devices: Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the memory block may be received and temporarily stored.... Agent: Myers Bigel Sibley & Sajovec

20080068889 - Nand memory cell at initializing state and initializing process for nand memory cell: The invention is directed to a NAND memory cell at an initializing state. The NAND memory cell at the initializing state comprises a substrate, a gate, at least two doped regions, a carrier storage element and a plurality of carriers. The substrate has at least two isolation structures formed therein... Agent: J C Patents, Inc.

20080068891 - Boosting to control programming of non-volatile memory: Boosting signals are applied to unselected word lines for a set of NAND strings while a program voltage signal is applied to a selected word line. For a selected NAND string, in a first interval, the drain select gate is opened so that the NAND string communicates with a respective... Agent: Vierra Magen/sandisk Corporation

20080068890 - Nand flash memory with reduced programming disturbance: An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word... Agent: Graybeal, Jackson, Haley LLP

20080068892 - Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices: The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080068894 - Differential flash memory programming technique: The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory... Agent: Hitt Gaines, PC Lsi Corporation

20080068893 - Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell: A non-volatile semiconductor memory device includes a non-volatile memory cell and a write circuit that is adapted to write data to the memory cell by supplying a write voltage and a write control voltage to the memory cell to change the write state of the memory cell, changing the supply... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080068895 - Integrated circuit having a drive circuit: An intergrated circuit having a drive circuit is disclosed. One embodiment provides an intergrated memory circuit arrangement with a drive circuit for an EEPROM. In one embodiment, the drive circuit contains tunnel field effect transistors and can be produced in particular on a small chip area.... Agent: Dicke, Billig & Czaja

20080068896 - Sonos memory array with improved read disturb characteristic: A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at... Agent: Schneck & Schneck

20080068897 - Semiconductor memory device and memory system including semiconductor memory device: A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.... Agent: Volentine & Whitt PLLC

20080068898 - Data readout circuit of memory cells, memory circuit and method of reading out data from memory cells: A data readout circuit of memory cells for reading out data from the memory cells includes a determination circuit 3 that reads out a plurality of data from multiplexed memory cells 5 having a unique data inversion direction and determines data not inverted in the data inversion direction as valid... Agent: Staas & Halsey LLP

20080068899 - Storage management process, storage management apparatus, and computer-readable medium storing storage management program: A storage management process and a storage management apparatus for managing first data stored in a storage area in a storage device in a first one of storage nodes constituting a distributed storage system. The first data is read out from the storage device and checked for normality in response... Agent: Staas & Halsey LLP

20080068900 - Memory module decoder: A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives... Agent: Knobbe Martens Olson & Bear LLP

20080068901 - Wordline booster circuit and method of operating a wordline booster circuit: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of... Agent: W. Riyon Harding International Business Machines Corporation

20080068902 - Wordline booster design structure and method of operating a wordline booster circuit: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of... Agent: Richard M. Kotulak International Business Machines Corporation

20080068903 - Pram performing program loop operation and method of programming the same: A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and... Agent: Volentine & Whitt PLLC

20080068904 - System and method for providing programmable delay read data strobe gating with voltage and temperature compensation: The present invention is a method for providing programmable delay read data strobe gating with voltage and temperature compensation. The method includes receiving a training request. The method further includes calibrating programmable delay lines for operating frequency and voltage and temperature variation. The method further includes locking to a first... Agent: Lsi Corporation

20080068905 - Reparable semiconductor memory device: A semiconductor memory device, including a plurality of cell arrays, each cell array configured to receive and output data through first data IO lines and including at least one block having memory cells corresponding to a plurality of column selecting lines, a redundancy cell array configured to receive and output... Agent: Lee & Morse, P.C.

20080068907 - Balanced sense amplifier circuits: A balanced sense amplifier circuit. The balanced sense amplifier circuit includes a reading circuit, which includes a first transistor and a second transistor. The first and second transistors include (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second... Agent: Schmeiser, Olsen & Watts

20080068906 - Method and apparatus for testing a memory device: Disclosed is a method for testing a memory device with a long-term clock signal by automatically performing precharge only after activation. In this method, a signal for precharging the banks of the memory device is automatically generated only at the falling edge of an external signal when a signal for... Agent: Ladas & Parry LLP

20080068908 - Semiconductor memory device having a word line strap structure and associated configuration method: A semiconductor memory device having a memory cell array with sub-memory cell arrays arranged in a bit line direction and a word line direction which is perpendicular to the bit line direction. The memory cell arrays including a plurality of memory cells. The memory device further including sense amplifying portions... Agent: Volentine & Whitt PLLC

20080068909 - Semiconductor device: A semiconductor device of the invention comprises: a memory cell array including memory cells formed at intersections between word lines and bit lines; first and second input/output ports each defined for inputting/outputting data of the memory cell array; sense amplifiers for amplifying data of the memory cells through the bit... Agent: Mcginn Intellectual Property Law Group, PLLC

20080068910 - Memory circuits preventing false programming: Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080068911 - System and method for providing swap path voltage and temperature compensation: The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path... Agent: Lsi Corporation

20080068912 - Flash memory device and refresh method thereof: A method for refreshing a flash memory device includes providing first and second refresh fields that include a plurality of memory blocks, and determining, when there is a request for a refresh, a condition of a memory block to be refreshed in accordance with which of the first and second... Agent: Volentine & Whitt PLLC

20080068913 - Refreshing the content of a memory cell of a memory arrangement: A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.... Agent: Dicke, Billig & Czaja

20080068914 - Output driving circuit and semiconductor memory device having the same: An output driver, memory device and corresponding method are provided, the output driver having two transistors with their drains commonly connected and each of two sources of the two transistors connected to a separate supply node of a same polarity power supply, and a decoupling capacitor connected to each source;... Agent: F. Chau & Associates, LLC

20080068915 - Semiconductor memory device: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080068916 - Semiconductor memory device: In addition to a booster power supply circuit boosting a power supply voltage to supply a boost voltage VPP to a memory core, cell capacitors composing a stabilization capacitor, and a bias generation circuit supplying a midpoint potential to a connection point of the cell capacitors, further, a clamp circuit... Agent: Arent Fox LLP

20080068917 - Controller for controlling a memory component in a semiconductor memory module: A control component for controlling at least one semiconductor memory component in a semiconductor memory module includes an address generator circuit for generating address signals. The address generator circuit generates different address signals based on the input of a configuration signal. The control component is operable to actuate semiconductor memory... Agent: Edell, Shapiro & Finnan, LLC

20080068918 - Semiconductor memory device capable of relieving defective bits found after packaging: A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two... Agent: Scully Scott Murphy & Presser, PC

20080062735 - Nanoscale wire coding for stochastic assembly: Methods for obtaining codes to be implemented in coding nanoscale wires are disclosed. The methods disclosed teach how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further teach how to generate different code permutations through random misalignment and how to promote... Agent: Richard P. Berg, Esq. C/o Ladas & Parry

20080062738 - Storage element and method for operating a storage element: Storage element for permanently storing information in a memory device. A coupling circuit is configured to couple a first and a second fuse in parallel with a programming line. A programming unit to control the coupling circuit depending on a common write data to successively couple the first and the... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080062734 - Interchangeable connection arrays for double-sided dimm placement: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.... Agent: Intel/blakely

20080062737 - Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080062736 - Storage device: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct.... Agent: Stanley P. Fisher Reed Smith LLP

20080062739 - Memory erase management system: A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the... Agent: Law Offices Of Mikio Ishimaru

20080062740 - Methods of programming a resistive memory device: Methods of programming a RRAM device are provided. An increasing set current is applied to a data storing layer pattern of the RRAM device while measuring a resistance of the data storing layer pattern until the resistance indicates a set state in the data storing layer pattern. An increasing reset... Agent: Myers Bigel Sibley & Sajovec

20080062741 - Phase change random access memory and method of testing the same: Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of... Agent: Harness, Dickey & Pierce, P.L.C

20080062743 - Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080062742 - Tree-style and-type match circuit device applied to content addressable memory: A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The tree-style AND-type match circuit increases the parallelism of the... Agent: Rosenberg, Klein & Lee

20080062744 - Random access memory including nanotube switching elements: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic... Agent: Wilmerhale/boston

20080062748 - Dynamic latch state saving device and protocol: The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080062745 - Hot-carrier-based nonvolatile memory utilizing differing transistor structures: A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a control circuit configured to... Agent: Richard P. Berg, Esq. C/o Ladas & Parry

20080062746 - Sram static noise margin test structure suitable for on chip parametric measurements: A set of memory cell test structures and a method are disclosed for assessment of the static noise margin (SNM) of a memory cell or an array of such cells, for example, of SRAM cells of an integrated circuit device, using discrete point measurement structures provided either on-chip or within... Agent: Texas Instruments Incorporated

20080062747 - Systems and methods for improving memory reliability: Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic... Agent: Law Offices Of Mark L. Berrier

20080062749 - Voltage controlled static random access memory: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory... Agent: Downs Rachlin Martin PLLC

20080062750 - Magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures and related methods: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent... Agent: Myers Bigel Sibley & Sajovec

20080062753 - Phase change memory device generating program current and method thereof: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of... Agent: Harness, Dickey & Pierce, P.L.C

20080062751 - Phase change random access memory device: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current... Agent: Volentine & Whitt PLLC

20080062754 - Method of resetting phase change memory bits through a series of pulses of increasing amplitude: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse... Agent: Trop Pruner & Hu, PC

20080062752 - Phase change memory erasable and programmable by a row decoder: An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or... Agent: Seed Intellectual Property Law Group PLLC

20080062755 - Isolation structure for deflectable nanotube elements: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to... Agent: Wilmerhale/boston

20080062756 - Layout of a sram memory cell: The invention proposes a SRAM memory cell comprising two inverters and, a plurality of switches, the SRAM cell being manufactured in a technology offering N/P shunt capabilities, the inputs of the inverters being connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of said... Agent: Eric S. Hyman Blakely, Sokoloff, Taylor & Zafman

20080062757 - Nanocrystal write once read only memory for archival storage: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the... Agent: Schwegman, Lundberg & Woessner, P.A.

20080062758 - Nonvolatile semiconductor storage apparatus: A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080062760 - Flash multi-level threshold distribution scheme: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080062761 - Defective block isolation in a non-volatile memory system: A method and apparatus provide an improved identification and isolation of defective blocks in non-volatile memory devices having a plurality of user accessible blocks of non-volatile storage elements where each block also has an associated defective block latch. The method provides for sensing each defective block latch to determine whether... Agent: Welsh & Katz, Ltd

20080062763 - Multi-bit flash memory device and memory cell array: A flash memory device comprises a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.... Agent: Volentine & Whitt PLLC

20080062762 - Nand architecture memory with voltage sensing: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20080062764 - Nonvolatile semiconductor memory device: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080062765 - Method for non-volatile memory with linear estimation of initial programming voltage: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080062767 - Method of fixing a read evaluation time or the difference between a read charge voltage and a read discriminating voltage in a non-volatile nand type memory device: The evaluation time or the difference between the read charge voltage and the read discrimination voltage of the programmed or erased state of a cell of a NAND memory array is set for the individual memory device. This is done in such a way that at least partially compensates the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080062766 - Well bias circuit in a memory device and method of operating the same: A well bias circuit in a memory device includes a well voltage supplying circuit configured to apply a high voltage to a well for erasing data in a memory cell. A well discharging circuit is configured to discharge the high voltage applied to the well in accordance with a first... Agent: Townsend And Townsend And Crew, LLP

20080062768 - Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080062759 - Flash memory device, method of operating a flash memory device and method for manufacturing the same device: A flash memory device includes a semiconductor substrate having a field oxide layer defining an active area; a gate oxide layer formed over parts of the active area of the semiconductor substrate; a coupling oxide layer formed over both the semiconductor substrate and a sidewall of the polygate; a floating... Agent: Sherr & Nourse, PLLC

20080062769 - Memory device and method providing an average threshold based refresh: The present invention relates to a non-volatile memory device, comprising a memory array (10, 20) with a plurality of memory cells (100, 200) arranged in rows and columns, bit line conductors (12, 22) coupled to said rows of memory cells, an averaging circuit (11, 21) with inputs coupled to a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080062770 - Non-volatile memory with linear estimation of initial programming voltage: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080062778 - Semiconductor memory device and its driving method: A semiconductor memory device includes a data transfer line for read, a data signal transfer unit, a reset controller, and a data signal transfer unit for write. The data signal transfer unit for read receives a first data signal corresponding to a read command via the data transfer line and... Agent: Blakely Sokoloff Taylor & Zafman

20080062772 - Data output circuit for semiconductor memory device: The present invention relates to a semiconductor memory, and more specifically, to a data output circuit capable of differentiating global data lines in accordance to an operation mode to output them to a data input/output pin. The present invention includes: a multiplexer selecting any one of a plurality of global... Agent: Ladas & Parry LLP

20080062771 - Semiconductor memory apparatus and data masking method of the same: A memory apparatus includes: a memory cell block; a data input part that performs signal processing to transmit general data and mask information input to the semiconductor memory apparatus to the memory cell block, and outputs the processed data and information; a broadband data line connected between the data input... Agent: Venable LLP

20080062773 - System and method for simulating an aspect of a memory circuit: A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from... Agent: Zilka-kotab, PC

20080062774 - Data input circuit of semiconductor memory apparatus and method of inputting the data: A data input circuit for a semiconductor memory apparatus includes a write latency control unit configured to generate a buffer enable signal based on a low frequency operation mode signal. A data input buffer buffers input data in response to the buffer enable signal.... Agent: Venable LLP

20080062775 - Fusion memory device and method: A fusion memory device and method that is capable of storing binary data in a compressed format and reading out the compressed binary data in a decompressed format is provided. The fusion memory device includes a main memory for storing data in a compressed format; a secondary memory for buffering... Agent: The Farrell Law Firm, P.C.

20080062776 - Semiconductor memory device having complete hidden refresh function: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated.... Agent: Mcdermott Will & Emery LLP

20080062777 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a driving controller that decodes bank activating signals to generate a plurality of driving control signals, activates some of the driving control signals, and outputs the activated driving signals; and a plurality of internal voltage generators each of which outputs an internal voltage in response... Agent: Venable LLP

20080062779 - Semiconductor integrated circuit: In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 and 21AR2. A second holding circuit 30B is dedicated to a... Agent: Mcdermott Will & Emery LLP

20080062780 - Phase detection method, memory control method, and related device: A phase detection method for detecting a phase difference between a data strobe signal and a clock signal, includes: latching the clock signal according to the data strobe signal to generate a phase lead/lag detection result; delaying the data strobe signal to generate a plurality of delayed data strobe signals;... Agent: North America Intellectual Property Corporation

20080062781 - Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory: An apparatus for controlling a switch module in a memory is disclosed. A first pulse width adjusting unit receives an input instruction signal and adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. A decoder receives... Agent: North America Intellectual Property Corporation

20080062782 - Nonvolatile semiconductor memory device using nonvolatile storage elements to which data can be written only once: A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080062783 - Design structure for in-system redundant array repair in integrated circuits: A design structure for repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from... Agent: Greenblum & Bernstein, P.L.C

20080062784 - Semiconductor memory: In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080062786 - Apparatus and method for providing atomicity with respect to request of write operation for successive sector: An apparatus for providing atomicity with respect to a request of a write operation for successive sectors in a flash memory is provided. The apparatus includes a data write module writing data in a main sector of a page and allocating status bits indicating a status of the data write... Agent: Sughrue Mion, PLLC

20080062785 - Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage... Agent: Davis Wright Tremaine LLP

20080062788 - Parallel bit test circuit and method: A parallel bit test circuit for a semiconductor memory device may include a plurality of data compressors, a delay unit, and a bus width converter. The data compressors may receive data output from data lines, compress the data, and output the compressed data. The delay unit may receive a clock... Agent: Harness, Dickey & Pierce, P.L.C

20080062789 - Memory diagnosis test circuit and test method using the same: According to an example embodiment, a memory diagnosis test circuit may include a memory core block, a word line selector, a bit line selector, and/or an analog mode control unit. The memory core block may include a plurality of memory cells. The word line selector may be configured to select... Agent: Harness, Dickey & Pierce, P.L.C

20080062787 - Method of detecting bit line bridge by selectively floating even-or odd-numbered bit lines of memory device: Provided is a bit line bridge detection method for selectively floating even-numbered or odd-numbered bit lines. The bit line bridge detection method simultaneously activates even-numbered sense amplifiers and odd-numbered sense amplifiers in response to a sense amplifier enable signal. The even-numbered sense amplifiers and the odd-numbered sense amplifiers are selectively... Agent: Marger Johnson & Mccollom, P.C.

20080062790 - Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer: A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance... Agent: F. Chau & Associates, LLC

20080062792 - Memory device and method for precharging a memory device: A memory device having a short precharge time is disclosed. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a preparatory period during which the two pairs of bit lines and an input to... Agent: F. Chau & Associates, LLC

20080062791 - Precharge circuit of semiconductor memory apparatus: A precharge circuit for a semiconductor memory apparatus includes a preliminary precharge signal generating unit that extracts read or write command including a precharge command to enable a preliminary precharge signal, and feedbacks the enabled preliminary precharge signal, to disable the preliminary precharge signal; and a precharge signal generating unit... Agent: Venable LLP

20080062793 - Sense amplifier circuitry and architecture to write data into and/or read from memory cells: A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is... Agent: Neil Steinberg

20080062794 - Semiconductor memory device: A semiconductor memory device includes a pair of local input/output (IO) lines, a global IO line, a local driver configured to pull up/down voltage levels of the first and second local IO lines in response to input data, a global driver configured to pull up/down a voltage level of the... Agent: Mcdermott Will & Emery LLP

20080062795 - Method and system for dram sensing: This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080062796 - Apparatus, system, and method for calibrating a holographic storage device: An apparatus, system, and method are disclosed for calibrating a holographic storage device. A read channel reads a factory-stored hologram from a holographic media. A calculation module calculates a read difference between the read factory-stored hologram and a first holographic pattern that digitally describes the factory-stored hologram. In one embodiment,... Agent: Kunzler & Mckenzie

20080062798 - Refresh operation of memory device: A memory device includes a refresh generator and a refresh command generation circuit. The refresh generator generates a refresh signal for a refresh operation enable. The refresh command generation circuit logically combines the refresh signal and a reset signal to produce a refresh command. The refresh command generation circuit produces... Agent: Mcdermott Will & Emery LLP

20080062797 - Refresh sequence control for multiple memory elements: A method for controlling a refresh sequence for multiple memory elements within an electronic device is disclosed. The method involves adjusting a programmable signal delay to avoid a simultaneous memory refresh between two or more of the multiple memory elements and passing a refresh signal from one memory element to... Agent: Honeywell International Inc.

20080062799 - Circuit and method for selecting test self-refresh period of semiconductor memory device: The present invention provides a self-refresh period adaptable for testing cells that are weak against hot temperature stress. An apparatus for controlling a self-refresh operation in a semiconductor memory device includes a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable... Agent: Mcdermott Will & Emery LLP

20080062800 - Semiconductor memory device: A semiconductor memory device includes: a high voltage input pad for receiving a high voltage which has the highest voltage level among a plurality of voltages used for a data access operation; a core region for storing a plurality of data; a peripheral region including a circuit for accessing the... Agent: Blakely Sokoloff Taylor & Zafman

20080062801 - Semiconductor non-volatile memory, data-writing method, semiconductor non-volatile memory fabrication method, and data-writing program storage medium: A semiconductor non-volatile memory, a data-writing method, a semiconductor non-volatile memory fabrication method and a medium storing a data-writing program that are capable of suppressing a change, due to an operation of memorization of data to a charge accumulation portion, in data which has been memorized at another charge accumulation... Agent: Volentine & Whitt PLLC

20080062802 - Circuit implementation of a dynamic power supply for sram core array: A SRAM device includes at least one memory cell having a source line for receiving an internal supply power, and a voltage management circuit coupled to the source line for generating the internal supply power that varies in at least two different voltage levels, depending on various operation modes of... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080062804 - Segmented search line circuit device for content addressable memory: A segmented search line circuit device for content addressable memory is provided. This device includes a content addressable memory and a segmented unit, wherein the content addressable memory has a plurality of cells arranged in an array and a search line connected between each pair of adjacent cells. Moreover, a... Agent: Birch Stewart Kolasch & Birch

20080062805 - Semiconductor storage device: Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected... Agent: Sughrue Mion, PLLC

20080062803 - System and method for encrypting data: A system and method for encrypting data. The system includes a controller and a processing element (PE) array coupled to the controller. The PE array is operative to perform one or more of encryption functions and decryption functions using an encryption algorithm. According to the system and method disclosed herein,... Agent: Sawyer Law Group LLP

20080062806 - Phase change memory comprising a low-voltage column decoder: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block... Agent: Seed Intellectual Property Law Group PLLC

20080062808 - Semiconductor device: A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make a drive-targeted memory chip selected or... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080062807 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a... Agent: Shemwell Mahamedi LLP

20080062809 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the... Agent: Blakely Sokoloff Taylor & Zafman

20080062810 - Apparatus and method for controlling clock signal in semiconductor memory device: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially... Agent: Mcdermott Will & Emery LLP

20080055957 - Three-dimensional memory module (3d-mm) excelling contemporary micro-drive (cmd): The present invention discloses a three-dimensional memory module (3D-MM), which excels contemporary micro-drive (CMD) in both physical size and storage capacity. Three-dimensional memory (3D-M)-based 3D-MM ((3D)2-MM) further excels CMD in manufacturing cost. Mask-programmable (3D)2-MM is the only semiconductor storage that can store a mobile movie library.... Agent: Guobiao Zhang

20080055959 - High yielding, voltage, temperature, and process insensitive lateral poly fuse memory: The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding,... Agent: Michael J. Ure

20080055956 - Design structure for content addressable memory: A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20080055958 - Semiconductor memory device: A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected... Agent: Stanley P. Fisher Reed Smith LLP

20080055961 - Ferroelectric memory device and electronic apparatus: A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a second node; a first negative potential generation circuit connected to the first node; and a second negative... Agent: Harness, Dickey & Pierce, P.L.C

20080055962 - Ferroelectric semiconductor memory device: A memory cell includes a ferroelectric capacitor for holding a charge and a transistor connected in parallel with the ferroelectric capacitor. A plurality of the ferroelectric memory cells are connected in series to form a memory cell block. A selection transistor connects,to one end of the block. A bit line... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080055960 - Semiconductor storage device, and data reading method: A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the... Agent: Arent Fox LLP

20080055964 - Nonvolatile memory device and related method of operation: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater... Agent: Volentine & Whitt PLLC

20080055963 - Phase change random access memory and related methods of operation: In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop, division program operations for cell groups including the selected memory cells are performed in consecutive timeslots.... Agent: Volentine & Whitt PLLC

20080055965 - Non-volatile memory cell in standard cmos process: A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080055967 - Memory with low power mode for write: The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode... Agent: Texas Instruments Incorporated

20080055966 - Storage circuit with efficient sleep mode and method: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating... Agent: Freescale Semiconductor, Inc. Law Department

20080055968 - Memory with five-transistor bit cells and associated control circuit: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080055969 - Phase change memory: A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20080055971 - Phase change random access memory device and related methods of operation: A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of... Agent: Volentine & Whitt PLLC

20080055970 - Medium for use in data storage, thermal energy storage and other applications, with functional layer made of different materials: A medium for use in data storage, thermal energy storage and other applications, the medium comprising a functional layer made of different materials. One embodiment provides a data storage medium. The data storage medium comprises a substrate and a data storage layer supported by the substrate. The data storage layer... Agent: Dinsmore & Shohl LLP

20080055972 - Phase change random access memory: Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation... Agent: Harness, Dickey & Pierce, P.L.C

20080055973 - Small electrode for a chacogenide switching device and method for fabricating same: Semiconductor devices including a memory cell are provided. In one embodiment, the memory cell includes a first conductive material within a pore of a dielectric layer. The first conductive material may include a first surface having a first dimension that is less than the photolithographic limit. Further, in this embodiment,... Agent: Fletcher Yoder (micron Technology, Inc.)

20080055974 - Semiconductor device: A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and... Agent: Neil Steinberg

20080055975 - Method for measuring threshold voltage of sonos flash device: Embodiments relate to a method for measuring a threshold voltage of a flash device including inputting a voltage and a pulse width. The dependence of threshold voltage on the applied voltages and the pulse width may be determined by using a threshold voltage measuring equation, and equations regarding a plurality... Agent: Sherr & Nourse, PLLC

20080055976 - Mem suspended gate non-volatile memory: A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20080055979 - Method of monitoring an erase threshold voltage distribution in a nand flash memory device: A method monitors an erase threshold voltage distribution in a NAND flash memory device. The method programs a main cell by applying a first program voltage to the main cell, and then measures a threshold voltage of the main cell. The method programs a peripheral cell using a second program... Agent: Townsend And Townsend And Crew, LLP

20080055980 - Method and apparatus for a non-volatile memory device with reduced program disturb: A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the... Agent: Baker & Mckenzie LLP Patent Department

20080055981 - Non-volatile memory device and method of preventing hot electron program disturb phenomenon: A method for preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device. A channel boosting disturb-prevention voltage lower than a program-prohibit voltage applied to other word lines is applied to edge word lines coupled to memory cells that are nearest to select transistors. As... Agent: Townsend And Townsend And Crew, LLP

20080055982 - Non-volatile memory device and method of preventing hot electron program disturb phenomenon: A method for preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device. A channel boosting disturb-prevention voltage lower than a program-prohibit voltage applied to other word lines is applied to edge word lines coupled to memory cells that are nearest to select transistors. As... Agent: Townsend And Townsend And Crew, LLP

20080055984 - Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling: A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080055985 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array including a plurality of memory cells having two or more storage states, one of the plurality of memory cells... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080055986 - Semiconductor memory device having faulty cells: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080055987 - Memory device and method of operating a memory device: A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2n with n being a non-zero integer, and a circuit or device... Agent: Dicke, Billig & Czaja

20080055989 - Memory system including flash memory and method of operating the same: A method for operating a memory system including a flash memory device having a plurality of memory blocks comprises determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with... Agent: Volentine & Whitt PLLC

20080055988 - Method, apparatus, and system providing adjustable memory page configuration: A method, apparatus and system are described which provide a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.... Agent: Dickstein Shapiro LLP

20080055990 - Non-volatile semiconductor storage device and non-volatile storage system: This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080055992 - Semiconductor device with the high-breakdown-voltage transistors: A semiconductor device includes a unit high-breakdown-voltage transistor includes first to fourth high-breakdown-voltage transistors. The first high-breakdown-voltage transistor is connected to a first write line at the other end of the current path thereof, and includes a first gate which is disposed in a first direction. The second high-breakdown-voltage transistor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080055993 - System and memory for sequential multi-plane page memory operations: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20080055991 - Voltage generator circuit capable of generating different voltages based on operating mode of non-volatile semiconductor memory device: High voltage generator circuits and methods for operating non-volatile semiconductor memory devices are provided for use with non-volatile memory such as FLASH memory devices, to selectively generate different types of control voltages for various operating modes of non-volatile memory devices.... Agent: F. Chau & Associates, LLC

20080055994 - Concurrent programming of non-volatile memory: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common... Agent: Vierra Magen/sandisk Corporation

20080055998 - Flash memory device and method for programming multi-level cells in the same: In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of... Agent: Volentine & Whitt PLLC

20080055997 - Flash memory device and refresh method: A flash memory device is disclosed and includes a memory cell array comprising memory cells arranged in rows and columns, a page buffer circuit having a single latch structure and configured to read data from a selected page in the memory cell array, and a controller controlling the page buffer... Agent: Volentine & Whitt PLLC

20080055996 - Flash memory device including unified oscillation circuit and method of operating the device: Embodiments of the present invention provide a flash memory device with a unified oscillation circuit, and a method of operating the device. The unified oscillation circuit produces alternative internal clock signals for corresponding alternative operating modes of the flash memory device. At least a portion of the unified oscillation circuit... Agent: Volentine & Whitt PLLC

20080055999 - Nonvolatile semiconductor memory device and writing method thereof: Disclosed herein is a nonvolatile semiconductor memory device including: a first selection transistor configured to be connected to a bit line; a second selection transistor configured to be connected to a common source line; a memory cell configured to be connected in series between the first and second selection transistors;... Agent: Rader Fishman & Grauer PLLC

20080055995 - Programming non-volatile memory with improved boosting: Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby... Agent: Vierra Magen/sandisk Corporation

20080056002 - Concurrent programming of non-volatile memory: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common... Agent: Vierra Magen/sandisk Corporation

20080056003 - Concurrent programming of non-volatile memory: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common... Agent: Vierra Magen/sandisk Corporation

20080056000 - System for performing data pattern sensitivity compensation using different voltage: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating... Agent: Vierra Magen/sandisk Corporation

20080056001 - System for performing data pattern sensitivity compensation using different voltage: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating... Agent: Vierra Magen/sandisk Corporation

20080056004 - Nand flash memory device and method of manufacturing and operating the same: A NAND flash memory device, and more particularly, to NAND flash memory device and method of manufacturing operating the same as described. A dielectric film and a conduction layer are formed between cell gates so that between-cell gates are buried. Therefore, an interference effect between floating gates, which becomes profound... Agent: Marshall, Gerstein & Borun LLP

20080055977 - Methods, devices and systems for sensing the state of fuse devices: A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the reference fuse. The reference sensor generates a sample clock with a certain threshold transition characteristic in response to the assertion of a sense... Agent: Trask Britt

20080055978 - Nonvolatile semiconductor memory with dummy cell which is absence of a source/drain region: A nonvolatile semiconductor memory according to the present invention includes a memory cell transistor which is disposed in a first region and which has a gate electrode of a stacked structure, and a dummy cell which is disposed in a second region neighboring the first region and which has a... Agent: Amin, Turocy & Calvin, LLP

20080055983 - Semiconductor memory device comprising controllable threshold voltage dummy memory cells: An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines... Agent: Stanley P. Fisher Reed Smith LLP

20080056005 - Non-volatile memory cell read failure reduction: The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method... Agent: Brooks, Cameron & Huebsch , PLLC

20080056006 - Flash memory device and method for programming multi-level cells in the same: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in... Agent: Volentine & Whitt PLLC

20080056007 - Flash memory device using program data cache and programming method thereof: A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation... Agent: Volentine & Whitt PLLC

20080056008 - Reducing read failure in a memory device: Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080056009 - Method of programming non-volatile memory: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate... Agent: Jianq Chyun Intellectual Property Office

20080056010 - Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current: Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes... Agent: Blakely Sokoloff Taylor & Zafman

20080056011 - Semiconductor device: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080056012 - Method for prioritized erasure of flash memory: A method for prioritized erasure of a non-volatile storage device, the method including the steps of: providing at least one flash unit of the storage device, wherein each flash unit has a plurality of blocks; writing data into the plurality of blocks; assigning an erasure-priority to each block, wherein the... Agent: Mark M. Friedman

20080056013 - Method and related apparatus capable of improving endurance of memory: A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells,... Agent: North America Intellectual Property Corporation

20080056023 - Nonvolatile memory device and related methods of operation: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of... Agent: Volentine & Whitt PLLC

20080056014 - Memory device with emulated characteristics: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.... Agent: Zilka-kotab, PC

20080056017 - Data output apparatus, memory system, data output method, and data processing method: A data output apparatus converts input data into data that changes less than the input data, and outputs the converted data to a memory.... Agent: Fitzpatrick Cella Harper & Scinto

20080056019 - Latency signal generator and method thereof: A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit... Agent: Harness, Dickey & Pierce, P.L.C

20080056015 - Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory: An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg... Agent: Schneck & Schneck

20080056016 - Semiconductor memory device: A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives... Agent: Blakely Sokoloff Taylor & Zafman

20080056020 - Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory: An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg... Agent: Schneck & Schneck

20080056018 - Semiconductor memory device and method of inputting/outputting data: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit... Agent: Harness, Dickey & Pierce, P.L.C

20080056021 - Semiconductor memory and system: A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line... Agent: Arent Fox LLP

20080056022 - Phase-change random access memory employing read before write for resistance stabilization: An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20080056024 - Device and method for reading out memory information: A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to... Agent: Dickstein Shapiro LLP

20080056025 - Semiconductor storage device: Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080056026 - System and memory for sequential multi-plane page memory operations: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20080056027 - Read strobe feedback in a memory system: A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080056028 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a plurality of data pieces input in succession in response to... Agent: Mcdermott Will & Emery LLP

20080056029 - Memory control circuit and method: A memory control circuit includes: a phase detection module for detecting a phase difference between a data strobe signal and a clock signal; a control module, coupled to the phase detection module, for generating a set of control signals according to the phase difference, where the set of control signals... Agent: North America Intellectual Property Corporation

20080056030 - Semiconductor memory device with delay locked loop: It is provided a semiconductor device with the ability to carry out data output operation using a reference clock of which the duty cycle is substantially 50%. The semiconductor device includes a clock buffer for receiving the external clock to generate an internal clock; a delay locked loop circuit for... Agent: Mcdermott Will & Emery LLP

20080056031 - Semiconductor memory: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell... Agent: Foley And Lardner LLP Suite 500

20080056033 - Semiconductor memory device: A semiconductor memory device includes a delay time selecting portion for outputting, as a final read/write command, an internal read/write command that corresponds to an external read/write command and is synchronized with an external clock rising edge at a tRCD time without any delay when an address is applied before... Agent: Mills & Onello LLP

20080056032 - Test method for semiconductor memory device and semiconductor memory device therefor: The present invention detects a sense amplifier having an unbalanced characteristic. In a test method for a semiconductor memory device for detecting a sense amplifier having an unbalanced characteristic, an intermediate potential having different H and L levels from normal operation is restored in a first memory cell of a... Agent: Arent Fox LLP

20080056034 - Redundancy program circuit and methods thereof: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control... Agent: Harness, Dickey & Pierce, P.L.C

20080056035 - Method and apparatus for adaptive programming of flash memory, flash memory devices, and systems including flash memory having adaptive programming capability: A flash memory device, a system including a flash memory device, a method for operating a flash memory cell, and an apparatus for operating a flash memory cell include applying a first bit line voltage to a bit line coupled to the cell, applying a first test voltage to a... Agent: Dickstein Shapiro LLP

20080056036 - Semiconductor memory device: A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS timing test signal. The RAS timing controller generates... Agent: Blakely Sokoloff Taylor & Zafman

20080056037 - Dram bit line precharge voltage generator: A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control... Agent: Oliff & Berridge, PLC

20080056038 - Semiconductor memory device: A semiconductor memory device is able to control a timing of an auto-precharge operation. The semiconductor memory device includes a timing controller and an auto-precharge controller. The timing controller generates timing control signals to be used for controlling a timing of an auto-precharge operation based on control signals inputted from... Agent: Mcdermott Will & Emery LLP

20080056039 - Sense amplifier, semiconductor memory device including the same, and data sensing method: A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to... Agent: F. Chau & Associates, LLC

20080056040 - Memory device having function of detecting bit line sense amp mismatch: Provided is a memory device that can detect a mismatch in a bit line sense amp, wherein the memory device includes a sense amp drive unit for selectively supplying a pull-up drive voltage or a pull-down drive voltage to a bit line sense amp in response to a sensing test... Agent: Blakely Sokoloff Taylor & Zafman

20080056041 - Memory circuit: A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080056042 - Storage capacity optimization in holographic storage media: Methods and systems are provided for storing data holographically. Multiple distinct data packets are received. The data packets are stored on a temporary data storage. Data that includes the data packets are written holographically during a single write session to a photopolymer storage medium by optically interfering an optical data... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20080056043 - Methods and apparatus to provide refresh for global out of range read requests: Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address... Agent: Texas Instruments Incorporated

20080056044 - Semiconductor device and fabrication method thereof: The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second... Agent: Arent Fox LLP

20080056046 - Apparatus and method for self-refreshing dynamic random access memory cells: A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080056045 - Device for refreshing memory contents: A device is disclosed for refreshing memory contents of first and second memory cells, wherein the memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time, having a... Agent: Slater & Matsil, L.L.P.

20080056047 - Method, apparatus, and system for active refresh management: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount... Agent: Kacvinsky LLC C/o Intellevate

20080056048 - Power gating circuit, system on chip circuit including the same and power gating method: A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three... Agent: F. Chau & Associates, LLC

20080056049 - Method for powering an electronic device and circuit: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating... Agent: Freescale Semiconductor, Inc. Law Department

20080056050 - Semiconductor memory device: A semiconductor memory device 100 is proposed including an internal address generation circuit 3, a first internal address control signal generation part 4, a second internal address control signal generation part 11, and an internal address control signal selection circuit 10 having an OR gate transistor 12. The internal address... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080056051 - Memory with memory banks and mode registers and method of operating a memory: Memory with at least two memory banks each having memory cells, a control circuit, and at least one bank mode register, wherein the bank mode register stores information about an operation mode of a memory bank, wherein the control circuit operates at least one of the memory banks according to... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080056052 - Global bit select circuit interface with dual read and write bit line pairs: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.... Agent: International Business Machines Corporation

20080056053 - Word line control method to improve read margin and write margin for embedded memories: Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the access cycle and to apply the further voltage to a further word line... Agent: Schwegman, Lundberg & Woessner / Infineon

20080056054 - Methods and apparatus to provide refresh for local out of range read requests to a memory device: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to... Agent: Texas Instruments Incorporated

20080056055 - Semiconductor memory device: A semiconductor memory device includes memory cells, word lines connected to the memory cells, word driver circuits for driving the word lines, a decoder circuit group including a plurality of decoder circuits outputting a decoder signal for selecting at least one of the word driver circuits, decoder lines connecting the... Agent: Arent Fox LLP

20080056056 - Semiconductor memory device and its driving method: A semiconductor memory device includes an address latch unit, a decoding circuit, and a precharge control unit. The address latch unit provides a latched address during an active operation interval and a precharge operation interval. The decoding circuit decodes an output of the address latch unit to provide a decoded... Agent: Blakely Sokoloff Taylor & Zafman

20080056057 - Synchronous semiconductor memory device: A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals... Agent: Volentine & Whitt PLLC