Static information storage and retrieval inventions 02/08

20080049483 - Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage: In a semiconductor integrated circuit device including a nonvolatile memory device and a semiconductor integrated circuit board which are mounted on a wiring board where the nonvolatile memory is enable to electrically program data therein at a first voltage and the semiconductor integrated circuit board is operable at a second... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080049484 - Semiconductor memory device where write and read disturbances have been improved: A data write transfer gate and a write driver transistor are connected to a data latch circuit for storing data, thereby producing a write data path. The data path is controlled by a word line and a data write bit line. In addition, a read drive transistor and a read... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080049485 - Semiconductor memory device: A write voltage source is capable of applying a write voltage, which is a high voltage. An antifuse is connected at one end to the write voltage source and has a resistance irreversibly variable based on the write voltage. A sense node is connectable to the other end of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080049482 - Compare circuit for a content addressable memory cell: A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080049481 - Semiconductor device: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such... Agent: Miles & Stockbridge PC

20080049486 - Transistor, memory cell array and method for forming and operating a memory device: A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and is addressable by selecting two word lines and a bit line is disclosed. For minimizing... Agent: Dicke, Billig & Czaja

20080049487 - Semiconductor memory device: A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line... Agent: Morrison & Foerster LLP

20080049488 - Spin-transfer based mram with reduced critical current density: A magnetic random access memory device comprises a spin torque MRAM cell (100) having a reduced switching current (Ic) wherein standard materials may be used for a free layer (108). A fixed magnetic element (112) polarizes electrons passing therethrough, and the free magnetic element (108) having a first plane anisotropy... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080049489 - Multi-bit spin memory: A multi-state spin based memory cell uses a pair of ferromagnetic layers. A first ferromagnetic layer can be set to any known state k from a set of n different states by adjusting a magnetic orientation of such layer. The relationship of the first ferromagnetic layer and a second magnetic... Agent: J. Nicholas Gross, Attorney

20080049490 - Phase-change memory device, phase-change channel transistor, and memory cell array: To reduce the voltage required to cause a phase transition from an amorphous phase to a crystalline phase, a phase-change memory device (1) comprises: a first electrode (6); a second electrode (8); and a memory layer (14) provided between the first (6) and second (8) electrodes, wherein the memory layer... Agent: Staas & Halsey LLP

20080049491 - Electromechanical non-volatile memory device and method of manufacturing the same: In a memory device and a method of manufacturing the memory device, the memory device includes first and second electrode patterns formed on a substrate. An insulating layer pattern and a third electrode pattern are successively formed on the substrate. The third electrode pattern extends to be apart from upper... Agent: Mills & Onello LLP

20080049492 - Spin memory with write pulse: An electron spin-based memory cell has a first ferromagnetic layer with a changeable magnetization state and a second ferromagnetic layer with a fixed magnetization state. A non-volatile logic state of such cell is dependent on a relationship between said first ferromagnetic layer and said second ferromagnetic layer, including whether said... Agent: J. Nicholas Gross, Attorney

20080049493 - Flash memory device and erasing method thereof: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of... Agent: F. Chau & Associates, LLC

20080049494 - Reducing effects of program disturb in a memory device: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage.... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20080049496 - Method for modifying data more than once in a multi-level cell memory location within a memory array: A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in... Agent: Dickstein Shapiro LLP

20080049497 - Methods of programming multi-bit flash memory devices and related devices: Methods of programming a multi-bit non-volatile memory device are provided. The multi-bit non-volatile memory device includes a memory cell array including a plurality of memory cells and a storage unit electrically coupled to the memory cell array. A first bit (FB) of multi-bit data is programmed from the storage unit... Agent: Myers Bigel Sibley & Sajovec

20080049498 - Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency: Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080049499 - Block status storage unit of flash memory device: A flash memory device includes: a memory cell array including pluralities of blocks; a block status storage unit including pluralities of latch cells arranged in rows and columns to store block status information signals corresponding to each of the blocks and providing the block status information signals in response to... Agent: F. Chau & Associates, LLC

20080049501 - Cell array of memory device sharing selection line: The present invention provides a cell array of a flash memory device. The cell array includes a memory cell transistor connected to a word line, a first selection transistor for controlling a first connection between the memory cell transistor and a bit line in response to a selection signal, and... Agent: Volentine & Whitt PLLC

20080049502 - Flash memory device and program method of flash memory device using different voltages: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least... Agent: Volentine & Whitt PLLC

20080049500 - Nonvolatile memory: A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which... Agent: Fish & Richardson P.C.

20080049503 - Nonvolatile storage and erase control: A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not... Agent: Murabito, Hao & Barnes LLP Third Floor

20080049504 - Memory control circuit, nonvolatile storage apparatus, and memory control method: An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing... Agent: Greenblum & Bernstein, P.L.C

20080049505 - Scalable memory system: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues... Agent: Dennis R. Haszko Patent Law Office Of D.r.haszko

20080049506 - Alternate row-based reading and writing for non-volatile memory: A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is... Agent: Vierra Magen/sandisk Corporation

20080049507 - Flash memory device employing disturbance monitoring scheme: A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a disturbed bit line. In a program operation of the flash memory device, a voltage level of the disturbed... Agent: Volentine & Whitt PLLC

20080049509 - Nonvolatile semiconductor memory device and control method thereof: A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a plurality of memory cells connected in series, each of said plurality of memory cells having a control gate, said plurality of memory cells including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080049508 - Nonvolatile semiconductor memory, its read method and a memory card: A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080049510 - Flash memory controller utilizing multiple voltages and a method of use: A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high... Agent: Sawyer Law Group LLP

20080049511 - Method of programming cells of a nand memory device: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080049495 - Method, apparatus and system relating to automatic cell threshold voltage measurement: Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line... Agent: Trask Britt, P.C./ Micron Technology

20080049514 - Memory device with a managing microprocessor system and an architecture of fail search and automatic redundancy: An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080049513 - Method and apparatus for programming non-volatile data storage device: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel... Agent: Sughrue Mion, PLLC

20080049512 - Nonvolatile memory device and method of programming the same: A method for conducting programming and erasure of charge-trapped memory devices includes: conducting at least one program/erase cycle of a charge-trapped memory device on the basis of a given threshold voltage of the charge-trapped memory device as a reference point; determining a wear-level of the erasing procedure; shifting the reference... Agent: Edell, Shapiro & Finnan, LLC

20080049515 - Semiconductor memory device: Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and... Agent: Mcginn Intellectual Property Law Group, PLLC

20080049516 - Flash memory device having improved program rate: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory... Agent: Harrity & Snyder, L.L.P.

20080049517 - Multi-level non-volatile memory and manufacturing method thereof: A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between... Agent: Jianq Chyun Intellectual Property Office

20080049518 - Nand flash memory programming: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices... Agent: Schwegman, Lundberg & Woessner, P.A.

20080049519 - Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current: Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes... Agent: Blakely Sokoloff Taylor & Zafman

20080049520 - Flash memory system and programming method performed therein: Provided are a flash memory system and a programming method performed in the flash memory system. The flash memory system includes a buffer unit including a plurality of buffers, and temporarily storing data transmitted by a host; a plurality of channel units each including at least one flash memory chip... Agent: Sughrue Mion, PLLC

20080049521 - Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080049522 - Content addressable memory entry coding for error detection and correction: A Content Addressable Memory (CAM) or Ternary CAM (TCAM) provides error detection and correction (EDAC). EDAC codes are chosen based on logical and physical properties of the CAM/TCAM. An entry in the CAM/TCAM comprises a plurality of groups, each group comprising a plurality of storage bits. Writes to the storage... Agent: Marger Johnson & Mccollom, P.C.

20080049523 - Line defect detection circuit for detecting weak line: Example embodiments relate to a line defect detection circuit, including a first driver disposed at one end of a line and configured to drive the line using a first voltage or a second voltage in response to a control signal, and a second driver disposed at the other end of... Agent: Lee & Morse, P.C.

20080049524 - Logic cell protected against random events: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080049526 - Semiconductor memory device with data and local redundancy memory cell arrays, and redundancy method thereof: A semiconductor memory device includes both a data redundancy memory cell array and a local redundancy memory cell array. Cells of the data redundancy memory cell array and/or cells the local redundancy memory cell arrays may be substituted for one or more defective cells of a normal memory cell array,... Agent: Marger Johnson & Mccollom, P.C.

20080049525 - Integrated semiconductor memory and method for operating an integrated semiconductor memory: In an embodiment, an integrated semiconductor memory includes a plurality of data lines via which data read out or to be read out from memory cells can be communicated, wherein the data lines comprise redundant data lines and non-redundant data lines, wherein the semiconductor memory has at least one data... Agent: Slater & Matsil, L.L.P.

20080049527 - Method for testing memory device: Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device... Agent: Ladas & Parry LLP

20080049528 - Bit line sense amplifier of semiconductor memory device having open bit line structure: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a... Agent: Marger Johnson & Mccollom, P.C.

20080049530 - Equalizer circuit and method of controlling the same: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect... Agent: Mcginn Intellectual Property Law Group, PLLC

20080049529 - Semiconductor memory device: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to the gates of the memory cells; bit lines connected to the drains of the plurality of memory cells; sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080049531 - Memory arrangement and method for operating such a memory arrangement: A memory arrangement and method of operating a memory arrangement is disclosed. In one embodiment of the memory arrangement according to the invention, rewritable memory cells are arranged at crossovers between word lines and bit lines, said memory cells being configured in such a manner that the information stored in... Agent: Dicke, Billig & Czaja

20080049532 - Semiconductor memory device and refresh control method thereof: A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is permitted while retaining... Agent: Sughrue Mion, PLLC

20080049533 - Supply voltage distribution system with reduced resistance for semiconductor devices: A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising: a first supply voltage distribution line arrangement and a second supply voltage distribution line arrangement, said first supply voltage distribution line arrangement and said second supply voltage distribution line arrangement... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080049534 - Voltage controlled static random access memory: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines(WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities.... Agent: Downs Rachlin Martin PLLC

20080049535 - Semiconductor memory device, rewrite processing method therefor, and program thereof: A comparing unit (12) in a readout control unit (11) compares one bit data stored in a memory body (20) with a value stored in a data storage unit B[m] which is prepared to store the one bit data. The data storage unit B[m] includes three memory cells MC[k] and... Agent: Wenderoth, Lind & Ponack L.L.P.

20080049536 - Semiconductor memory device and semiconductor device comprising the same: A semiconductor memory device comprises a plurality of input/output (I/O) ports, a plurality of memory cell arrays and a region configurator. The region configurator is adapted to hold share region information about at least one share region. In the memory cell arrays, at least one share region accessible through the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080049539 - Semiconductor memory device: Disclosed is a word line driving circuit which includes a first MOS transistor and a second MOS transistor having mutually different conductivity types and a third MOS transistor of a conductivity type which is the same as that of the first MOS transistor. Gates of the first and second MOS... Agent: Young & Thompson

20080049538 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit configured to includes fuses and anti-fuses integrated; an address switching circuit configured to produce a second internal address on the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080049537 - 1-transistor type dram cell, a dram device and manufacturing method therefore, driving circuit for dram, and driving method therefor: The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing... Agent: Ladas & Parry LLP

20080049540 - Semiconductor memory device comprising data path controller and related method: A semiconductor memory device and a related method are disclosed. The semiconductor memory device includes a data sensing output unit simultaneously providing first and second data to first and second data path lines, respectively; and a data output circuit, wherein the first and second data are serially output to an... Agent: Volentine & Whitt PLLC

20080049541 - Semiconductor memory device: A semiconductor memory device includes an FIFO block connected to a data input/output terminal DQ, a time-division transfer circuit that inputs and outputs in parallel n-bit data inputted and outputted continuously via the data input/output terminal DQ, a data bus RWBS that performs a data transfer between the time-division transfer... Agent: Scully Scott Murphy & Presser, PC

20080049542 - Address counter for nonvolatile memory device: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080043508 - Method for programming one-time programmable memory of integrated circuit: A method for programming a one-time programmable memory of an integrated circuit includes the following steps: writing an instruction set into the one-time programmable memory via a first programmable interface, running a programmable self-instruction of the instruction set, and writing a proofreading value of the integrated circuit into the one-time... Agent: Hdsl

20080043509 - Memory device using antifuses: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native... Agent: Mcandrews Held & Malloy, Ltd

20080043510 - Semiconductor memory device containing antifuse write voltage generation circuit: A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which... Agent: Arent Fox LLP

20080043507 - Content addressable memory with twisted data lines: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of the CAM cells, each pair of data lines including at least one data line that is formed by conductive segments disposed in two different... Agent: Shemwell Gregory & Courtney LLP

20080043511 - Autonomous antifuse cell: An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In... Agent: Schneck & Schneck

20080043512 - Non-volatile semiconductor memory: When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read... Agent: Arent Fox LLP

20080043513 - Intergrated circuit having memory with resistive memory cells: A memory device, and method of operating the same, wherein the device includes resistive memory cells being switched between a low-resistive state and a high-resistive state; an evaluation unit, being coupled to a resistive memory cell to determine a resistive state of the resistive memory cell; and a voltage regulation... Agent: Dicke, Billig & Czaja

20080043514 - Semiconductor memory having resistance change element: A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043515 - Electrochemical memory device: s

20080043516 - Non-volatile, static random access memory with regulated erase saturation and program window: A system and method for regulating the erase saturation in a semiconductor memory is disclosed. More particularly, the present invention measures the under-erase and over-erase condition of all SONOS transistors in an array of non-volatile SRAM cells and corrects the erase voltage to prevent over-erase and under-erase.... Agent: Holme Roberts & Owen, LLP

20080043519 - Magnetic memory element, magnetic memory having said magnetic memory element, and method for driving magnetic memory: An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043518 - Magentic memory device and method of magnetization reversal of the magnetization of at least one magnetic memory element: Method of magnetization reversal of the magnetization (M) of at least one first magnetic memory element of an array of magnetic memory elements comprising the steps of: applying a first magnetic field pulse to a first set of magnetic memory elements, and applying a second magnetic field pulse to a... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080043517 - Memory device: A memory device includes a memory element, a first wiring and a second wiring. The memory element includes a memory layer retaining information based on a magnetization state of a magnetic material and a magnetization pinned layer in which a magnetization direction is pinned and which is provided for the... Agent: Bell, Boyd & Lloyd, LLP

20080043521 - Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell: A method of determining the memory state of a resistive memory cell including a first electrode, a second electrode and an active material being arranged between the first electrode and the second electrode, comprises generating a read capacity by applying a voltage between the first electrode and the second electrode,... Agent: Slater & Matsil LLP

20080043520 - I-shaped phase change memory cell with thermal isolation: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080043522 - Nonvolatile semiconductor memory device and phase change memory device: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a... Agent: Mcdermott Will & Emery LLP

20080043523 - Control and testing of a micro electromechanical switch: A circuit includes a micro electro mechanical switch and a detection circuit. The micro electro mechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact in response to an electrostatic force provided by a top activation electrode and... Agent: Freescale Semiconductor, Inc. Law Department

20080043524 - Semiconductor memory device: A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043526 - Operating techniques for reducing program and read disturbs of a non-volatile memory: The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080043527 - Non-volatile memory with both single and multiple level cells: Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices... Agent: Brooks, Cameron & Huebsch , PLLC

20080043528 - Semiconductor storage device provided with memory cell having charge accumulation layer and control gate: A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043530 - Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080043529 - Novel multi-state memory: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080043531 - Non-volatile semiconductor memory device: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043532 - Semiconductor memory device, semiconductor device, and data write method: A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives the data held at the address from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043533 - Nand flash memory: A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043534 - Memory system and data writing method: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043535 - Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080043536 - Non-volatile memory device and method of programming same: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage... Agent: Volentine & Whitt PLLC

20080043525 - Bit cell reference device and methods thereof: A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a... Agent: Larson Newman Abel Polansky & White, LLP

20080043538 - Non-volatile semiconductor storage device and word line drive method: The present invention provides a non-volatile semiconductor storage device which includes word lines used as control gates of memory cells; a pre-decoder which generates pre-decode signals; a main decoder which generates main decode signals; and a sub-decoder. The sub-decoder is equipped with pull-up power lines whose potentials are controlled by... Agent: Mcginn Intellectual Property Law Group, PLLC

20080043537 - Semiconductor nonvolatile memory: In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and... Agent: Volentine & Whitt PLLC

20080043539 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory for suppressing the access delay due to the parasitic capacitance between bit lines is disclosed. Bit lines are selected by a bit select signal, and the data of the memory cell selected in accordance with the level of data lines by a sense amplifier are read,... Agent: Volentine & Whitt PLLC

20080043541 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent: Frommer Lawrence & Haug

20080043540 - Multilevel driver: The present disclosure includes various method, device, and system embodiments for multilevel driving of rowlines and/or wordlines. One such method embodiment includes supplying a first power voltage (V1) and a second power voltage (V2) that is greater than V1, to the driver circuit. The method includes supplying a first boost... Agent: Brooks, Cameron & Huebsch , PLLC

20080043542 - Static random access memory device having reduced leakage current during active mode and a method of operating thereof: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control... Agent: Texas Instruments Incorporated

20080043543 - Method for manufacturing, writing method and reading non-volatile memory: A method of manufacturing, programming and reading a non-volatile memory is provided. First, a to-be-coded memory having a plurality of to-be-coded cells arranged in a array is provided. Next, an implanting resist layer is formed on the to-be-coded memory. Then, a mask is disposed on the to-be-coded memory, wherein the... Agent: Bacon & Thomas, PLLC

20080043544 - Memory device and method of improving the reliability of a memory device: A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated... Agent: Slater & Matsil LLP

20080043546 - Method of controlling a memory device having a memory core: Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored... Agent: Deniro/rambus

20080043545 - Multiple data rate ram memory controller: A memory controller for a multiple data rate RAM memory module is provided. Said controller comprises a PLL unit (PLL) for generating different clock phases (clk, clk90, clk180) from a reference clock (ref clk). In addition, a controllable delay unit (CDU) for delaying a strobe signal (dqs) is provided.... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080043547 - Latency control circuit and method using queuing design method: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal... Agent: Marger Johnson & Mccollom, P.C.

20080043548 - Semiconductor memory device for stack package and read data skew control method thereof: A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point... Agent: F. Chau & Associates, LLC

20080043551 - Electrical fuse circuit, memory device and electronic part: An electrical fuse circuit including: a capacitor composing an electrical fuse; a write circuit breaking an insulating film of the capacitor by applying voltage to between both terminals of the capacitor in accordance with a write signal; and a precharge circuit precharging with respect to the terminal of the capacitor,... Agent: Arent Fox LLP

20080043549 - Semiconductor memory apparatus and method of controlling the same: A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether general cells corresponding to input addresses are repaired or not and activate the redundant cells, decoding units configured to decode a refresh address... Agent: Venable LLP

20080043550 - Semiconductor memory device: A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043552 - Integrated circuit: An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an LSI tester by the use of a read command and for outputting write data to the LSI tester by... Agent: Arent Fox LLP

20080043553 - Semiconductor memory device and method of testing the same: A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080043554 - Semiconductor memory device realizing high-speed access: In data read, a single read global bit line is shared with a plurality of local bit lines.... Agent: Steptoe & Johnson LLP

20080043555 - Timing control for sense amplifiers in a memory circuit: An integrated circuit 18 includes a memory 20 having timing circuitry formed of a global controller 26 and a self-timing path for triggering the sense amplifiers 28 to read bit lines 30 within the array of bit cells 24. The self timing path includes timing cells 34 embedded within the... Agent: Nixon & Vanderhye, PC

20080043556 - Dynamic power control of a memory device thermal sensor: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the... Agent: Intel Corporation C/o Intellevate, LLC

20080043557 - Semiconductor devices the include a fuse part including an antifuse and protection circuit: A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal... Agent: Myers Bigel Sibley & Sajovec

20080043558 - Securing an integrated circuit: Securing an integrated circuit, including fabricating the integrated circuit so that the integrated circuit includes at least one efuse that is intended to be always blown during operation of the integrated circuit and the integrated circuit includes security circuitry capable of blowing the efuse and of performing other security related... Agent: Ibm (roc-blf)

20080043560 - Dual mode sram architecture for voltage scaling and power management: The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM... Agent: Texas Instruments Incorporated

20080043559 - Memory power management: Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the charge pumps being configured to provide at least two voltages. Logic is configured to control how the voltages are delivered to... Agent: Unity Semiconductor Corporation

20080043561 - Circuit for an sram with reduced power consumption: A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit... Agent: Slater & Matsil, L.L.P.

20080043562 - Power management of memory via wake/sleep cycles: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then... Agent: Network Appliance/blakely

20080043563 - Flexibly controlling the transfer of data between input/output devices and memory: Data transfer between input/output devices and memory is controlled. Data transfer begins under the control of one control block, and control of the data transfer is passed from the one control block to another control block, in response to transferring an amount of data specified in the one control block.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080043564 - Semiconductor memory device including distributed data input/output lines: Example embodiments are directed to a semiconductor memory device having a hierarchical input/output (I/O) line structure. The semiconductor memory device may include a plurality of core blocks, with each core block including a plurality of memory banks sharing an input/output sense amplifier. Data input/output lines may be arranged on each... Agent: Harness, Dickey & Pierce, P.L.C

20080043565 - Memory device and method having multiple address, data and command buses: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080043566 - Latency counter: A latency counter includes: a point-shift type FIFO circuit having plural latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and having an internal command MDRDT supplied in common to the input gates; and a selector that makes any one of the input... Agent: Young & Thompson

20080037307 - Non-volatile memory erase verify: A memory device having memory cells fabricated in a substrate well is described. The memory device includes control circuitry to perform an erase operation on the memory cells and a voltage bias circuit to bias the substrate well to a positive voltage level during an erase verification operation of memory... Agent: Schwegman, Lundberg & Woessner, P.A.

20080037309 - Semiconductor memory device: Disclosed is a semiconductor memory device in which two sorts of series-connected transfer gates, that is, even-numbered and odd-numbered transfer gates are provided in series with each other between the ends of neighboring bit lines of a memory cell array connecting to bit lines of a sense amplifier. A first... Agent: Sughrue Mion, PLLC

20080037311 - Semiconductor memory device: Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080037308 - Fixed write-protect seamless memory card: In an embodiment of the present invention, a memory card includes a bottom plastic piece having a plurality of lateral sides, one of which includes a notch, and a cavity interposed along the lateral sides. A printed circuit board (PCB) assembly, including memory, is positioned in the cavity. A fin-structure... Agent: Law Offices Of Imam

20080037310 - Semiconductor memory device and connection method thereof: A semiconductor memory device comprising a substrate, a memory electrically connected to the substrate, a first and a second transmission/reception units transmitting a signal supplied by the memory and receiving a signal to be supplied to the memory, both arranged on a surface of the substrate, a branch circuit which... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20080037312 - Ferroelectric memory: A ferroelectric memory includes: a memory cell having a ferroelectric capacitor, wherein, in a read-out operation, a first signal Q1 is given when a first voltage is applied to the ferroelectric capacitor, and a second signal Q2 is given when a second voltage having an identical magnitude as a magnitude... Agent: Harness, Dickey & Pierce, P.L.C

20080037313 - Configurable sram system and method: A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example,... Agent: Downs Rachlin Martin PLLC

20080037314 - Magnetic memory: A magnetic memory includes a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and a word line electrically connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080037315 - Thin film magnetic memory device writing data with bidirectional current: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets... Agent: Mcdermott Will & Emery LLP

20080037316 - Multi-valued logic/memory cells and methods thereof: A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to the tunnel diodes and... Agent: Nixon Peabody LLP - Patent Group

20080037317 - Resistive memory device: A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a control transistor having a gate, a first terminal, and a second terminal. The first terminal of the access... Agent: Fletcher Yoder (micron Technology, Inc.)

20080037318 - Thin film magnetic memory device having redundant configuration: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is... Agent: Mcdermott Will & Emery LLP

20080037319 - Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance: The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080037320 - Flash memory with multi-bit read: A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2X logic levels to store X data bits and an error bit. At least one extra bit provided during... Agent: Schwegman, Lundberg & Woessner, P.A.

20080037321 - Partial-write-collector algorithm for multi level cell (mlc) flash: A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write... Agent: Law Offices Of Imam

20080037322 - Semiconductor memory having electrically erasable and programmable semiconductor memory cells: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080037323 - Semiconductor integrated circuit and nonvolatile memory element: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080037324 - Electrical thin film memory: A memory device includes a layer of material structure and a plurality of memory cells each formed using a corresponding different portion of the layer. Each memory cell is constructed and designed to change a material property of the corresponding portion of the layer upon application of an electrical write... Agent: Fish & Richardson PC

20080037326 - Xip flash memory device and program method: A memory cell in flash memory device is provided which includes a memory cell transistor having a control gate coupled to a word line and a drain coupled to a bit line; and a selection transistor for connecting a source of the memory cell transistor and a common source line... Agent: Volentine & Whitt PLLC

20080037325 - On-chip ee-prom programming waveform generation: Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges... Agent: Townsend And Townsend And Crew, LLP

20080037327 - Memory devices and methods using selective self-boost programming operations: In a flash memory device, different self-boosting techniques are selectively applied to a string of serially connected memory cells responsive to a programming voltage applied to a selected word line. For example, non-local self-boosting and local self-boosting may be selectively applied responsive to the programming voltage applied to the selected... Agent: Myers Bigel Sibley & Sajovec

20080037328 - Semiconductor memory device: A memory device including a memory cell array with information cells and reference cells arranged and a sense amplifier configured to sense data stored in the memory cell array, wherein the sense amplifier has a latch-type of differential amplifier configured to detect a current difference between a selected information cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080037329 - Nonvolatile semiconductor memory, method for reading the same, and microprocessor: A nonvolatile semiconductor memory that improved a read rate. In a memory cell array in which each memory cell includes two storage areas, thresholds of outer storage areas of two memory cells which are symmetrical with respect to two adjacent bit lines are set so as to create a pair... Agent: Arent Fox LLP

20080037330 - Ramp gate erase for dual bit flash memory: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than... Agent: Eschweiler & Associates, LLC National City Bank Building

20080037331 - Non-volatile memory device and associated method of erasure: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation... Agent: Volentine & Whitt PLLC

20080037332 - Semiconductor storage device and electronic equipment: A semiconductor storage device is capable of discriminating information stored in memory cells with high accuracy even if a gap that separates distributions of cell current values between data 0 and data 1 among a plurality of memory cells in a memory cell array becomes extremely narrow or overlapped with... Agent: Birch Stewart Kolasch & Birch

20080037333 - Memory device with separate read and write gate voltage controls: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line... Agent: F. Chau & Associates, LLC

20080037334 - Semiconductor device having output buffer initialization circuit and output buffer initialization method: A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output... Agent: F. Chau & Associates, LLC

20080037335 - Semiconductor memory device: The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAM 1 has word lines 101 to 10n, word lines 22 and 24, memory cells 301 to 30n... Agent: Mcginn Intellectual Property Law Group, PLLC

20080037336 - Semiconductor memory device: A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the... Agent: Mcdermott Will & Emery LLP

20080037337 - Semiconductor memory: A semiconductor memory includes a plurality of memory cells, each of which includes a first inverter connected to one of high-data retaining supply lines which constitute one of high-data retaining supply line pairs corresponding to the memory cell and a second inverter connected to the other one of the high-data... Agent: Mcdermott Will & Emery LLP

20080037338 - Self-timing circuit with programmable delay and programmable accelerator circuits: A memory has a novel self-timing circuit that generates internal memory control signals. Control signals may include an address latch enable signal, a decoder enable signal, and a sense amplifier enable signal. The circuit has a timing loop whose timing mimics the timing of an access of the real memory.... Agent: Qualcomm Incorporated

20080037342 - Apparatus and method for repairing a semiconductor memory: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores... Agent: Trask Britt, P.C./ Micron Technology

20080037340 - Apparatus for testing a memory of an integrated circuit: An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.... Agent: International Business Machines Corporation Dept. 18g

20080037341 - Enabling memory redundancy during testing: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory... Agent: International Business Machines Corporation Dept. 18g

20080037339 - Memory array for an integrated circuit: A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant... Agent: International Business Machines Corporation Dept. 18g

20080037343 - Memory having sense time of variable duration: In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is... Agent: Freescale Semiconductor, Inc. Law Department

20080037344 - Semiconductor memory and memory system: Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection... Agent: Arent Fox LLP

20080037345 - High-speed, self-synchronized current sense amplifier: A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node.... Agent: Schneck & Schneck

20080037346 - Memory array with a delayed wordline boost: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a... Agent: Texas Instruments Incorporated

20080037347 - Electronic device, format discrimination system and format discrimination method: [Means for Solving the Problems] The electronic device comprises a socket (2) for mounting a memory card (1), an I/F unit (3) for reading data from the memory card (1) mounted in the socket (2), a detector (4) for detecting a difference between the position of the boundary of blocks... Agent: Mcdermott Will & Emery LLP

20080037348 - Method for adjusting programming/erasing time in memory system: A method for adjusting a programming/erasing time in a memory system is disclosed. In one embodiment, a programming/erasing step is executed for writing data into the memory system, wherein the programming/erasing step is executed until a programming/erasing time and/or a cycle number per unit of time is reached. Then, a... Agent: Beedar Technology Inc.

20080037349 - Ultra low-cost solid-state memory: A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or... Agent: Hitachi Global Storage Technologies, Inc.

20080037351 - Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features: An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080037350 - Method and apparatus for in-system redundant array repair on integrated circuits: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing... Agent: Scully, Scott, Murphy & Presser, P.C.

20080037352 - Combo semiconductor memory apparatus: A combo semiconductor memory apparatus capable of reducing current and power consumption is provides. The semiconductor memory apparatus includes: a signal generator that generates a voltage control signal according to the level of an external voltage; and a voltage generator that pumps up the level of the external voltage in... Agent: Venable LLP

20080037353 - Interface circuit system and method for performing power saving operations during a command-related latency: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at... Agent: Zilka-kotab, PC

20080037354 - Word line voltage control circuit for memory devices: A memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines, and coupled between a power line and a ground line. A word line decoder is coupled to one end of the word line for selecting... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080037355 - Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load: A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080037356 - Semiconductor memory device: A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit... Agent: Mcginn Intellectual Property Law Group, PLLC

20080037357 - Double-rate memory: A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control... Agent: Freescale Semiconductor, Inc. Law Department

20080037358 - Semiconductor memory device comprising a plurality of static memory cells: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power... Agent: Mcdermott Will & Emery LLP

20080031029 - Semiconductor memory device with split bit-line structure: A semiconductor memory device with split bit-line structure is disclosed to realize compact high-density memory device with high speed. The semiconductor memory device includes a first bit-line coupled to a first memory cell, and a second bit-line coupled to a second memory cell. The first and the second bit-lines are... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080031030 - System and method for power management in memory systems: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit... Agent: Zilka-kotab, PC

20080031031 - Semiconductor integrated circuit and ic card system: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power,... Agent: Miles & Stockbridge PC

20080031032 - Method and apparatus processing variable resistance memory cell write operation: A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As the switchable current blocking device blocks current flow through the variable resistance memory cell, the charge storing element charges.... Agent: Dickstein Shapiro LLP

20080031033 - Method and apparatus for reducing power consumption in a content addressable memory: Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit comprises a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level... Agent: Qualcomm Incorporated

20080031034 - Memory cell comprising a molecular transistor, device comprising a plurality of such cells and method for using same: The memory cell comprises a field effect memory transistor comprising a nanowire covered by a type of memory molecules and an access transistor of the same type. A source of the access transistor is connected to a drain of the memory transistor. The nanowire of the access transistor and the... Agent: Oliff & Berridge, PLC

20080031035 - Thin-film magnetic device with strong spin polarisation perpendicular to the plane of the layers, magnetic tunnel junction and spin valve using such a device: A thin-film magnetic device comprises, on a substrate, a composite assembly deposited by cathode sputtering and consists of a first layer made of a ferromagnetic material with a high rate of spin polarisation, the magnetisation of which is in plane in the absence of any electric or magnetic interaction, a... Agent: Burr & Brown

20080031036 - Semiconductor switching device: A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar transistor is provided... Agent: Timothy M Honeycutt Attorney At Law

20080031037 - Semiconductor memory device: An SRAM cell is formed by five transistors. The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2... Agent: Scully Scott Murphy & Presser, PC

20080031038 - Non-volatile memory and operating method thereof: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge sto